hw/arm/fsl-imx6ul.c

   1 /*
   2  * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
   3  *
   4  * i.MX6UL SOC emulation.
   5  *
   6  * Based on hw/arm/fsl-imx7.c
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qapi/error.h"
  21 #include "qemu-common.h"
  22 #include "hw/arm/fsl-imx6ul.h"
  23 #include "hw/misc/unimp.h"
  24 #include "sysemu/sysemu.h"
  25 #include "qemu/error-report.h"
  26
  27 #define NAME_SIZE 20
  28
  29 static void fsl_imx6ul_init(Object *obj)
  30 {
  31     FslIMX6ULState *s = FSL_IMX6UL(obj);
  32     char name[NAME_SIZE];
  33     int i;
  34
  35     for (i = 0; i < MIN(smp_cpus, FSL_IMX6UL_NUM_CPUS); i++) {
  36         snprintf(name, NAME_SIZE, "cpu%d", i);
  37         object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
  38                                 "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
  39     }
  40
  41     /*
  42      * A7MPCORE
  43      */
  44     sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore),
  45                           TYPE_A15MPCORE_PRIV);
  46
  47     /*
  48      * CCM
  49      */
  50     sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6UL_CCM);
  51
  52     /*
  53      * SRC
  54      */
  55     sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
  56
  57     /*
  58      * GPCv2
  59      */
  60     sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2),
  61                           TYPE_IMX_GPCV2);
  62
  63     /*
  64      * SNVS
  65      */
  66     sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs),
  67                           TYPE_IMX7_SNVS);
  68
  69     /*
  70      * GPR
  71      */
  72     sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr),
  73                           TYPE_IMX7_GPR);
  74
  75     /*
  76      * GPIOs 1 to 5
  77      */
  78     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
  79         snprintf(name, NAME_SIZE, "gpio%d", i);
  80         sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
  81                               TYPE_IMX_GPIO);
  82     }
  83
  84     /*
  85      * GPT 1, 2
  86      */
  87     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
  88         snprintf(name, NAME_SIZE, "gpt%d", i);
  89         sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]),
  90                               TYPE_IMX7_GPT);
  91     }
  92
  93     /*
  94      * EPIT 1, 2
  95      */
  96     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
  97         snprintf(name, NAME_SIZE, "epit%d", i + 1);
  98         sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
  99                               TYPE_IMX_EPIT);
 100     }
 101
 102     /*
 103      * eCSPI
 104      */
 105     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
 106         snprintf(name, NAME_SIZE, "spi%d", i + 1);
 107         sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
 108                               TYPE_IMX_SPI);
 109     }
 110
 111     /*
 112      * I2C
 113      */
 114     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
 115         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
 116         sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
 117                               TYPE_IMX_I2C);
 118     }
 119
 120     /*
 121      * UART
 122      */
 123     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
 124         snprintf(name, NAME_SIZE, "uart%d", i);
 125         sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
 126                               TYPE_IMX_SERIAL);
 127     }
 128
 129     /*
 130      * Ethernet
 131      */
 132     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
 133         snprintf(name, NAME_SIZE, "eth%d", i);
 134         sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]),
 135                               TYPE_IMX_ENET);
 136     }
 137
 138     /*
 139      * SDHCI
 140      */
 141     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
 142         snprintf(name, NAME_SIZE, "usdhc%d", i);
 143         sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]),
 144                               TYPE_IMX_USDHC);
 145     }
 146
 147     /*
 148      * Watchdog
 149      */
 150     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
 151         snprintf(name, NAME_SIZE, "wdt%d", i);
 152         sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
 153                               TYPE_IMX2_WDT);
 154     }
 155 }
 156
 157 static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
 158 {
 159     FslIMX6ULState *s = FSL_IMX6UL(dev);
 160     int i;
 161     qemu_irq irq;
 162     char name[NAME_SIZE];
 163
 164     if (smp_cpus > FSL_IMX6UL_NUM_CPUS) {
 165         error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
 166                    TYPE_FSL_IMX6UL, FSL_IMX6UL_NUM_CPUS, smp_cpus);
 167         return;
 168     }
 169
 170     for (i = 0; i < smp_cpus; i++) {
 171         Object *o = OBJECT(&s->cpu[i]);
 172
 173         object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
 174                                 "psci-conduit", &error_abort);
 175
 176         /* On uniprocessor, the CBAR is set to 0 */
 177         if (smp_cpus > 1) {
 178             object_property_set_int(o, FSL_IMX6UL_A7MPCORE_ADDR,
 179                                     "reset-cbar", &error_abort);
 180         }
 181
 182         if (i) {
 183             /* Secondary CPUs start in PSCI powered-down state */
 184             object_property_set_bool(o, true,
 185                                      "start-powered-off", &error_abort);
 186         }
 187
 188         object_property_set_bool(o, true, "realized", &error_abort);
 189     }
 190
 191     /*
 192      * A7MPCORE
 193      */
 194     object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
 195                             &error_abort);
 196     object_property_set_int(OBJECT(&s->a7mpcore),
 197                             FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL,
 198                             "num-irq", &error_abort);
 199     object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
 200                              &error_abort);
 201     sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
 202
 203     for (i = 0; i < smp_cpus; i++) {
 204         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
 205         DeviceState  *d   = DEVICE(qemu_get_cpu(i));
 206
 207         irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
 208         sysbus_connect_irq(sbd, i, irq);
 209         sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ));
 210     }
 211
 212     /*
 213      * A7MPCORE DAP
 214      */
 215     create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
 216                                 0x100000);
 217
 218     /*
 219      * GPT 1, 2
 220      */
 221     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
 222         static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
 223             FSL_IMX6UL_GPT1_ADDR,
 224             FSL_IMX6UL_GPT2_ADDR,
 225         };
 226
 227         static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = {
 228             FSL_IMX6UL_GPT1_IRQ,
 229             FSL_IMX6UL_GPT2_IRQ,
 230         };
 231
 232         s->gpt[i].ccm = IMX_CCM(&s->ccm);
 233         object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
 234                                  &error_abort);
 235
 236         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0,
 237                         FSL_IMX6UL_GPTn_ADDR[i]);
 238
 239         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
 240                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 241                                             FSL_IMX6UL_GPTn_IRQ[i]));
 242     }
 243
 244     /*
 245      * EPIT 1, 2
 246      */
 247     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
 248         static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
 249             FSL_IMX6UL_EPIT1_ADDR,
 250             FSL_IMX6UL_EPIT2_ADDR,
 251         };
 252
 253         static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = {
 254             FSL_IMX6UL_EPIT1_IRQ,
 255             FSL_IMX6UL_EPIT2_IRQ,
 256         };
 257
 258         s->epit[i].ccm = IMX_CCM(&s->ccm);
 259         object_property_set_bool(OBJECT(&s->epit[i]), true, "realized",
 260                                  &error_abort);
 261
 262         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0,
 263                         FSL_IMX6UL_EPITn_ADDR[i]);
 264
 265         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
 266                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 267                                             FSL_IMX6UL_EPITn_IRQ[i]));
 268     }
 269
 270     /*
 271      * GPIO
 272      */
 273     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
 274         static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
 275             FSL_IMX6UL_GPIO1_ADDR,
 276             FSL_IMX6UL_GPIO2_ADDR,
 277             FSL_IMX6UL_GPIO3_ADDR,
 278             FSL_IMX6UL_GPIO4_ADDR,
 279             FSL_IMX6UL_GPIO5_ADDR,
 280         };
 281
 282         static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
 283             FSL_IMX6UL_GPIO1_LOW_IRQ,
 284             FSL_IMX6UL_GPIO2_LOW_IRQ,
 285             FSL_IMX6UL_GPIO3_LOW_IRQ,
 286             FSL_IMX6UL_GPIO4_LOW_IRQ,
 287             FSL_IMX6UL_GPIO5_LOW_IRQ,
 288         };
 289
 290         static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
 291             FSL_IMX6UL_GPIO1_HIGH_IRQ,
 292             FSL_IMX6UL_GPIO2_HIGH_IRQ,
 293             FSL_IMX6UL_GPIO3_HIGH_IRQ,
 294             FSL_IMX6UL_GPIO4_HIGH_IRQ,
 295             FSL_IMX6UL_GPIO5_HIGH_IRQ,
 296         };
 297
 298         object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
 299                                  &error_abort);
 300
 301         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 302                         FSL_IMX6UL_GPIOn_ADDR[i]);
 303
 304         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 305                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 306                                             FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
 307
 308         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
 309                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 310                                             FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
 311     }
 312
 313     /*
 314      * IOMUXC and IOMUXC_GPR
 315      */
 316     for (i = 0; i < 1; i++) {
 317         static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
 318             FSL_IMX6UL_IOMUXC_ADDR,
 319             FSL_IMX6UL_IOMUXC_GPR_ADDR,
 320         };
 321
 322         snprintf(name, NAME_SIZE, "iomuxc%d", i);
 323         create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
 324     }
 325
 326     /*
 327      * CCM
 328      */
 329     object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
 330     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR);
 331
 332     /*
 333      * SRC
 334      */
 335     object_property_set_bool(OBJECT(&s->src), true, "realized", &error_abort);
 336     sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR);
 337
 338     /*
 339      * GPCv2
 340      */
 341     object_property_set_bool(OBJECT(&s->gpcv2), true,
 342                              "realized", &error_abort);
 343     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
 344
 345     /* Initialize all ECSPI */
 346     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
 347         static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
 348             FSL_IMX6UL_ECSPI1_ADDR,
 349             FSL_IMX6UL_ECSPI2_ADDR,
 350             FSL_IMX6UL_ECSPI3_ADDR,
 351             FSL_IMX6UL_ECSPI4_ADDR,
 352         };
 353
 354         static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = {
 355             FSL_IMX6UL_ECSPI1_IRQ,
 356             FSL_IMX6UL_ECSPI2_IRQ,
 357             FSL_IMX6UL_ECSPI3_IRQ,
 358             FSL_IMX6UL_ECSPI4_IRQ,
 359         };
 360
 361         /* Initialize the SPI */
 362         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
 363                                  &error_abort);
 364
 365         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
 366                         FSL_IMX6UL_SPIn_ADDR[i]);
 367
 368         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 369                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 370                                             FSL_IMX6UL_SPIn_IRQ[i]));
 371     }
 372
 373     /*
 374      * I2C
 375      */
 376     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
 377         static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
 378             FSL_IMX6UL_I2C1_ADDR,
 379             FSL_IMX6UL_I2C2_ADDR,
 380             FSL_IMX6UL_I2C3_ADDR,
 381             FSL_IMX6UL_I2C4_ADDR,
 382         };
 383
 384         static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = {
 385             FSL_IMX6UL_I2C1_IRQ,
 386             FSL_IMX6UL_I2C2_IRQ,
 387             FSL_IMX6UL_I2C3_IRQ,
 388             FSL_IMX6UL_I2C4_IRQ,
 389         };
 390
 391         object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
 392                                  &error_abort);
 393         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
 394
 395         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 396                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 397                                             FSL_IMX6UL_I2Cn_IRQ[i]));
 398     }
 399
 400     /*
 401      * UART
 402      */
 403     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
 404         static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
 405             FSL_IMX6UL_UART1_ADDR,
 406             FSL_IMX6UL_UART2_ADDR,
 407             FSL_IMX6UL_UART3_ADDR,
 408             FSL_IMX6UL_UART4_ADDR,
 409             FSL_IMX6UL_UART5_ADDR,
 410             FSL_IMX6UL_UART6_ADDR,
 411             FSL_IMX6UL_UART7_ADDR,
 412             FSL_IMX6UL_UART8_ADDR,
 413         };
 414
 415         static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = {
 416             FSL_IMX6UL_UART1_IRQ,
 417             FSL_IMX6UL_UART2_IRQ,
 418             FSL_IMX6UL_UART3_IRQ,
 419             FSL_IMX6UL_UART4_IRQ,
 420             FSL_IMX6UL_UART5_IRQ,
 421             FSL_IMX6UL_UART6_IRQ,
 422             FSL_IMX6UL_UART7_IRQ,
 423             FSL_IMX6UL_UART8_IRQ,
 424         };
 425
 426         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 427
 428         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
 429                                  &error_abort);
 430
 431         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0,
 432                         FSL_IMX6UL_UARTn_ADDR[i]);
 433
 434         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 435                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 436                                             FSL_IMX6UL_UARTn_IRQ[i]));
 437     }
 438
 439     /*
 440      * Ethernet
 441      */
 442     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
 443         static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = {
 444             FSL_IMX6UL_ENET1_ADDR,
 445             FSL_IMX6UL_ENET2_ADDR,
 446         };
 447
 448         static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = {
 449             FSL_IMX6UL_ENET1_IRQ,
 450             FSL_IMX6UL_ENET2_IRQ,
 451         };
 452
 453         static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = {
 454             FSL_IMX6UL_ENET1_TIMER_IRQ,
 455             FSL_IMX6UL_ENET2_TIMER_IRQ,
 456         };
 457
 458         object_property_set_uint(OBJECT(&s->eth[i]),
 459                                  FSL_IMX6UL_ETH_NUM_TX_RINGS,
 460                                  "tx-ring-num", &error_abort);
 461         qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
 462         object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
 463                                  &error_abort);
 464
 465         sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0,
 466                         FSL_IMX6UL_ENETn_ADDR[i]);
 467
 468         sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
 469                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 470                                             FSL_IMX6UL_ENETn_IRQ[i]));
 471
 472         sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
 473                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 474                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
 475     }
 476
 477     /*
 478      * USDHC
 479      */
 480     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
 481         static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
 482             FSL_IMX6UL_USDHC1_ADDR,
 483             FSL_IMX6UL_USDHC2_ADDR,
 484         };
 485
 486         static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = {
 487             FSL_IMX6UL_USDHC1_IRQ,
 488             FSL_IMX6UL_USDHC2_IRQ,
 489         };
 490
 491         object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
 492                                  &error_abort);
 493
 494         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
 495                         FSL_IMX6UL_USDHCn_ADDR[i]);
 496
 497         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
 498                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 499                                             FSL_IMX6UL_USDHCn_IRQ[i]));
 500     }
 501
 502     /*
 503      * SNVS
 504      */
 505     object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
 506     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
 507
 508     /*
 509      * Watchdog
 510      */
 511     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
 512         static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
 513             FSL_IMX6UL_WDOG1_ADDR,
 514             FSL_IMX6UL_WDOG2_ADDR,
 515             FSL_IMX6UL_WDOG3_ADDR,
 516         };
 517
 518         object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
 519                                  &error_abort);
 520
 521         sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
 522                         FSL_IMX6UL_WDOGn_ADDR[i]);
 523     }
 524
 525     /*
 526      * GPR
 527      */
 528     object_property_set_bool(OBJECT(&s->gpr), true, "realized",
 529                              &error_abort);
 530     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
 531
 532     /*
 533      * SDMA
 534      */
 535     create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
 536
 537     /*
 538      * APHB_DMA
 539      */
 540     create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR,
 541                                 FSL_IMX6UL_APBH_DMA_SIZE);
 542
 543     /*
 544      * ADCs
 545      */
 546     for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) {
 547         static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = {
 548             FSL_IMX6UL_ADC1_ADDR,
 549             FSL_IMX6UL_ADC2_ADDR,
 550         };
 551
 552         snprintf(name, NAME_SIZE, "adc%d", i);
 553         create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
 554     }
 555
 556     /*
 557      * LCD
 558      */
 559     create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
 560
 561     /*
 562      * ROM memory
 563      */
 564     memory_region_init_rom(&s->rom, NULL, "imx6ul.rom",
 565                            FSL_IMX6UL_ROM_SIZE, &error_abort);
 566     memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR,
 567                                 &s->rom);
 568
 569     /*
 570      * CAAM memory
 571      */
 572     memory_region_init_rom(&s->caam, NULL, "imx6ul.caam",
 573                            FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort);
 574     memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR,
 575                                 &s->caam);
 576
 577     /*
 578      * OCRAM memory
 579      */
 580     memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram",
 581                            FSL_IMX6UL_OCRAM_MEM_SIZE,
 582                            &error_abort);
 583     memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR,
 584                                 &s->ocram);
 585
 586     /*
 587      * internal OCRAM (128 KB) is aliased over 512 KB
 588      */
 589     memory_region_init_alias(&s->ocram_alias, NULL, "imx6ul.ocram_alias",
 590                              &s->ocram, 0, FSL_IMX6UL_OCRAM_ALIAS_SIZE);
 591     memory_region_add_subregion(get_system_memory(),
 592                                 FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
 593 }
 594
 595 static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
 596 {
 597     DeviceClass *dc = DEVICE_CLASS(oc);
 598
 599     dc->realize = fsl_imx6ul_realize;
 600     dc->desc = "i.MX6UL SOC";
 601     /* Reason: Uses serial_hds and nd_table in realize() directly */
 602     dc->user_creatable = false;
 603 }
 604
 605 static const TypeInfo fsl_imx6ul_type_info = {
 606     .name = TYPE_FSL_IMX6UL,
 607     .parent = TYPE_DEVICE,
 608     .instance_size = sizeof(FslIMX6ULState),
 609     .instance_init = fsl_imx6ul_init,
 610     .class_init = fsl_imx6ul_class_init,
 611 };
 612
 613 static void fsl_imx6ul_register_types(void)
 614 {
 615     type_register_static(&fsl_imx6ul_type_info);
 616 }
 617 type_init(fsl_imx6ul_register_types)