2 * Copyright (c) 2018, Impinj, Inc.
4 * i.MX7 SoC definitions
6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
8 * Based on hw/arm/fsl-imx6.c
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu-common.h"
24 #include "hw/arm/fsl-imx7.h"
25 #include "hw/misc/unimp.h"
26 #include "sysemu/sysemu.h"
27 #include "qemu/error-report.h"
31 static void fsl_imx7_init(Object
*obj
)
33 BusState
*sysbus
= sysbus_get_default();
34 FslIMX7State
*s
= FSL_IMX7(obj
);
39 for (i
= 0; i
< MIN(smp_cpus
, FSL_IMX7_NUM_CPUS
); i
++) {
40 object_initialize(&s
->cpu
[i
], sizeof(s
->cpu
[i
]),
41 ARM_CPU_TYPE_NAME("cortex-a7"));
42 snprintf(name
, NAME_SIZE
, "cpu%d", i
);
43 object_property_add_child(obj
, name
, OBJECT(&s
->cpu
[i
]),
50 object_initialize(&s
->a7mpcore
, sizeof(s
->a7mpcore
), TYPE_A15MPCORE_PRIV
);
51 qdev_set_parent_bus(DEVICE(&s
->a7mpcore
), sysbus
);
52 object_property_add_child(obj
, "a7mpcore",
53 OBJECT(&s
->a7mpcore
), &error_fatal
);
58 for (i
= 0; i
< FSL_IMX7_NUM_GPIOS
; i
++) {
59 object_initialize(&s
->gpio
[i
], sizeof(s
->gpio
[i
]),
61 qdev_set_parent_bus(DEVICE(&s
->gpio
[i
]), sysbus
);
62 snprintf(name
, NAME_SIZE
, "gpio%d", i
);
63 object_property_add_child(obj
, name
,
64 OBJECT(&s
->gpio
[i
]), &error_fatal
);
70 for (i
= 0; i
< FSL_IMX7_NUM_GPTS
; i
++) {
71 object_initialize(&s
->gpt
[i
], sizeof(s
->gpt
[i
]), TYPE_IMX7_GPT
);
72 qdev_set_parent_bus(DEVICE(&s
->gpt
[i
]), sysbus
);
73 snprintf(name
, NAME_SIZE
, "gpt%d", i
);
74 object_property_add_child(obj
, name
, OBJECT(&s
->gpt
[i
]),
81 object_initialize(&s
->ccm
, sizeof(s
->ccm
), TYPE_IMX7_CCM
);
82 qdev_set_parent_bus(DEVICE(&s
->ccm
), sysbus
);
83 object_property_add_child(obj
, "ccm", OBJECT(&s
->ccm
), &error_fatal
);
88 object_initialize(&s
->analog
, sizeof(s
->analog
), TYPE_IMX7_ANALOG
);
89 qdev_set_parent_bus(DEVICE(&s
->analog
), sysbus
);
90 object_property_add_child(obj
, "analog", OBJECT(&s
->analog
), &error_fatal
);
95 object_initialize(&s
->gpcv2
, sizeof(s
->gpcv2
), TYPE_IMX_GPCV2
);
96 qdev_set_parent_bus(DEVICE(&s
->gpcv2
), sysbus
);
97 object_property_add_child(obj
, "gpcv2", OBJECT(&s
->gpcv2
), &error_fatal
);
99 for (i
= 0; i
< FSL_IMX7_NUM_ECSPIS
; i
++) {
100 object_initialize(&s
->spi
[i
], sizeof(s
->spi
[i
]), TYPE_IMX_SPI
);
101 qdev_set_parent_bus(DEVICE(&s
->spi
[i
]), sysbus_get_default());
102 snprintf(name
, NAME_SIZE
, "spi%d", i
+ 1);
103 object_property_add_child(obj
, name
, OBJECT(&s
->spi
[i
]), NULL
);
107 for (i
= 0; i
< FSL_IMX7_NUM_I2CS
; i
++) {
108 object_initialize(&s
->i2c
[i
], sizeof(s
->i2c
[i
]), TYPE_IMX_I2C
);
109 qdev_set_parent_bus(DEVICE(&s
->i2c
[i
]), sysbus_get_default());
110 snprintf(name
, NAME_SIZE
, "i2c%d", i
+ 1);
111 object_property_add_child(obj
, name
, OBJECT(&s
->i2c
[i
]), NULL
);
117 for (i
= 0; i
< FSL_IMX7_NUM_UARTS
; i
++) {
118 object_initialize(&s
->uart
[i
], sizeof(s
->uart
[i
]), TYPE_IMX_SERIAL
);
119 qdev_set_parent_bus(DEVICE(&s
->uart
[i
]), sysbus
);
120 snprintf(name
, NAME_SIZE
, "uart%d", i
);
121 object_property_add_child(obj
, name
, OBJECT(&s
->uart
[i
]),
128 for (i
= 0; i
< FSL_IMX7_NUM_ETHS
; i
++) {
129 object_initialize(&s
->eth
[i
], sizeof(s
->eth
[i
]), TYPE_IMX_ENET
);
130 qdev_set_parent_bus(DEVICE(&s
->eth
[i
]), sysbus
);
131 snprintf(name
, NAME_SIZE
, "eth%d", i
);
132 object_property_add_child(obj
, name
, OBJECT(&s
->eth
[i
]),
139 for (i
= 0; i
< FSL_IMX7_NUM_USDHCS
; i
++) {
140 object_initialize(&s
->usdhc
[i
], sizeof(s
->usdhc
[i
]),
142 qdev_set_parent_bus(DEVICE(&s
->usdhc
[i
]), sysbus
);
143 snprintf(name
, NAME_SIZE
, "usdhc%d", i
);
144 object_property_add_child(obj
, name
, OBJECT(&s
->usdhc
[i
]),
151 object_initialize(&s
->snvs
, sizeof(s
->snvs
), TYPE_IMX7_SNVS
);
152 qdev_set_parent_bus(DEVICE(&s
->snvs
), sysbus
);
153 object_property_add_child(obj
, "snvs", OBJECT(&s
->snvs
), &error_fatal
);
158 for (i
= 0; i
< FSL_IMX7_NUM_WDTS
; i
++) {
159 object_initialize(&s
->wdt
[i
], sizeof(s
->wdt
[i
]), TYPE_IMX2_WDT
);
160 qdev_set_parent_bus(DEVICE(&s
->wdt
[i
]), sysbus
);
161 snprintf(name
, NAME_SIZE
, "wdt%d", i
);
162 object_property_add_child(obj
, name
, OBJECT(&s
->wdt
[i
]),
169 object_initialize(&s
->gpr
, sizeof(s
->gpr
), TYPE_IMX7_GPR
);
170 qdev_set_parent_bus(DEVICE(&s
->gpr
), sysbus
);
171 object_property_add_child(obj
, "gpr", OBJECT(&s
->gpr
), &error_fatal
);
173 object_initialize(&s
->pcie
, sizeof(s
->pcie
), TYPE_DESIGNWARE_PCIE_HOST
);
174 qdev_set_parent_bus(DEVICE(&s
->pcie
), sysbus
);
175 object_property_add_child(obj
, "pcie", OBJECT(&s
->pcie
), &error_fatal
);
177 for (i
= 0; i
< FSL_IMX7_NUM_USBS
; i
++) {
178 object_initialize(&s
->usb
[i
],
179 sizeof(s
->usb
[i
]), TYPE_CHIPIDEA
);
180 qdev_set_parent_bus(DEVICE(&s
->usb
[i
]), sysbus
);
181 snprintf(name
, NAME_SIZE
, "usb%d", i
);
182 object_property_add_child(obj
, name
,
183 OBJECT(&s
->usb
[i
]), &error_fatal
);
187 static void fsl_imx7_realize(DeviceState
*dev
, Error
**errp
)
189 FslIMX7State
*s
= FSL_IMX7(dev
);
193 char name
[NAME_SIZE
];
195 if (smp_cpus
> FSL_IMX7_NUM_CPUS
) {
196 error_setg(errp
, "%s: Only %d CPUs are supported (%d requested)",
197 TYPE_FSL_IMX7
, FSL_IMX7_NUM_CPUS
, smp_cpus
);
201 for (i
= 0; i
< smp_cpus
; i
++) {
202 o
= OBJECT(&s
->cpu
[i
]);
204 object_property_set_int(o
, QEMU_PSCI_CONDUIT_SMC
,
205 "psci-conduit", &error_abort
);
207 /* On uniprocessor, the CBAR is set to 0 */
209 object_property_set_int(o
, FSL_IMX7_A7MPCORE_ADDR
,
210 "reset-cbar", &error_abort
);
214 /* Secondary CPUs start in PSCI powered-down state */
215 object_property_set_bool(o
, true,
216 "start-powered-off", &error_abort
);
219 object_property_set_bool(o
, true, "realized", &error_abort
);
225 object_property_set_int(OBJECT(&s
->a7mpcore
), smp_cpus
, "num-cpu",
227 object_property_set_int(OBJECT(&s
->a7mpcore
),
228 FSL_IMX7_MAX_IRQ
+ GIC_INTERNAL
,
229 "num-irq", &error_abort
);
231 object_property_set_bool(OBJECT(&s
->a7mpcore
), true, "realized",
233 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->a7mpcore
), 0, FSL_IMX7_A7MPCORE_ADDR
);
235 for (i
= 0; i
< smp_cpus
; i
++) {
236 SysBusDevice
*sbd
= SYS_BUS_DEVICE(&s
->a7mpcore
);
237 DeviceState
*d
= DEVICE(qemu_get_cpu(i
));
239 irq
= qdev_get_gpio_in(d
, ARM_CPU_IRQ
);
240 sysbus_connect_irq(sbd
, i
, irq
);
241 irq
= qdev_get_gpio_in(d
, ARM_CPU_FIQ
);
242 sysbus_connect_irq(sbd
, i
+ smp_cpus
, irq
);
248 create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR
,
254 for (i
= 0; i
< FSL_IMX7_NUM_GPTS
; i
++) {
255 static const hwaddr FSL_IMX7_GPTn_ADDR
[FSL_IMX7_NUM_GPTS
] = {
262 s
->gpt
[i
].ccm
= IMX_CCM(&s
->ccm
);
263 object_property_set_bool(OBJECT(&s
->gpt
[i
]), true, "realized",
265 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpt
[i
]), 0, FSL_IMX7_GPTn_ADDR
[i
]);
268 for (i
= 0; i
< FSL_IMX7_NUM_GPIOS
; i
++) {
269 static const hwaddr FSL_IMX7_GPIOn_ADDR
[FSL_IMX7_NUM_GPIOS
] = {
279 object_property_set_bool(OBJECT(&s
->gpio
[i
]), true, "realized",
281 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0, FSL_IMX7_GPIOn_ADDR
[i
]);
285 * IOMUXC and IOMUXC_LPSR
287 for (i
= 0; i
< FSL_IMX7_NUM_IOMUXCS
; i
++) {
288 static const hwaddr FSL_IMX7_IOMUXCn_ADDR
[FSL_IMX7_NUM_IOMUXCS
] = {
289 FSL_IMX7_IOMUXC_ADDR
,
290 FSL_IMX7_IOMUXC_LPSR_ADDR
,
293 snprintf(name
, NAME_SIZE
, "iomuxc%d", i
);
294 create_unimplemented_device(name
, FSL_IMX7_IOMUXCn_ADDR
[i
],
295 FSL_IMX7_IOMUXCn_SIZE
);
301 object_property_set_bool(OBJECT(&s
->ccm
), true, "realized", &error_abort
);
302 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ccm
), 0, FSL_IMX7_CCM_ADDR
);
307 object_property_set_bool(OBJECT(&s
->analog
), true, "realized",
309 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->analog
), 0, FSL_IMX7_ANALOG_ADDR
);
314 object_property_set_bool(OBJECT(&s
->gpcv2
), true,
315 "realized", &error_abort
);
316 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpcv2
), 0, FSL_IMX7_GPC_ADDR
);
318 /* Initialize all ECSPI */
319 for (i
= 0; i
< FSL_IMX7_NUM_ECSPIS
; i
++) {
320 static const hwaddr FSL_IMX7_SPIn_ADDR
[FSL_IMX7_NUM_ECSPIS
] = {
321 FSL_IMX7_ECSPI1_ADDR
,
322 FSL_IMX7_ECSPI2_ADDR
,
323 FSL_IMX7_ECSPI3_ADDR
,
324 FSL_IMX7_ECSPI4_ADDR
,
327 static const hwaddr FSL_IMX7_SPIn_IRQ
[FSL_IMX7_NUM_ECSPIS
] = {
334 /* Initialize the SPI */
335 object_property_set_bool(OBJECT(&s
->spi
[i
]), true, "realized",
337 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
338 FSL_IMX7_SPIn_ADDR
[i
]);
339 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
340 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
341 FSL_IMX7_SPIn_IRQ
[i
]));
344 for (i
= 0; i
< FSL_IMX7_NUM_I2CS
; i
++) {
345 static const hwaddr FSL_IMX7_I2Cn_ADDR
[FSL_IMX7_NUM_I2CS
] = {
352 static const hwaddr FSL_IMX7_I2Cn_IRQ
[FSL_IMX7_NUM_I2CS
] = {
359 object_property_set_bool(OBJECT(&s
->i2c
[i
]), true, "realized",
361 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0, FSL_IMX7_I2Cn_ADDR
[i
]);
363 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0,
364 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
365 FSL_IMX7_I2Cn_IRQ
[i
]));
371 for (i
= 0; i
< FSL_IMX7_NUM_UARTS
; i
++) {
372 static const hwaddr FSL_IMX7_UARTn_ADDR
[FSL_IMX7_NUM_UARTS
] = {
382 static const int FSL_IMX7_UARTn_IRQ
[FSL_IMX7_NUM_UARTS
] = {
393 if (i
< MAX_SERIAL_PORTS
) {
394 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hds
[i
]);
397 object_property_set_bool(OBJECT(&s
->uart
[i
]), true, "realized",
400 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, FSL_IMX7_UARTn_ADDR
[i
]);
402 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_UARTn_IRQ
[i
]);
403 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, irq
);
409 for (i
= 0; i
< FSL_IMX7_NUM_ETHS
; i
++) {
410 static const hwaddr FSL_IMX7_ENETn_ADDR
[FSL_IMX7_NUM_ETHS
] = {
415 object_property_set_uint(OBJECT(&s
->eth
[i
]), FSL_IMX7_ETH_NUM_TX_RINGS
,
416 "tx-ring-num", &error_abort
);
417 qdev_set_nic_properties(DEVICE(&s
->eth
[i
]), &nd_table
[i
]);
418 object_property_set_bool(OBJECT(&s
->eth
[i
]), true, "realized",
421 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->eth
[i
]), 0, FSL_IMX7_ENETn_ADDR
[i
]);
423 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_ENET_IRQ(i
, 0));
424 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->eth
[i
]), 0, irq
);
425 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_ENET_IRQ(i
, 3));
426 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->eth
[i
]), 1, irq
);
432 for (i
= 0; i
< FSL_IMX7_NUM_USDHCS
; i
++) {
433 static const hwaddr FSL_IMX7_USDHCn_ADDR
[FSL_IMX7_NUM_USDHCS
] = {
434 FSL_IMX7_USDHC1_ADDR
,
435 FSL_IMX7_USDHC2_ADDR
,
436 FSL_IMX7_USDHC3_ADDR
,
439 static const int FSL_IMX7_USDHCn_IRQ
[FSL_IMX7_NUM_USDHCS
] = {
445 object_property_set_bool(OBJECT(&s
->usdhc
[i
]), true, "realized",
448 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->usdhc
[i
]), 0,
449 FSL_IMX7_USDHCn_ADDR
[i
]);
451 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_USDHCn_IRQ
[i
]);
452 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usdhc
[i
]), 0, irq
);
458 object_property_set_bool(OBJECT(&s
->snvs
), true, "realized", &error_abort
);
459 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->snvs
), 0, FSL_IMX7_SNVS_ADDR
);
464 create_unimplemented_device("sdma", FSL_IMX7_SRC_ADDR
, FSL_IMX7_SRC_SIZE
);
469 for (i
= 0; i
< FSL_IMX7_NUM_WDTS
; i
++) {
470 static const hwaddr FSL_IMX7_WDOGn_ADDR
[FSL_IMX7_NUM_WDTS
] = {
477 object_property_set_bool(OBJECT(&s
->wdt
[i
]), true, "realized",
480 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0, FSL_IMX7_WDOGn_ADDR
[i
]);
486 create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR
, FSL_IMX7_SDMA_SIZE
);
489 object_property_set_bool(OBJECT(&s
->gpr
), true, "realized",
491 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpr
), 0, FSL_IMX7_GPR_ADDR
);
493 object_property_set_bool(OBJECT(&s
->pcie
), true,
494 "realized", &error_abort
);
495 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->pcie
), 0, FSL_IMX7_PCIE_REG_ADDR
);
497 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_PCI_INTA_IRQ
);
498 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->pcie
), 0, irq
);
499 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_PCI_INTB_IRQ
);
500 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->pcie
), 1, irq
);
501 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_PCI_INTC_IRQ
);
502 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->pcie
), 2, irq
);
503 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_PCI_INTD_IRQ
);
504 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->pcie
), 3, irq
);
507 for (i
= 0; i
< FSL_IMX7_NUM_USBS
; i
++) {
508 static const hwaddr FSL_IMX7_USBMISCn_ADDR
[FSL_IMX7_NUM_USBS
] = {
509 FSL_IMX7_USBMISC1_ADDR
,
510 FSL_IMX7_USBMISC2_ADDR
,
511 FSL_IMX7_USBMISC3_ADDR
,
514 static const hwaddr FSL_IMX7_USBn_ADDR
[FSL_IMX7_NUM_USBS
] = {
520 static const hwaddr FSL_IMX7_USBn_IRQ
[FSL_IMX7_NUM_USBS
] = {
526 object_property_set_bool(OBJECT(&s
->usb
[i
]), true, "realized",
528 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->usb
[i
]), 0,
529 FSL_IMX7_USBn_ADDR
[i
]);
531 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_USBn_IRQ
[i
]);
532 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usb
[i
]), 0, irq
);
534 snprintf(name
, NAME_SIZE
, "usbmisc%d", i
);
535 create_unimplemented_device(name
, FSL_IMX7_USBMISCn_ADDR
[i
],
536 FSL_IMX7_USBMISCn_SIZE
);
542 for (i
= 0; i
< FSL_IMX7_NUM_ADCS
; i
++) {
543 static const hwaddr FSL_IMX7_ADCn_ADDR
[FSL_IMX7_NUM_ADCS
] = {
548 snprintf(name
, NAME_SIZE
, "adc%d", i
);
549 create_unimplemented_device(name
, FSL_IMX7_ADCn_ADDR
[i
],
556 create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR
,
557 FSL_IMX7_LCDIF_SIZE
);
560 static void fsl_imx7_class_init(ObjectClass
*oc
, void *data
)
562 DeviceClass
*dc
= DEVICE_CLASS(oc
);
564 dc
->realize
= fsl_imx7_realize
;
566 /* Reason: Uses serial_hds and nd_table in realize() directly */
567 dc
->user_creatable
= false;
568 dc
->desc
= "i.MX7 SOC";
571 static const TypeInfo fsl_imx7_type_info
= {
572 .name
= TYPE_FSL_IMX7
,
573 .parent
= TYPE_DEVICE
,
574 .instance_size
= sizeof(FslIMX7State
),
575 .instance_init
= fsl_imx7_init
,
576 .class_init
= fsl_imx7_class_init
,
579 static void fsl_imx7_register_types(void)
581 type_register_static(&fsl_imx7_type_info
);
583 type_init(fsl_imx7_register_types
)