hw/arm/highbank.c

   1 /*
   2  * Calxeda Highbank SoC emulation
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include "hw/sysbus.h"
  21 #include "hw/arm/arm.h"
  22 #include "hw/devices.h"
  23 #include "hw/loader.h"
  24 #include "net/net.h"
  25 #include "sysemu/sysemu.h"
  26 #include "hw/boards.h"
  27 #include "sysemu/blockdev.h"
  28 #include "exec/address-spaces.h"
  29
  30 #define SMP_BOOT_ADDR 0x100
  31 #define SMP_BOOT_REG  0x40
  32 #define GIC_BASE_ADDR 0xfff10000
  33
  34 #define NIRQ_GIC      160
  35
  36 /* Board init.  */
  37
  38 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  39 {
  40     int n;
  41     uint32_t smpboot[] = {
  42         0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
  43         0xe210000f, /* ands r0, r0, #0x0f */
  44         0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
  45         0xe0830200, /* add r0, r3, r0, lsl #4 */
  46         0xe59f2024, /* ldr r2, privbase */
  47         0xe3a01001, /* mov r1, #1 */
  48         0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
  49         0xe3a010ff, /* mov r1, #0xff */
  50         0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
  51         0xf57ff04f, /* dsb */
  52         0xe320f003, /* wfi */
  53         0xe5901000, /* ldr     r1, [r0] */
  54         0xe1110001, /* tst     r1, r1 */
  55         0x0afffffb, /* beq     <wfi> */
  56         0xe12fff11, /* bx      r1 */
  57         GIC_BASE_ADDR      /* privbase: gic address.  */
  58     };
  59     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  60         smpboot[n] = tswap32(smpboot[n]);
  61     }
  62     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
  63 }
  64
  65 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  66 {
  67     CPUARMState *env = &cpu->env;
  68
  69     switch (info->nb_cpus) {
  70     case 4:
  71         stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
  72     case 3:
  73         stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
  74     case 2:
  75         stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
  76         env->regs[15] = SMP_BOOT_ADDR;
  77         break;
  78     default:
  79         break;
  80     }
  81 }
  82
  83 #define NUM_REGS      0x200
  84 static void hb_regs_write(void *opaque, hwaddr offset,
  85                           uint64_t value, unsigned size)
  86 {
  87     uint32_t *regs = opaque;
  88
  89     if (offset == 0xf00) {
  90         if (value == 1 || value == 2) {
  91             qemu_system_reset_request();
  92         } else if (value == 3) {
  93             qemu_system_shutdown_request();
  94         }
  95     }
  96
  97     regs[offset/4] = value;
  98 }
  99
 100 static uint64_t hb_regs_read(void *opaque, hwaddr offset,
 101                              unsigned size)
 102 {
 103     uint32_t *regs = opaque;
 104     uint32_t value = regs[offset/4];
 105
 106     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
 107         value |= 0x30000000;
 108     }
 109
 110     return value;
 111 }
 112
 113 static const MemoryRegionOps hb_mem_ops = {
 114     .read = hb_regs_read,
 115     .write = hb_regs_write,
 116     .endianness = DEVICE_NATIVE_ENDIAN,
 117 };
 118
 119 typedef struct {
 120     SysBusDevice busdev;
 121     MemoryRegion *iomem;
 122     uint32_t regs[NUM_REGS];
 123 } HighbankRegsState;
 124
 125 static VMStateDescription vmstate_highbank_regs = {
 126     .name = "highbank-regs",
 127     .version_id = 0,
 128     .minimum_version_id = 0,
 129     .minimum_version_id_old = 0,
 130     .fields = (VMStateField[]) {
 131         VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
 132         VMSTATE_END_OF_LIST(),
 133     },
 134 };
 135
 136 static void highbank_regs_reset(DeviceState *dev)
 137 {
 138     SysBusDevice *sys_dev = SYS_BUS_DEVICE(dev);
 139     HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, sys_dev);
 140
 141     s->regs[0x40] = 0x05F20121;
 142     s->regs[0x41] = 0x2;
 143     s->regs[0x42] = 0x05F30121;
 144     s->regs[0x43] = 0x05F40121;
 145 }
 146
 147 static int highbank_regs_init(SysBusDevice *dev)
 148 {
 149     HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev);
 150
 151     s->iomem = g_new(MemoryRegion, 1);
 152     memory_region_init_io(s->iomem, OBJECT(s), &hb_mem_ops, s->regs,
 153                           "highbank_regs", 0x1000);
 154     sysbus_init_mmio(dev, s->iomem);
 155
 156     return 0;
 157 }
 158
 159 static void highbank_regs_class_init(ObjectClass *klass, void *data)
 160 {
 161     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 162     DeviceClass *dc = DEVICE_CLASS(klass);
 163
 164     sbc->init = highbank_regs_init;
 165     dc->desc = "Calxeda Highbank registers";
 166     dc->vmsd = &vmstate_highbank_regs;
 167     dc->reset = highbank_regs_reset;
 168 }
 169
 170 static const TypeInfo highbank_regs_info = {
 171     .name          = "highbank-regs",
 172     .parent        = TYPE_SYS_BUS_DEVICE,
 173     .instance_size = sizeof(HighbankRegsState),
 174     .class_init    = highbank_regs_class_init,
 175 };
 176
 177 static void highbank_regs_register_types(void)
 178 {
 179     type_register_static(&highbank_regs_info);
 180 }
 181
 182 type_init(highbank_regs_register_types)
 183
 184 static struct arm_boot_info highbank_binfo;
 185
 186 enum cxmachines {
 187     CALXEDA_HIGHBANK,
 188     CALXEDA_MIDWAY,
 189 };
 190
 191 /* ram_size must be set to match the upper bound of memory in the
 192  * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 193  * normally 0xff900000 or -m 4089. When running this board on a
 194  * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 195  * device tree and pass -m 2047 to QEMU.
 196  */
 197 static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
 198 {
 199     ram_addr_t ram_size = args->ram_size;
 200     const char *cpu_model = args->cpu_model;
 201     const char *kernel_filename = args->kernel_filename;
 202     const char *kernel_cmdline = args->kernel_cmdline;
 203     const char *initrd_filename = args->initrd_filename;
 204     DeviceState *dev = NULL;
 205     SysBusDevice *busdev;
 206     qemu_irq *irqp;
 207     qemu_irq pic[128];
 208     int n;
 209     qemu_irq cpu_irq[4];
 210     MemoryRegion *sysram;
 211     MemoryRegion *dram;
 212     MemoryRegion *sysmem;
 213     char *sysboot_filename;
 214
 215     if (!cpu_model) {
 216         switch (machine) {
 217         case CALXEDA_HIGHBANK:
 218             cpu_model = "cortex-a9";
 219             break;
 220         case CALXEDA_MIDWAY:
 221             cpu_model = "cortex-a15";
 222             break;
 223         }
 224     }
 225
 226     for (n = 0; n < smp_cpus; n++) {
 227         ARMCPU *cpu;
 228         cpu = cpu_arm_init(cpu_model);
 229         if (cpu == NULL) {
 230             fprintf(stderr, "Unable to find CPU definition\n");
 231             exit(1);
 232         }
 233
 234         /* This will become a QOM property eventually */
 235         cpu->reset_cbar = GIC_BASE_ADDR;
 236         irqp = arm_pic_init_cpu(cpu);
 237         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 238     }
 239
 240     sysmem = get_system_memory();
 241     dram = g_new(MemoryRegion, 1);
 242     memory_region_init_ram(dram, NULL, "highbank.dram", ram_size);
 243     /* SDRAM at address zero.  */
 244     memory_region_add_subregion(sysmem, 0, dram);
 245
 246     sysram = g_new(MemoryRegion, 1);
 247     memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000);
 248     memory_region_add_subregion(sysmem, 0xfff88000, sysram);
 249     if (bios_name != NULL) {
 250         sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 251         if (sysboot_filename != NULL) {
 252             uint32_t filesize = get_image_size(sysboot_filename);
 253             if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
 254                 hw_error("Unable to load %s\n", bios_name);
 255             }
 256         } else {
 257            hw_error("Unable to find %s\n", bios_name);
 258         }
 259     }
 260
 261     switch (machine) {
 262     case CALXEDA_HIGHBANK:
 263         dev = qdev_create(NULL, "l2x0");
 264         qdev_init_nofail(dev);
 265         busdev = SYS_BUS_DEVICE(dev);
 266         sysbus_mmio_map(busdev, 0, 0xfff12000);
 267
 268         dev = qdev_create(NULL, "a9mpcore_priv");
 269         break;
 270     case CALXEDA_MIDWAY:
 271         dev = qdev_create(NULL, "a15mpcore_priv");
 272         break;
 273     }
 274     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 275     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
 276     qdev_init_nofail(dev);
 277     busdev = SYS_BUS_DEVICE(dev);
 278     sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
 279     for (n = 0; n < smp_cpus; n++) {
 280         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 281     }
 282
 283     for (n = 0; n < 128; n++) {
 284         pic[n] = qdev_get_gpio_in(dev, n);
 285     }
 286
 287     dev = qdev_create(NULL, "sp804");
 288     qdev_prop_set_uint32(dev, "freq0", 150000000);
 289     qdev_prop_set_uint32(dev, "freq1", 150000000);
 290     qdev_init_nofail(dev);
 291     busdev = SYS_BUS_DEVICE(dev);
 292     sysbus_mmio_map(busdev, 0, 0xfff34000);
 293     sysbus_connect_irq(busdev, 0, pic[18]);
 294     sysbus_create_simple("pl011", 0xfff36000, pic[20]);
 295
 296     dev = qdev_create(NULL, "highbank-regs");
 297     qdev_init_nofail(dev);
 298     busdev = SYS_BUS_DEVICE(dev);
 299     sysbus_mmio_map(busdev, 0, 0xfff3c000);
 300
 301     sysbus_create_simple("pl061", 0xfff30000, pic[14]);
 302     sysbus_create_simple("pl061", 0xfff31000, pic[15]);
 303     sysbus_create_simple("pl061", 0xfff32000, pic[16]);
 304     sysbus_create_simple("pl061", 0xfff33000, pic[17]);
 305     sysbus_create_simple("pl031", 0xfff35000, pic[19]);
 306     sysbus_create_simple("pl022", 0xfff39000, pic[23]);
 307
 308     sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
 309
 310     if (nd_table[0].used) {
 311         qemu_check_nic_model(&nd_table[0], "xgmac");
 312         dev = qdev_create(NULL, "xgmac");
 313         qdev_set_nic_properties(dev, &nd_table[0]);
 314         qdev_init_nofail(dev);
 315         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
 316         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
 317         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
 318         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
 319
 320         qemu_check_nic_model(&nd_table[1], "xgmac");
 321         dev = qdev_create(NULL, "xgmac");
 322         qdev_set_nic_properties(dev, &nd_table[1]);
 323         qdev_init_nofail(dev);
 324         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
 325         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
 326         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
 327         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
 328     }
 329
 330     highbank_binfo.ram_size = ram_size;
 331     highbank_binfo.kernel_filename = kernel_filename;
 332     highbank_binfo.kernel_cmdline = kernel_cmdline;
 333     highbank_binfo.initrd_filename = initrd_filename;
 334     /* highbank requires a dtb in order to boot, and the dtb will override
 335      * the board ID. The following value is ignored, so set it to -1 to be
 336      * clear that the value is meaningless.
 337      */
 338     highbank_binfo.board_id = -1;
 339     highbank_binfo.nb_cpus = smp_cpus;
 340     highbank_binfo.loader_start = 0;
 341     highbank_binfo.write_secondary_boot = hb_write_secondary;
 342     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
 343     arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
 344 }
 345
 346 static void highbank_init(QEMUMachineInitArgs *args)
 347 {
 348     calxeda_init(args, CALXEDA_HIGHBANK);
 349 }
 350
 351 static void midway_init(QEMUMachineInitArgs *args)
 352 {
 353     calxeda_init(args, CALXEDA_MIDWAY);
 354 }
 355
 356 static QEMUMachine highbank_machine = {
 357     .name = "highbank",
 358     .desc = "Calxeda Highbank (ECX-1000)",
 359     .init = highbank_init,
 360     .block_default_type = IF_SCSI,
 361     .max_cpus = 4,
 362     DEFAULT_MACHINE_OPTIONS,
 363 };
 364
 365 static QEMUMachine midway_machine = {
 366     .name = "midway",
 367     .desc = "Calxeda Midway (ECX-2000)",
 368     .init = midway_init,
 369     .block_default_type = IF_SCSI,
 370     .max_cpus = 4,
 371     DEFAULT_MACHINE_OPTIONS,
 372 };
 373
 374 static void calxeda_machines_init(void)
 375 {
 376     qemu_register_machine(&highbank_machine);
 377     qemu_register_machine(&midway_machine);
 378 }
 379
 380 machine_init(calxeda_machines_init);