2 * Arm Musca-B1 test chip board emulation
4 * Copyright (c) 2019 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
13 * The Musca boards are a reference implementation of a system using
14 * the SSE-200 subsystem for embedded:
15 * https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-a-test-chip-board
16 * https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-b-test-chip-board
17 * We model the A and B1 variants of this board, as described in the TRMs:
18 * http://infocenter.arm.com/help/topic/com.arm.doc.101107_0000_00_en/index.html
19 * http://infocenter.arm.com/help/topic/com.arm.doc.101312_0000_00_en/index.html
22 #include "qemu/osdep.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
25 #include "exec/address-spaces.h"
26 #include "sysemu/sysemu.h"
27 #include "hw/arm/boot.h"
28 #include "hw/arm/armsse.h"
29 #include "hw/boards.h"
30 #include "hw/char/pl011.h"
31 #include "hw/core/split-irq.h"
32 #include "hw/misc/tz-mpc.h"
33 #include "hw/misc/tz-ppc.h"
34 #include "hw/misc/unimp.h"
35 #include "hw/rtc/pl031.h"
36 #include "qom/object.h"
38 #define MUSCA_NUMIRQ_MAX 96
39 #define MUSCA_PPC_MAX 3
40 #define MUSCA_MPC_MAX 5
42 typedef struct MPCInfo MPCInfo
;
44 typedef enum MuscaType
{
49 struct MuscaMachineClass
{
55 const MPCInfo
*mpc_info
;
58 typedef struct MuscaMachineClass MuscaMachineClass
;
60 struct MuscaMachineState
{
65 MemoryRegion ram
[MUSCA_MPC_MAX
];
66 SplitIRQ cpu_irq_splitter
[MUSCA_NUMIRQ_MAX
];
67 SplitIRQ sec_resp_splitter
;
68 TZPPC ppc
[MUSCA_PPC_MAX
];
69 MemoryRegion container
;
70 UnimplementedDeviceState eflash
[2];
71 UnimplementedDeviceState qspi
;
72 TZMPC mpc
[MUSCA_MPC_MAX
];
73 UnimplementedDeviceState mhu
[2];
74 UnimplementedDeviceState pwm
[3];
75 UnimplementedDeviceState i2s
;
77 UnimplementedDeviceState i2c
[2];
78 UnimplementedDeviceState spi
;
79 UnimplementedDeviceState scc
;
80 UnimplementedDeviceState timer
;
82 UnimplementedDeviceState pvt
;
83 UnimplementedDeviceState sdio
;
84 UnimplementedDeviceState gpio
;
85 UnimplementedDeviceState cryptoisland
;
87 typedef struct MuscaMachineState MuscaMachineState
;
89 #define TYPE_MUSCA_MACHINE "musca"
90 #define TYPE_MUSCA_A_MACHINE MACHINE_TYPE_NAME("musca-a")
91 #define TYPE_MUSCA_B1_MACHINE MACHINE_TYPE_NAME("musca-b1")
93 DECLARE_OBJ_CHECKERS(MuscaMachineState
, MuscaMachineClass
,
94 MUSCA_MACHINE
, TYPE_MUSCA_MACHINE
)
97 * Main SYSCLK frequency in Hz
98 * TODO this should really be different for the two cores, but we
99 * don't model that in our SSE-200 model yet.
101 #define SYSCLK_FRQ 40000000
103 static qemu_irq
get_sse_irq_in(MuscaMachineState
*mms
, int irqno
)
105 /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */
106 assert(irqno
< MUSCA_NUMIRQ_MAX
);
108 return qdev_get_gpio_in(DEVICE(&mms
->cpu_irq_splitter
[irqno
]), 0);
112 * Most of the devices in the Musca board sit behind Peripheral Protection
113 * Controllers. These data structures define the layout of which devices
114 * sit behind which PPCs.
115 * The devfn for each port is a function which creates, configures
116 * and initializes the device, returning the MemoryRegion which
117 * needs to be plugged into the downstream end of the PPC port.
119 typedef MemoryRegion
*MakeDevFn(MuscaMachineState
*mms
, void *opaque
,
120 const char *name
, hwaddr size
);
122 typedef struct PPCPortInfo
{
130 typedef struct PPCInfo
{
132 PPCPortInfo ports
[TZ_NUM_PORTS
];
135 static MemoryRegion
*make_unimp_dev(MuscaMachineState
*mms
,
136 void *opaque
, const char *name
, hwaddr size
)
139 * Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
140 * and return a pointer to its MemoryRegion.
142 UnimplementedDeviceState
*uds
= opaque
;
144 object_initialize_child(OBJECT(mms
), name
, uds
, TYPE_UNIMPLEMENTED_DEVICE
);
145 qdev_prop_set_string(DEVICE(uds
), "name", name
);
146 qdev_prop_set_uint64(DEVICE(uds
), "size", size
);
147 sysbus_realize(SYS_BUS_DEVICE(uds
), &error_fatal
);
148 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds
), 0);
151 typedef enum MPCInfoType
{
164 /* Order of the MPCs here must match the order of the bits in SECMPCINTSTATUS */
165 static const MPCInfo a_mpc_info
[] = { {
178 static const MPCInfo b1_mpc_info
[] = { {
199 .name
= "cryptoisland",
200 .type
= MPC_CRYPTOISLAND
,
206 static MemoryRegion
*make_mpc(MuscaMachineState
*mms
, void *opaque
,
207 const char *name
, hwaddr size
)
210 * Create an MPC and the RAM or flash behind it.
215 * MPC 4: CryptoIsland
216 * For now we implement the flash regions as ROM (ie not programmable)
217 * (with their control interface memory regions being unimplemented
218 * stubs behind the PPCs).
219 * The whole CryptoIsland region behind its MPC is an unimplemented stub.
221 MuscaMachineClass
*mmc
= MUSCA_MACHINE_GET_CLASS(mms
);
223 int i
= mpc
- &mms
->mpc
[0];
224 MemoryRegion
*downstream
;
225 MemoryRegion
*upstream
;
226 UnimplementedDeviceState
*uds
;
228 const MPCInfo
*mpcinfo
= mmc
->mpc_info
;
230 mpcname
= g_strdup_printf("%s-mpc", mpcinfo
[i
].name
);
232 switch (mpcinfo
[i
].type
) {
234 downstream
= &mms
->ram
[i
];
235 memory_region_init_rom(downstream
, NULL
, mpcinfo
[i
].name
,
236 mpcinfo
[i
].size
, &error_fatal
);
239 downstream
= &mms
->ram
[i
];
240 memory_region_init_ram(downstream
, NULL
, mpcinfo
[i
].name
,
241 mpcinfo
[i
].size
, &error_fatal
);
243 case MPC_CRYPTOISLAND
:
244 /* We don't implement the CryptoIsland yet */
245 uds
= &mms
->cryptoisland
;
246 object_initialize_child(OBJECT(mms
), name
, uds
,
247 TYPE_UNIMPLEMENTED_DEVICE
);
248 qdev_prop_set_string(DEVICE(uds
), "name", mpcinfo
[i
].name
);
249 qdev_prop_set_uint64(DEVICE(uds
), "size", mpcinfo
[i
].size
);
250 sysbus_realize(SYS_BUS_DEVICE(uds
), &error_fatal
);
251 downstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(uds
), 0);
254 g_assert_not_reached();
257 object_initialize_child(OBJECT(mms
), mpcname
, mpc
, TYPE_TZ_MPC
);
258 object_property_set_link(OBJECT(mpc
), "downstream", OBJECT(downstream
),
260 sysbus_realize(SYS_BUS_DEVICE(mpc
), &error_fatal
);
261 /* Map the upstream end of the MPC into system memory */
262 upstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc
), 1);
263 memory_region_add_subregion(get_system_memory(), mpcinfo
[i
].addr
, upstream
);
264 /* and connect its interrupt to the SSE-200 */
265 qdev_connect_gpio_out_named(DEVICE(mpc
), "irq", 0,
266 qdev_get_gpio_in_named(DEVICE(&mms
->sse
),
267 "mpcexp_status", i
));
270 /* Return the register interface MR for our caller to map behind the PPC */
271 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc
), 0);
274 static MemoryRegion
*make_rtc(MuscaMachineState
*mms
, void *opaque
,
275 const char *name
, hwaddr size
)
277 PL031State
*rtc
= opaque
;
279 object_initialize_child(OBJECT(mms
), name
, rtc
, TYPE_PL031
);
280 sysbus_realize(SYS_BUS_DEVICE(rtc
), &error_fatal
);
281 sysbus_connect_irq(SYS_BUS_DEVICE(rtc
), 0, get_sse_irq_in(mms
, 39));
282 return sysbus_mmio_get_region(SYS_BUS_DEVICE(rtc
), 0);
285 static MemoryRegion
*make_uart(MuscaMachineState
*mms
, void *opaque
,
286 const char *name
, hwaddr size
)
288 PL011State
*uart
= opaque
;
289 int i
= uart
- &mms
->uart
[0];
290 int irqbase
= 7 + i
* 6;
293 object_initialize_child(OBJECT(mms
), name
, uart
, TYPE_PL011
);
294 qdev_prop_set_chr(DEVICE(uart
), "chardev", serial_hd(i
));
295 sysbus_realize(SYS_BUS_DEVICE(uart
), &error_fatal
);
296 s
= SYS_BUS_DEVICE(uart
);
297 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqbase
+ 5)); /* combined */
298 sysbus_connect_irq(s
, 1, get_sse_irq_in(mms
, irqbase
+ 0)); /* RX */
299 sysbus_connect_irq(s
, 2, get_sse_irq_in(mms
, irqbase
+ 1)); /* TX */
300 sysbus_connect_irq(s
, 3, get_sse_irq_in(mms
, irqbase
+ 2)); /* RT */
301 sysbus_connect_irq(s
, 4, get_sse_irq_in(mms
, irqbase
+ 3)); /* MS */
302 sysbus_connect_irq(s
, 5, get_sse_irq_in(mms
, irqbase
+ 4)); /* E */
303 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart
), 0);
306 static MemoryRegion
*make_musca_a_devs(MuscaMachineState
*mms
, void *opaque
,
307 const char *name
, hwaddr size
)
310 * Create the container MemoryRegion for all the devices that live
311 * behind the Musca-A PPC's single port. These devices don't have a PPC
312 * port each, but we use the PPCPortInfo struct as a convenient way
313 * to describe them. Note that addresses here are relative to the base
314 * address of the PPC port region: 0x40100000, and devices appear both
315 * at the 0x4... NS region and the 0x5... S region.
318 MemoryRegion
*container
= &mms
->container
;
320 const PPCPortInfo devices
[] = {
321 { "uart0", make_uart
, &mms
->uart
[0], 0x1000, 0x1000 },
322 { "uart1", make_uart
, &mms
->uart
[1], 0x2000, 0x1000 },
323 { "spi", make_unimp_dev
, &mms
->spi
, 0x3000, 0x1000 },
324 { "i2c0", make_unimp_dev
, &mms
->i2c
[0], 0x4000, 0x1000 },
325 { "i2c1", make_unimp_dev
, &mms
->i2c
[1], 0x5000, 0x1000 },
326 { "i2s", make_unimp_dev
, &mms
->i2s
, 0x6000, 0x1000 },
327 { "pwm0", make_unimp_dev
, &mms
->pwm
[0], 0x7000, 0x1000 },
328 { "rtc", make_rtc
, &mms
->rtc
, 0x8000, 0x1000 },
329 { "qspi", make_unimp_dev
, &mms
->qspi
, 0xa000, 0x1000 },
330 { "timer", make_unimp_dev
, &mms
->timer
, 0xb000, 0x1000 },
331 { "scc", make_unimp_dev
, &mms
->scc
, 0xc000, 0x1000 },
332 { "pwm1", make_unimp_dev
, &mms
->pwm
[1], 0xe000, 0x1000 },
333 { "pwm2", make_unimp_dev
, &mms
->pwm
[2], 0xf000, 0x1000 },
334 { "gpio", make_unimp_dev
, &mms
->gpio
, 0x10000, 0x1000 },
335 { "mpc0", make_mpc
, &mms
->mpc
[0], 0x12000, 0x1000 },
336 { "mpc1", make_mpc
, &mms
->mpc
[1], 0x13000, 0x1000 },
339 memory_region_init(container
, OBJECT(mms
), "musca-device-container", size
);
341 for (i
= 0; i
< ARRAY_SIZE(devices
); i
++) {
342 const PPCPortInfo
*pinfo
= &devices
[i
];
345 mr
= pinfo
->devfn(mms
, pinfo
->opaque
, pinfo
->name
, pinfo
->size
);
346 memory_region_add_subregion(container
, pinfo
->addr
, mr
);
349 return &mms
->container
;
352 static void musca_init(MachineState
*machine
)
354 MuscaMachineState
*mms
= MUSCA_MACHINE(machine
);
355 MuscaMachineClass
*mmc
= MUSCA_MACHINE_GET_CLASS(mms
);
356 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
357 MemoryRegion
*system_memory
= get_system_memory();
359 DeviceState
*dev_splitter
;
364 assert(mmc
->num_irqs
<= MUSCA_NUMIRQ_MAX
);
365 assert(mmc
->num_mpcs
<= MUSCA_MPC_MAX
);
367 if (strcmp(machine
->cpu_type
, mc
->default_cpu_type
) != 0) {
368 error_report("This board can only be used with CPU %s",
369 mc
->default_cpu_type
);
373 object_initialize_child(OBJECT(machine
), "sse-200", &mms
->sse
,
375 ssedev
= DEVICE(&mms
->sse
);
376 object_property_set_link(OBJECT(&mms
->sse
), "memory",
377 OBJECT(system_memory
), &error_fatal
);
378 qdev_prop_set_uint32(ssedev
, "EXP_NUMIRQ", mmc
->num_irqs
);
379 qdev_prop_set_uint32(ssedev
, "init-svtor", mmc
->init_svtor
);
380 qdev_prop_set_uint32(ssedev
, "SRAM_ADDR_WIDTH", mmc
->sram_addr_width
);
381 qdev_prop_set_uint32(ssedev
, "MAINCLK", SYSCLK_FRQ
);
383 * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for
384 * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0.
386 if (mmc
->type
== MUSCA_B1
) {
387 qdev_prop_set_bit(ssedev
, "CPU0_FPU", true);
388 qdev_prop_set_bit(ssedev
, "CPU0_DSP", true);
390 sysbus_realize(SYS_BUS_DEVICE(&mms
->sse
), &error_fatal
);
393 * We need to create splitters to feed the IRQ inputs
394 * for each CPU in the SSE-200 from each device in the board.
396 for (i
= 0; i
< mmc
->num_irqs
; i
++) {
397 char *name
= g_strdup_printf("musca-irq-splitter%d", i
);
398 SplitIRQ
*splitter
= &mms
->cpu_irq_splitter
[i
];
400 object_initialize_child_with_props(OBJECT(machine
), name
, splitter
,
401 sizeof(*splitter
), TYPE_SPLIT_IRQ
,
405 object_property_set_int(OBJECT(splitter
), "num-lines", 2,
407 qdev_realize(DEVICE(splitter
), NULL
, &error_fatal
);
408 qdev_connect_gpio_out(DEVICE(splitter
), 0,
409 qdev_get_gpio_in_named(ssedev
, "EXP_IRQ", i
));
410 qdev_connect_gpio_out(DEVICE(splitter
), 1,
411 qdev_get_gpio_in_named(ssedev
,
416 * The sec_resp_cfg output from the SSE-200 must be split into multiple
417 * lines, one for each of the PPCs we create here.
419 object_initialize_child_with_props(OBJECT(machine
), "sec-resp-splitter",
420 &mms
->sec_resp_splitter
,
421 sizeof(mms
->sec_resp_splitter
),
422 TYPE_SPLIT_IRQ
, &error_fatal
, NULL
);
424 object_property_set_int(OBJECT(&mms
->sec_resp_splitter
), "num-lines",
425 ARRAY_SIZE(mms
->ppc
), &error_fatal
);
426 qdev_realize(DEVICE(&mms
->sec_resp_splitter
), NULL
, &error_fatal
);
427 dev_splitter
= DEVICE(&mms
->sec_resp_splitter
);
428 qdev_connect_gpio_out_named(ssedev
, "sec_resp_cfg", 0,
429 qdev_get_gpio_in(dev_splitter
, 0));
432 * Most of the devices in the board are behind Peripheral Protection
433 * Controllers. The required order for initializing things is:
434 * + initialize the PPC
435 * + initialize, configure and realize downstream devices
436 * + connect downstream device MemoryRegions to the PPC
438 * + map the PPC's MemoryRegions to the places in the address map
439 * where the downstream devices should appear
440 * + wire up the PPC's control lines to the SSE object
442 * The PPC mapping differs for the -A and -B1 variants; the -A version
443 * is much simpler, using only a single port of a single PPC and putting
444 * all the devices behind that.
446 const PPCInfo a_ppcs
[] = { {
447 .name
= "ahb_ppcexp0",
449 { "musca-devices", make_musca_a_devs
, 0, 0x40100000, 0x100000 },
455 * Devices listed with an 0x4.. address appear in both the NS 0x4.. region
456 * and the 0x5.. S region. Devices listed with an 0x5.. address appear
457 * only in the S region.
459 const PPCInfo b1_ppcs
[] = { {
460 .name
= "apb_ppcexp0",
462 { "eflash0", make_unimp_dev
, &mms
->eflash
[0],
463 0x52400000, 0x1000 },
464 { "eflash1", make_unimp_dev
, &mms
->eflash
[1],
465 0x52500000, 0x1000 },
466 { "qspi", make_unimp_dev
, &mms
->qspi
, 0x42800000, 0x100000 },
467 { "mpc0", make_mpc
, &mms
->mpc
[0], 0x52000000, 0x1000 },
468 { "mpc1", make_mpc
, &mms
->mpc
[1], 0x52100000, 0x1000 },
469 { "mpc2", make_mpc
, &mms
->mpc
[2], 0x52200000, 0x1000 },
470 { "mpc3", make_mpc
, &mms
->mpc
[3], 0x52300000, 0x1000 },
471 { "mhu0", make_unimp_dev
, &mms
->mhu
[0], 0x42600000, 0x100000 },
472 { "mhu1", make_unimp_dev
, &mms
->mhu
[1], 0x42700000, 0x100000 },
473 { }, /* port 9: unused */
474 { }, /* port 10: unused */
475 { }, /* port 11: unused */
476 { }, /* port 12: unused */
477 { }, /* port 13: unused */
478 { "mpc4", make_mpc
, &mms
->mpc
[4], 0x52e00000, 0x1000 },
481 .name
= "apb_ppcexp1",
483 { "pwm0", make_unimp_dev
, &mms
->pwm
[0], 0x40101000, 0x1000 },
484 { "pwm1", make_unimp_dev
, &mms
->pwm
[1], 0x40102000, 0x1000 },
485 { "pwm2", make_unimp_dev
, &mms
->pwm
[2], 0x40103000, 0x1000 },
486 { "i2s", make_unimp_dev
, &mms
->i2s
, 0x40104000, 0x1000 },
487 { "uart0", make_uart
, &mms
->uart
[0], 0x40105000, 0x1000 },
488 { "uart1", make_uart
, &mms
->uart
[1], 0x40106000, 0x1000 },
489 { "i2c0", make_unimp_dev
, &mms
->i2c
[0], 0x40108000, 0x1000 },
490 { "i2c1", make_unimp_dev
, &mms
->i2c
[1], 0x40109000, 0x1000 },
491 { "spi", make_unimp_dev
, &mms
->spi
, 0x4010a000, 0x1000 },
492 { "scc", make_unimp_dev
, &mms
->scc
, 0x5010b000, 0x1000 },
493 { "timer", make_unimp_dev
, &mms
->timer
, 0x4010c000, 0x1000 },
494 { "rtc", make_rtc
, &mms
->rtc
, 0x4010d000, 0x1000 },
495 { "pvt", make_unimp_dev
, &mms
->pvt
, 0x4010e000, 0x1000 },
496 { "sdio", make_unimp_dev
, &mms
->sdio
, 0x4010f000, 0x1000 },
499 .name
= "ahb_ppcexp0",
501 { }, /* port 0: unused */
502 { "gpio", make_unimp_dev
, &mms
->gpio
, 0x41000000, 0x1000 },
510 num_ppcs
= ARRAY_SIZE(a_ppcs
);
514 num_ppcs
= ARRAY_SIZE(b1_ppcs
);
517 g_assert_not_reached();
519 assert(num_ppcs
<= MUSCA_PPC_MAX
);
521 for (i
= 0; i
< num_ppcs
; i
++) {
522 const PPCInfo
*ppcinfo
= &ppcs
[i
];
523 TZPPC
*ppc
= &mms
->ppc
[i
];
528 object_initialize_child(OBJECT(machine
), ppcinfo
->name
, ppc
,
530 ppcdev
= DEVICE(ppc
);
532 for (port
= 0; port
< TZ_NUM_PORTS
; port
++) {
533 const PPCPortInfo
*pinfo
= &ppcinfo
->ports
[port
];
541 mr
= pinfo
->devfn(mms
, pinfo
->opaque
, pinfo
->name
, pinfo
->size
);
542 portname
= g_strdup_printf("port[%d]", port
);
543 object_property_set_link(OBJECT(ppc
), portname
, OBJECT(mr
),
548 sysbus_realize(SYS_BUS_DEVICE(ppc
), &error_fatal
);
550 for (port
= 0; port
< TZ_NUM_PORTS
; port
++) {
551 const PPCPortInfo
*pinfo
= &ppcinfo
->ports
[port
];
556 sysbus_mmio_map(SYS_BUS_DEVICE(ppc
), port
, pinfo
->addr
);
558 gpioname
= g_strdup_printf("%s_nonsec", ppcinfo
->name
);
559 qdev_connect_gpio_out_named(ssedev
, gpioname
, port
,
560 qdev_get_gpio_in_named(ppcdev
,
564 gpioname
= g_strdup_printf("%s_ap", ppcinfo
->name
);
565 qdev_connect_gpio_out_named(ssedev
, gpioname
, port
,
566 qdev_get_gpio_in_named(ppcdev
,
571 gpioname
= g_strdup_printf("%s_irq_enable", ppcinfo
->name
);
572 qdev_connect_gpio_out_named(ssedev
, gpioname
, 0,
573 qdev_get_gpio_in_named(ppcdev
,
576 gpioname
= g_strdup_printf("%s_irq_clear", ppcinfo
->name
);
577 qdev_connect_gpio_out_named(ssedev
, gpioname
, 0,
578 qdev_get_gpio_in_named(ppcdev
,
581 gpioname
= g_strdup_printf("%s_irq_status", ppcinfo
->name
);
582 qdev_connect_gpio_out_named(ppcdev
, "irq", 0,
583 qdev_get_gpio_in_named(ssedev
,
587 qdev_connect_gpio_out(dev_splitter
, i
,
588 qdev_get_gpio_in_named(ppcdev
,
592 armv7m_load_kernel(ARM_CPU(first_cpu
), machine
->kernel_filename
, 0x2000000);
595 static void musca_class_init(ObjectClass
*oc
, void *data
)
597 MachineClass
*mc
= MACHINE_CLASS(oc
);
599 mc
->default_cpus
= 2;
600 mc
->min_cpus
= mc
->default_cpus
;
601 mc
->max_cpus
= mc
->default_cpus
;
602 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
603 mc
->init
= musca_init
;
606 static void musca_a_class_init(ObjectClass
*oc
, void *data
)
608 MachineClass
*mc
= MACHINE_CLASS(oc
);
609 MuscaMachineClass
*mmc
= MUSCA_MACHINE_CLASS(oc
);
611 mc
->desc
= "ARM Musca-A board (dual Cortex-M33)";
613 mmc
->init_svtor
= 0x10200000;
614 mmc
->sram_addr_width
= 15;
616 mmc
->mpc_info
= a_mpc_info
;
617 mmc
->num_mpcs
= ARRAY_SIZE(a_mpc_info
);
620 static void musca_b1_class_init(ObjectClass
*oc
, void *data
)
622 MachineClass
*mc
= MACHINE_CLASS(oc
);
623 MuscaMachineClass
*mmc
= MUSCA_MACHINE_CLASS(oc
);
625 mc
->desc
= "ARM Musca-B1 board (dual Cortex-M33)";
626 mmc
->type
= MUSCA_B1
;
628 * This matches the DAPlink firmware which boots from QSPI. There
629 * is also a firmware blob which boots from the eFlash, which
630 * uses init_svtor = 0x1A000000. QEMU doesn't currently support that,
631 * though we could in theory expose a machine property on the command
632 * line to allow the user to request eFlash boot.
634 mmc
->init_svtor
= 0x10000000;
635 mmc
->sram_addr_width
= 17;
637 mmc
->mpc_info
= b1_mpc_info
;
638 mmc
->num_mpcs
= ARRAY_SIZE(b1_mpc_info
);
641 static const TypeInfo musca_info
= {
642 .name
= TYPE_MUSCA_MACHINE
,
643 .parent
= TYPE_MACHINE
,
645 .instance_size
= sizeof(MuscaMachineState
),
646 .class_size
= sizeof(MuscaMachineClass
),
647 .class_init
= musca_class_init
,
650 static const TypeInfo musca_a_info
= {
651 .name
= TYPE_MUSCA_A_MACHINE
,
652 .parent
= TYPE_MUSCA_MACHINE
,
653 .class_init
= musca_a_class_init
,
656 static const TypeInfo musca_b1_info
= {
657 .name
= TYPE_MUSCA_B1_MACHINE
,
658 .parent
= TYPE_MUSCA_MACHINE
,
659 .class_init
= musca_b1_class_init
,
662 static void musca_machine_init(void)
664 type_register_static(&musca_info
);
665 type_register_static(&musca_a_info
);
666 type_register_static(&musca_b1_info
);
669 type_init(musca_machine_init
);