2 * Marvell MV88W8618 / Freecom MusicPal emulation.
4 * Copyright (c) 2008 Jan Kiszka
6 * This code is licensed under the GNU GPL v2.
8 * Contributions after 2012-01-13 are licensed under the terms of the
9 * GNU GPL, version 2 or (at your option) any later version.
12 #include "hw/sysbus.h"
13 #include "hw/arm/arm.h"
14 #include "hw/devices.h"
16 #include "sysemu/sysemu.h"
17 #include "hw/boards.h"
18 #include "hw/char/serial.h"
19 #include "qemu/timer.h"
20 #include "hw/ptimer.h"
21 #include "block/block.h"
22 #include "hw/block/flash.h"
23 #include "ui/console.h"
24 #include "hw/i2c/i2c.h"
25 #include "sysemu/blockdev.h"
26 #include "exec/address-spaces.h"
27 #include "ui/pixel_ops.h"
29 #define MP_MISC_BASE 0x80002000
30 #define MP_MISC_SIZE 0x00001000
32 #define MP_ETH_BASE 0x80008000
33 #define MP_ETH_SIZE 0x00001000
35 #define MP_WLAN_BASE 0x8000C000
36 #define MP_WLAN_SIZE 0x00000800
38 #define MP_UART1_BASE 0x8000C840
39 #define MP_UART2_BASE 0x8000C940
41 #define MP_GPIO_BASE 0x8000D000
42 #define MP_GPIO_SIZE 0x00001000
44 #define MP_FLASHCFG_BASE 0x90006000
45 #define MP_FLASHCFG_SIZE 0x00001000
47 #define MP_AUDIO_BASE 0x90007000
49 #define MP_PIC_BASE 0x90008000
50 #define MP_PIC_SIZE 0x00001000
52 #define MP_PIT_BASE 0x90009000
53 #define MP_PIT_SIZE 0x00001000
55 #define MP_LCD_BASE 0x9000c000
56 #define MP_LCD_SIZE 0x00001000
58 #define MP_SRAM_BASE 0xC0000000
59 #define MP_SRAM_SIZE 0x00020000
61 #define MP_RAM_DEFAULT_SIZE 32*1024*1024
62 #define MP_FLASH_SIZE_MAX 32*1024*1024
64 #define MP_TIMER1_IRQ 4
65 #define MP_TIMER2_IRQ 5
66 #define MP_TIMER3_IRQ 6
67 #define MP_TIMER4_IRQ 7
70 #define MP_UART1_IRQ 11
71 #define MP_UART2_IRQ 11
72 #define MP_GPIO_IRQ 12
74 #define MP_AUDIO_IRQ 30
76 /* Wolfson 8750 I2C address */
77 #define MP_WM_ADDR 0x1A
79 /* Ethernet register offsets */
80 #define MP_ETH_SMIR 0x010
81 #define MP_ETH_PCXR 0x408
82 #define MP_ETH_SDCMR 0x448
83 #define MP_ETH_ICR 0x450
84 #define MP_ETH_IMR 0x458
85 #define MP_ETH_FRDP0 0x480
86 #define MP_ETH_FRDP1 0x484
87 #define MP_ETH_FRDP2 0x488
88 #define MP_ETH_FRDP3 0x48C
89 #define MP_ETH_CRDP0 0x4A0
90 #define MP_ETH_CRDP1 0x4A4
91 #define MP_ETH_CRDP2 0x4A8
92 #define MP_ETH_CRDP3 0x4AC
93 #define MP_ETH_CTDP0 0x4E0
94 #define MP_ETH_CTDP1 0x4E4
95 #define MP_ETH_CTDP2 0x4E8
96 #define MP_ETH_CTDP3 0x4EC
99 #define MP_ETH_SMIR_DATA 0x0000FFFF
100 #define MP_ETH_SMIR_ADDR 0x03FF0000
101 #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */
102 #define MP_ETH_SMIR_RDVALID (1 << 27)
105 #define MP_ETH_PHY1_BMSR 0x00210000
106 #define MP_ETH_PHY1_PHYSID1 0x00410000
107 #define MP_ETH_PHY1_PHYSID2 0x00610000
109 #define MP_PHY_BMSR_LINK 0x0004
110 #define MP_PHY_BMSR_AUTONEG 0x0008
112 #define MP_PHY_88E3015 0x01410E20
114 /* TX descriptor status */
115 #define MP_ETH_TX_OWN (1 << 31)
117 /* RX descriptor status */
118 #define MP_ETH_RX_OWN (1 << 31)
120 /* Interrupt cause/mask bits */
121 #define MP_ETH_IRQ_RX_BIT 0
122 #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT)
123 #define MP_ETH_IRQ_TXHI_BIT 2
124 #define MP_ETH_IRQ_TXLO_BIT 3
126 /* Port config bits */
127 #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */
129 /* SDMA command bits */
130 #define MP_ETH_CMD_TXHI (1 << 23)
131 #define MP_ETH_CMD_TXLO (1 << 22)
133 typedef struct mv88w8618_tx_desc
{
141 typedef struct mv88w8618_rx_desc
{
144 uint16_t buffer_size
;
149 #define TYPE_MV88W8618_ETH "mv88w8618_eth"
150 #define MV88W8618_ETH(obj) \
151 OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH)
153 typedef struct mv88w8618_eth_state
{
155 SysBusDevice parent_obj
;
164 uint32_t vlan_header
;
165 uint32_t tx_queue
[2];
166 uint32_t rx_queue
[4];
167 uint32_t frx_queue
[4];
171 } mv88w8618_eth_state
;
173 static void eth_rx_desc_put(uint32_t addr
, mv88w8618_rx_desc
*desc
)
175 cpu_to_le32s(&desc
->cmdstat
);
176 cpu_to_le16s(&desc
->bytes
);
177 cpu_to_le16s(&desc
->buffer_size
);
178 cpu_to_le32s(&desc
->buffer
);
179 cpu_to_le32s(&desc
->next
);
180 cpu_physical_memory_write(addr
, desc
, sizeof(*desc
));
183 static void eth_rx_desc_get(uint32_t addr
, mv88w8618_rx_desc
*desc
)
185 cpu_physical_memory_read(addr
, desc
, sizeof(*desc
));
186 le32_to_cpus(&desc
->cmdstat
);
187 le16_to_cpus(&desc
->bytes
);
188 le16_to_cpus(&desc
->buffer_size
);
189 le32_to_cpus(&desc
->buffer
);
190 le32_to_cpus(&desc
->next
);
193 static int eth_can_receive(NetClientState
*nc
)
198 static ssize_t
eth_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
200 mv88w8618_eth_state
*s
= qemu_get_nic_opaque(nc
);
202 mv88w8618_rx_desc desc
;
205 for (i
= 0; i
< 4; i
++) {
206 desc_addr
= s
->cur_rx
[i
];
211 eth_rx_desc_get(desc_addr
, &desc
);
212 if ((desc
.cmdstat
& MP_ETH_RX_OWN
) && desc
.buffer_size
>= size
) {
213 cpu_physical_memory_write(desc
.buffer
+ s
->vlan_header
,
215 desc
.bytes
= size
+ s
->vlan_header
;
216 desc
.cmdstat
&= ~MP_ETH_RX_OWN
;
217 s
->cur_rx
[i
] = desc
.next
;
219 s
->icr
|= MP_ETH_IRQ_RX
;
220 if (s
->icr
& s
->imr
) {
221 qemu_irq_raise(s
->irq
);
223 eth_rx_desc_put(desc_addr
, &desc
);
226 desc_addr
= desc
.next
;
227 } while (desc_addr
!= s
->rx_queue
[i
]);
232 static void eth_tx_desc_put(uint32_t addr
, mv88w8618_tx_desc
*desc
)
234 cpu_to_le32s(&desc
->cmdstat
);
235 cpu_to_le16s(&desc
->res
);
236 cpu_to_le16s(&desc
->bytes
);
237 cpu_to_le32s(&desc
->buffer
);
238 cpu_to_le32s(&desc
->next
);
239 cpu_physical_memory_write(addr
, desc
, sizeof(*desc
));
242 static void eth_tx_desc_get(uint32_t addr
, mv88w8618_tx_desc
*desc
)
244 cpu_physical_memory_read(addr
, desc
, sizeof(*desc
));
245 le32_to_cpus(&desc
->cmdstat
);
246 le16_to_cpus(&desc
->res
);
247 le16_to_cpus(&desc
->bytes
);
248 le32_to_cpus(&desc
->buffer
);
249 le32_to_cpus(&desc
->next
);
252 static void eth_send(mv88w8618_eth_state
*s
, int queue_index
)
254 uint32_t desc_addr
= s
->tx_queue
[queue_index
];
255 mv88w8618_tx_desc desc
;
261 eth_tx_desc_get(desc_addr
, &desc
);
262 next_desc
= desc
.next
;
263 if (desc
.cmdstat
& MP_ETH_TX_OWN
) {
266 cpu_physical_memory_read(desc
.buffer
, buf
, len
);
267 qemu_send_packet(qemu_get_queue(s
->nic
), buf
, len
);
269 desc
.cmdstat
&= ~MP_ETH_TX_OWN
;
270 s
->icr
|= 1 << (MP_ETH_IRQ_TXLO_BIT
- queue_index
);
271 eth_tx_desc_put(desc_addr
, &desc
);
273 desc_addr
= next_desc
;
274 } while (desc_addr
!= s
->tx_queue
[queue_index
]);
277 static uint64_t mv88w8618_eth_read(void *opaque
, hwaddr offset
,
280 mv88w8618_eth_state
*s
= opaque
;
284 if (s
->smir
& MP_ETH_SMIR_OPCODE
) {
285 switch (s
->smir
& MP_ETH_SMIR_ADDR
) {
286 case MP_ETH_PHY1_BMSR
:
287 return MP_PHY_BMSR_LINK
| MP_PHY_BMSR_AUTONEG
|
289 case MP_ETH_PHY1_PHYSID1
:
290 return (MP_PHY_88E3015
>> 16) | MP_ETH_SMIR_RDVALID
;
291 case MP_ETH_PHY1_PHYSID2
:
292 return (MP_PHY_88E3015
& 0xFFFF) | MP_ETH_SMIR_RDVALID
;
294 return MP_ETH_SMIR_RDVALID
;
305 case MP_ETH_FRDP0
... MP_ETH_FRDP3
:
306 return s
->frx_queue
[(offset
- MP_ETH_FRDP0
)/4];
308 case MP_ETH_CRDP0
... MP_ETH_CRDP3
:
309 return s
->rx_queue
[(offset
- MP_ETH_CRDP0
)/4];
311 case MP_ETH_CTDP0
... MP_ETH_CTDP3
:
312 return s
->tx_queue
[(offset
- MP_ETH_CTDP0
)/4];
319 static void mv88w8618_eth_write(void *opaque
, hwaddr offset
,
320 uint64_t value
, unsigned size
)
322 mv88w8618_eth_state
*s
= opaque
;
330 s
->vlan_header
= ((value
>> MP_ETH_PCXR_2BSM_BIT
) & 1) * 2;
334 if (value
& MP_ETH_CMD_TXHI
) {
337 if (value
& MP_ETH_CMD_TXLO
) {
340 if (value
& (MP_ETH_CMD_TXHI
| MP_ETH_CMD_TXLO
) && s
->icr
& s
->imr
) {
341 qemu_irq_raise(s
->irq
);
351 if (s
->icr
& s
->imr
) {
352 qemu_irq_raise(s
->irq
);
356 case MP_ETH_FRDP0
... MP_ETH_FRDP3
:
357 s
->frx_queue
[(offset
- MP_ETH_FRDP0
)/4] = value
;
360 case MP_ETH_CRDP0
... MP_ETH_CRDP3
:
361 s
->rx_queue
[(offset
- MP_ETH_CRDP0
)/4] =
362 s
->cur_rx
[(offset
- MP_ETH_CRDP0
)/4] = value
;
365 case MP_ETH_CTDP0
... MP_ETH_CTDP3
:
366 s
->tx_queue
[(offset
- MP_ETH_CTDP0
)/4] = value
;
371 static const MemoryRegionOps mv88w8618_eth_ops
= {
372 .read
= mv88w8618_eth_read
,
373 .write
= mv88w8618_eth_write
,
374 .endianness
= DEVICE_NATIVE_ENDIAN
,
377 static void eth_cleanup(NetClientState
*nc
)
379 mv88w8618_eth_state
*s
= qemu_get_nic_opaque(nc
);
384 static NetClientInfo net_mv88w8618_info
= {
385 .type
= NET_CLIENT_OPTIONS_KIND_NIC
,
386 .size
= sizeof(NICState
),
387 .can_receive
= eth_can_receive
,
388 .receive
= eth_receive
,
389 .cleanup
= eth_cleanup
,
392 static int mv88w8618_eth_init(SysBusDevice
*sbd
)
394 DeviceState
*dev
= DEVICE(sbd
);
395 mv88w8618_eth_state
*s
= MV88W8618_ETH(dev
);
397 sysbus_init_irq(sbd
, &s
->irq
);
398 s
->nic
= qemu_new_nic(&net_mv88w8618_info
, &s
->conf
,
399 object_get_typename(OBJECT(dev
)), dev
->id
, s
);
400 memory_region_init_io(&s
->iomem
, OBJECT(s
), &mv88w8618_eth_ops
, s
,
401 "mv88w8618-eth", MP_ETH_SIZE
);
402 sysbus_init_mmio(sbd
, &s
->iomem
);
406 static const VMStateDescription mv88w8618_eth_vmsd
= {
407 .name
= "mv88w8618_eth",
409 .minimum_version_id
= 1,
410 .minimum_version_id_old
= 1,
411 .fields
= (VMStateField
[]) {
412 VMSTATE_UINT32(smir
, mv88w8618_eth_state
),
413 VMSTATE_UINT32(icr
, mv88w8618_eth_state
),
414 VMSTATE_UINT32(imr
, mv88w8618_eth_state
),
415 VMSTATE_UINT32(vlan_header
, mv88w8618_eth_state
),
416 VMSTATE_UINT32_ARRAY(tx_queue
, mv88w8618_eth_state
, 2),
417 VMSTATE_UINT32_ARRAY(rx_queue
, mv88w8618_eth_state
, 4),
418 VMSTATE_UINT32_ARRAY(frx_queue
, mv88w8618_eth_state
, 4),
419 VMSTATE_UINT32_ARRAY(cur_rx
, mv88w8618_eth_state
, 4),
420 VMSTATE_END_OF_LIST()
424 static Property mv88w8618_eth_properties
[] = {
425 DEFINE_NIC_PROPERTIES(mv88w8618_eth_state
, conf
),
426 DEFINE_PROP_END_OF_LIST(),
429 static void mv88w8618_eth_class_init(ObjectClass
*klass
, void *data
)
431 DeviceClass
*dc
= DEVICE_CLASS(klass
);
432 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
434 k
->init
= mv88w8618_eth_init
;
435 dc
->vmsd
= &mv88w8618_eth_vmsd
;
436 dc
->props
= mv88w8618_eth_properties
;
439 static const TypeInfo mv88w8618_eth_info
= {
440 .name
= TYPE_MV88W8618_ETH
,
441 .parent
= TYPE_SYS_BUS_DEVICE
,
442 .instance_size
= sizeof(mv88w8618_eth_state
),
443 .class_init
= mv88w8618_eth_class_init
,
446 /* LCD register offsets */
447 #define MP_LCD_IRQCTRL 0x180
448 #define MP_LCD_IRQSTAT 0x184
449 #define MP_LCD_SPICTRL 0x1ac
450 #define MP_LCD_INST 0x1bc
451 #define MP_LCD_DATA 0x1c0
454 #define MP_LCD_SPI_DATA 0x00100011
455 #define MP_LCD_SPI_CMD 0x00104011
456 #define MP_LCD_SPI_INVALID 0x00000000
459 #define MP_LCD_INST_SETPAGE0 0xB0
461 #define MP_LCD_INST_SETPAGE7 0xB7
463 #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
465 #define TYPE_MUSICPAL_LCD "musicpal_lcd"
466 #define MUSICPAL_LCD(obj) \
467 OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD)
469 typedef struct musicpal_lcd_state
{
471 SysBusDevice parent_obj
;
481 uint8_t video_ram
[128*64/8];
482 } musicpal_lcd_state
;
484 static uint8_t scale_lcd_color(musicpal_lcd_state
*s
, uint8_t col
)
486 switch (s
->brightness
) {
492 return (col
* s
->brightness
) / 7;
496 #define SET_LCD_PIXEL(depth, type) \
497 static inline void glue(set_lcd_pixel, depth) \
498 (musicpal_lcd_state *s, int x, int y, type col) \
501 DisplaySurface *surface = qemu_console_surface(s->con); \
502 type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \
504 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
505 for (dx = 0; dx < 3; dx++, pixel++) \
508 SET_LCD_PIXEL(8, uint8_t)
509 SET_LCD_PIXEL(16, uint16_t)
510 SET_LCD_PIXEL(32, uint32_t)
512 static void lcd_refresh(void *opaque
)
514 musicpal_lcd_state
*s
= opaque
;
515 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
518 switch (surface_bits_per_pixel(surface
)) {
521 #define LCD_REFRESH(depth, func) \
523 col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
524 scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
525 scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
526 for (x = 0; x < 128; x++) { \
527 for (y = 0; y < 64; y++) { \
528 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
529 glue(set_lcd_pixel, depth)(s, x, y, col); \
531 glue(set_lcd_pixel, depth)(s, x, y, 0); \
536 LCD_REFRESH(8, rgb_to_pixel8
)
537 LCD_REFRESH(16, rgb_to_pixel16
)
538 LCD_REFRESH(32, (is_surface_bgr(surface
) ?
539 rgb_to_pixel32bgr
: rgb_to_pixel32
))
541 hw_error("unsupported colour depth %i\n",
542 surface_bits_per_pixel(surface
));
545 dpy_gfx_update(s
->con
, 0, 0, 128*3, 64*3);
548 static void lcd_invalidate(void *opaque
)
552 static void musicpal_lcd_gpio_brightness_in(void *opaque
, int irq
, int level
)
554 musicpal_lcd_state
*s
= opaque
;
555 s
->brightness
&= ~(1 << irq
);
556 s
->brightness
|= level
<< irq
;
559 static uint64_t musicpal_lcd_read(void *opaque
, hwaddr offset
,
562 musicpal_lcd_state
*s
= opaque
;
573 static void musicpal_lcd_write(void *opaque
, hwaddr offset
,
574 uint64_t value
, unsigned size
)
576 musicpal_lcd_state
*s
= opaque
;
584 if (value
== MP_LCD_SPI_DATA
|| value
== MP_LCD_SPI_CMD
) {
587 s
->mode
= MP_LCD_SPI_INVALID
;
592 if (value
>= MP_LCD_INST_SETPAGE0
&& value
<= MP_LCD_INST_SETPAGE7
) {
593 s
->page
= value
- MP_LCD_INST_SETPAGE0
;
599 if (s
->mode
== MP_LCD_SPI_CMD
) {
600 if (value
>= MP_LCD_INST_SETPAGE0
&&
601 value
<= MP_LCD_INST_SETPAGE7
) {
602 s
->page
= value
- MP_LCD_INST_SETPAGE0
;
605 } else if (s
->mode
== MP_LCD_SPI_DATA
) {
606 s
->video_ram
[s
->page
*128 + s
->page_off
] = value
;
607 s
->page_off
= (s
->page_off
+ 1) & 127;
613 static const MemoryRegionOps musicpal_lcd_ops
= {
614 .read
= musicpal_lcd_read
,
615 .write
= musicpal_lcd_write
,
616 .endianness
= DEVICE_NATIVE_ENDIAN
,
619 static const GraphicHwOps musicpal_gfx_ops
= {
620 .invalidate
= lcd_invalidate
,
621 .gfx_update
= lcd_refresh
,
624 static int musicpal_lcd_init(SysBusDevice
*sbd
)
626 DeviceState
*dev
= DEVICE(sbd
);
627 musicpal_lcd_state
*s
= MUSICPAL_LCD(dev
);
631 memory_region_init_io(&s
->iomem
, OBJECT(s
), &musicpal_lcd_ops
, s
,
632 "musicpal-lcd", MP_LCD_SIZE
);
633 sysbus_init_mmio(sbd
, &s
->iomem
);
635 s
->con
= graphic_console_init(dev
, &musicpal_gfx_ops
, s
);
636 qemu_console_resize(s
->con
, 128*3, 64*3);
638 qdev_init_gpio_in(dev
, musicpal_lcd_gpio_brightness_in
, 3);
643 static const VMStateDescription musicpal_lcd_vmsd
= {
644 .name
= "musicpal_lcd",
646 .minimum_version_id
= 1,
647 .minimum_version_id_old
= 1,
648 .fields
= (VMStateField
[]) {
649 VMSTATE_UINT32(brightness
, musicpal_lcd_state
),
650 VMSTATE_UINT32(mode
, musicpal_lcd_state
),
651 VMSTATE_UINT32(irqctrl
, musicpal_lcd_state
),
652 VMSTATE_UINT32(page
, musicpal_lcd_state
),
653 VMSTATE_UINT32(page_off
, musicpal_lcd_state
),
654 VMSTATE_BUFFER(video_ram
, musicpal_lcd_state
),
655 VMSTATE_END_OF_LIST()
659 static void musicpal_lcd_class_init(ObjectClass
*klass
, void *data
)
661 DeviceClass
*dc
= DEVICE_CLASS(klass
);
662 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
664 k
->init
= musicpal_lcd_init
;
665 dc
->vmsd
= &musicpal_lcd_vmsd
;
668 static const TypeInfo musicpal_lcd_info
= {
669 .name
= TYPE_MUSICPAL_LCD
,
670 .parent
= TYPE_SYS_BUS_DEVICE
,
671 .instance_size
= sizeof(musicpal_lcd_state
),
672 .class_init
= musicpal_lcd_class_init
,
675 /* PIC register offsets */
676 #define MP_PIC_STATUS 0x00
677 #define MP_PIC_ENABLE_SET 0x08
678 #define MP_PIC_ENABLE_CLR 0x0C
680 #define TYPE_MV88W8618_PIC "mv88w8618_pic"
681 #define MV88W8618_PIC(obj) \
682 OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC)
684 typedef struct mv88w8618_pic_state
{
686 SysBusDevice parent_obj
;
693 } mv88w8618_pic_state
;
695 static void mv88w8618_pic_update(mv88w8618_pic_state
*s
)
697 qemu_set_irq(s
->parent_irq
, (s
->level
& s
->enabled
));
700 static void mv88w8618_pic_set_irq(void *opaque
, int irq
, int level
)
702 mv88w8618_pic_state
*s
= opaque
;
705 s
->level
|= 1 << irq
;
707 s
->level
&= ~(1 << irq
);
709 mv88w8618_pic_update(s
);
712 static uint64_t mv88w8618_pic_read(void *opaque
, hwaddr offset
,
715 mv88w8618_pic_state
*s
= opaque
;
719 return s
->level
& s
->enabled
;
726 static void mv88w8618_pic_write(void *opaque
, hwaddr offset
,
727 uint64_t value
, unsigned size
)
729 mv88w8618_pic_state
*s
= opaque
;
732 case MP_PIC_ENABLE_SET
:
736 case MP_PIC_ENABLE_CLR
:
737 s
->enabled
&= ~value
;
741 mv88w8618_pic_update(s
);
744 static void mv88w8618_pic_reset(DeviceState
*d
)
746 mv88w8618_pic_state
*s
= MV88W8618_PIC(d
);
752 static const MemoryRegionOps mv88w8618_pic_ops
= {
753 .read
= mv88w8618_pic_read
,
754 .write
= mv88w8618_pic_write
,
755 .endianness
= DEVICE_NATIVE_ENDIAN
,
758 static int mv88w8618_pic_init(SysBusDevice
*dev
)
760 mv88w8618_pic_state
*s
= MV88W8618_PIC(dev
);
762 qdev_init_gpio_in(DEVICE(dev
), mv88w8618_pic_set_irq
, 32);
763 sysbus_init_irq(dev
, &s
->parent_irq
);
764 memory_region_init_io(&s
->iomem
, OBJECT(s
), &mv88w8618_pic_ops
, s
,
765 "musicpal-pic", MP_PIC_SIZE
);
766 sysbus_init_mmio(dev
, &s
->iomem
);
770 static const VMStateDescription mv88w8618_pic_vmsd
= {
771 .name
= "mv88w8618_pic",
773 .minimum_version_id
= 1,
774 .minimum_version_id_old
= 1,
775 .fields
= (VMStateField
[]) {
776 VMSTATE_UINT32(level
, mv88w8618_pic_state
),
777 VMSTATE_UINT32(enabled
, mv88w8618_pic_state
),
778 VMSTATE_END_OF_LIST()
782 static void mv88w8618_pic_class_init(ObjectClass
*klass
, void *data
)
784 DeviceClass
*dc
= DEVICE_CLASS(klass
);
785 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
787 k
->init
= mv88w8618_pic_init
;
788 dc
->reset
= mv88w8618_pic_reset
;
789 dc
->vmsd
= &mv88w8618_pic_vmsd
;
792 static const TypeInfo mv88w8618_pic_info
= {
793 .name
= TYPE_MV88W8618_PIC
,
794 .parent
= TYPE_SYS_BUS_DEVICE
,
795 .instance_size
= sizeof(mv88w8618_pic_state
),
796 .class_init
= mv88w8618_pic_class_init
,
799 /* PIT register offsets */
800 #define MP_PIT_TIMER1_LENGTH 0x00
802 #define MP_PIT_TIMER4_LENGTH 0x0C
803 #define MP_PIT_CONTROL 0x10
804 #define MP_PIT_TIMER1_VALUE 0x14
806 #define MP_PIT_TIMER4_VALUE 0x20
807 #define MP_BOARD_RESET 0x34
809 /* Magic board reset value (probably some watchdog behind it) */
810 #define MP_BOARD_RESET_MAGIC 0x10000
812 typedef struct mv88w8618_timer_state
{
813 ptimer_state
*ptimer
;
817 } mv88w8618_timer_state
;
819 #define TYPE_MV88W8618_PIT "mv88w8618_pit"
820 #define MV88W8618_PIT(obj) \
821 OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT)
823 typedef struct mv88w8618_pit_state
{
825 SysBusDevice parent_obj
;
829 mv88w8618_timer_state timer
[4];
830 } mv88w8618_pit_state
;
832 static void mv88w8618_timer_tick(void *opaque
)
834 mv88w8618_timer_state
*s
= opaque
;
836 qemu_irq_raise(s
->irq
);
839 static void mv88w8618_timer_init(SysBusDevice
*dev
, mv88w8618_timer_state
*s
,
844 sysbus_init_irq(dev
, &s
->irq
);
847 bh
= qemu_bh_new(mv88w8618_timer_tick
, s
);
848 s
->ptimer
= ptimer_init(bh
);
851 static uint64_t mv88w8618_pit_read(void *opaque
, hwaddr offset
,
854 mv88w8618_pit_state
*s
= opaque
;
855 mv88w8618_timer_state
*t
;
858 case MP_PIT_TIMER1_VALUE
... MP_PIT_TIMER4_VALUE
:
859 t
= &s
->timer
[(offset
-MP_PIT_TIMER1_VALUE
) >> 2];
860 return ptimer_get_count(t
->ptimer
);
867 static void mv88w8618_pit_write(void *opaque
, hwaddr offset
,
868 uint64_t value
, unsigned size
)
870 mv88w8618_pit_state
*s
= opaque
;
871 mv88w8618_timer_state
*t
;
875 case MP_PIT_TIMER1_LENGTH
... MP_PIT_TIMER4_LENGTH
:
876 t
= &s
->timer
[offset
>> 2];
879 ptimer_set_limit(t
->ptimer
, t
->limit
, 1);
881 ptimer_stop(t
->ptimer
);
886 for (i
= 0; i
< 4; i
++) {
888 if (value
& 0xf && t
->limit
> 0) {
889 ptimer_set_limit(t
->ptimer
, t
->limit
, 0);
890 ptimer_set_freq(t
->ptimer
, t
->freq
);
891 ptimer_run(t
->ptimer
, 0);
893 ptimer_stop(t
->ptimer
);
900 if (value
== MP_BOARD_RESET_MAGIC
) {
901 qemu_system_reset_request();
907 static void mv88w8618_pit_reset(DeviceState
*d
)
909 mv88w8618_pit_state
*s
= MV88W8618_PIT(d
);
912 for (i
= 0; i
< 4; i
++) {
913 ptimer_stop(s
->timer
[i
].ptimer
);
914 s
->timer
[i
].limit
= 0;
918 static const MemoryRegionOps mv88w8618_pit_ops
= {
919 .read
= mv88w8618_pit_read
,
920 .write
= mv88w8618_pit_write
,
921 .endianness
= DEVICE_NATIVE_ENDIAN
,
924 static int mv88w8618_pit_init(SysBusDevice
*dev
)
926 mv88w8618_pit_state
*s
= MV88W8618_PIT(dev
);
929 /* Letting them all run at 1 MHz is likely just a pragmatic
931 for (i
= 0; i
< 4; i
++) {
932 mv88w8618_timer_init(dev
, &s
->timer
[i
], 1000000);
935 memory_region_init_io(&s
->iomem
, OBJECT(s
), &mv88w8618_pit_ops
, s
,
936 "musicpal-pit", MP_PIT_SIZE
);
937 sysbus_init_mmio(dev
, &s
->iomem
);
941 static const VMStateDescription mv88w8618_timer_vmsd
= {
944 .minimum_version_id
= 1,
945 .minimum_version_id_old
= 1,
946 .fields
= (VMStateField
[]) {
947 VMSTATE_PTIMER(ptimer
, mv88w8618_timer_state
),
948 VMSTATE_UINT32(limit
, mv88w8618_timer_state
),
949 VMSTATE_END_OF_LIST()
953 static const VMStateDescription mv88w8618_pit_vmsd
= {
954 .name
= "mv88w8618_pit",
956 .minimum_version_id
= 1,
957 .minimum_version_id_old
= 1,
958 .fields
= (VMStateField
[]) {
959 VMSTATE_STRUCT_ARRAY(timer
, mv88w8618_pit_state
, 4, 1,
960 mv88w8618_timer_vmsd
, mv88w8618_timer_state
),
961 VMSTATE_END_OF_LIST()
965 static void mv88w8618_pit_class_init(ObjectClass
*klass
, void *data
)
967 DeviceClass
*dc
= DEVICE_CLASS(klass
);
968 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
970 k
->init
= mv88w8618_pit_init
;
971 dc
->reset
= mv88w8618_pit_reset
;
972 dc
->vmsd
= &mv88w8618_pit_vmsd
;
975 static const TypeInfo mv88w8618_pit_info
= {
976 .name
= TYPE_MV88W8618_PIT
,
977 .parent
= TYPE_SYS_BUS_DEVICE
,
978 .instance_size
= sizeof(mv88w8618_pit_state
),
979 .class_init
= mv88w8618_pit_class_init
,
982 /* Flash config register offsets */
983 #define MP_FLASHCFG_CFGR0 0x04
985 #define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg"
986 #define MV88W8618_FLASHCFG(obj) \
987 OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG)
989 typedef struct mv88w8618_flashcfg_state
{
991 SysBusDevice parent_obj
;
996 } mv88w8618_flashcfg_state
;
998 static uint64_t mv88w8618_flashcfg_read(void *opaque
,
1002 mv88w8618_flashcfg_state
*s
= opaque
;
1005 case MP_FLASHCFG_CFGR0
:
1013 static void mv88w8618_flashcfg_write(void *opaque
, hwaddr offset
,
1014 uint64_t value
, unsigned size
)
1016 mv88w8618_flashcfg_state
*s
= opaque
;
1019 case MP_FLASHCFG_CFGR0
:
1025 static const MemoryRegionOps mv88w8618_flashcfg_ops
= {
1026 .read
= mv88w8618_flashcfg_read
,
1027 .write
= mv88w8618_flashcfg_write
,
1028 .endianness
= DEVICE_NATIVE_ENDIAN
,
1031 static int mv88w8618_flashcfg_init(SysBusDevice
*dev
)
1033 mv88w8618_flashcfg_state
*s
= MV88W8618_FLASHCFG(dev
);
1035 s
->cfgr0
= 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1036 memory_region_init_io(&s
->iomem
, OBJECT(s
), &mv88w8618_flashcfg_ops
, s
,
1037 "musicpal-flashcfg", MP_FLASHCFG_SIZE
);
1038 sysbus_init_mmio(dev
, &s
->iomem
);
1042 static const VMStateDescription mv88w8618_flashcfg_vmsd
= {
1043 .name
= "mv88w8618_flashcfg",
1045 .minimum_version_id
= 1,
1046 .minimum_version_id_old
= 1,
1047 .fields
= (VMStateField
[]) {
1048 VMSTATE_UINT32(cfgr0
, mv88w8618_flashcfg_state
),
1049 VMSTATE_END_OF_LIST()
1053 static void mv88w8618_flashcfg_class_init(ObjectClass
*klass
, void *data
)
1055 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1056 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1058 k
->init
= mv88w8618_flashcfg_init
;
1059 dc
->vmsd
= &mv88w8618_flashcfg_vmsd
;
1062 static const TypeInfo mv88w8618_flashcfg_info
= {
1063 .name
= TYPE_MV88W8618_FLASHCFG
,
1064 .parent
= TYPE_SYS_BUS_DEVICE
,
1065 .instance_size
= sizeof(mv88w8618_flashcfg_state
),
1066 .class_init
= mv88w8618_flashcfg_class_init
,
1069 /* Misc register offsets */
1070 #define MP_MISC_BOARD_REVISION 0x18
1072 #define MP_BOARD_REVISION 0x31
1075 SysBusDevice parent_obj
;
1077 } MusicPalMiscState
;
1079 #define TYPE_MUSICPAL_MISC "musicpal-misc"
1080 #define MUSICPAL_MISC(obj) \
1081 OBJECT_CHECK(MusicPalMiscState, (obj), TYPE_MUSICPAL_MISC)
1083 static uint64_t musicpal_misc_read(void *opaque
, hwaddr offset
,
1087 case MP_MISC_BOARD_REVISION
:
1088 return MP_BOARD_REVISION
;
1095 static void musicpal_misc_write(void *opaque
, hwaddr offset
,
1096 uint64_t value
, unsigned size
)
1100 static const MemoryRegionOps musicpal_misc_ops
= {
1101 .read
= musicpal_misc_read
,
1102 .write
= musicpal_misc_write
,
1103 .endianness
= DEVICE_NATIVE_ENDIAN
,
1106 static void musicpal_misc_init(Object
*obj
)
1108 SysBusDevice
*sd
= SYS_BUS_DEVICE(obj
);
1109 MusicPalMiscState
*s
= MUSICPAL_MISC(obj
);
1111 memory_region_init_io(&s
->iomem
, OBJECT(s
), &musicpal_misc_ops
, NULL
,
1112 "musicpal-misc", MP_MISC_SIZE
);
1113 sysbus_init_mmio(sd
, &s
->iomem
);
1116 static const TypeInfo musicpal_misc_info
= {
1117 .name
= TYPE_MUSICPAL_MISC
,
1118 .parent
= TYPE_SYS_BUS_DEVICE
,
1119 .instance_init
= musicpal_misc_init
,
1120 .instance_size
= sizeof(MusicPalMiscState
),
1123 /* WLAN register offsets */
1124 #define MP_WLAN_MAGIC1 0x11c
1125 #define MP_WLAN_MAGIC2 0x124
1127 static uint64_t mv88w8618_wlan_read(void *opaque
, hwaddr offset
,
1131 /* Workaround to allow loading the binary-only wlandrv.ko crap
1132 * from the original Freecom firmware. */
1133 case MP_WLAN_MAGIC1
:
1135 case MP_WLAN_MAGIC2
:
1143 static void mv88w8618_wlan_write(void *opaque
, hwaddr offset
,
1144 uint64_t value
, unsigned size
)
1148 static const MemoryRegionOps mv88w8618_wlan_ops
= {
1149 .read
= mv88w8618_wlan_read
,
1150 .write
=mv88w8618_wlan_write
,
1151 .endianness
= DEVICE_NATIVE_ENDIAN
,
1154 static int mv88w8618_wlan_init(SysBusDevice
*dev
)
1156 MemoryRegion
*iomem
= g_new(MemoryRegion
, 1);
1158 memory_region_init_io(iomem
, OBJECT(dev
), &mv88w8618_wlan_ops
, NULL
,
1159 "musicpal-wlan", MP_WLAN_SIZE
);
1160 sysbus_init_mmio(dev
, iomem
);
1164 /* GPIO register offsets */
1165 #define MP_GPIO_OE_LO 0x008
1166 #define MP_GPIO_OUT_LO 0x00c
1167 #define MP_GPIO_IN_LO 0x010
1168 #define MP_GPIO_IER_LO 0x014
1169 #define MP_GPIO_IMR_LO 0x018
1170 #define MP_GPIO_ISR_LO 0x020
1171 #define MP_GPIO_OE_HI 0x508
1172 #define MP_GPIO_OUT_HI 0x50c
1173 #define MP_GPIO_IN_HI 0x510
1174 #define MP_GPIO_IER_HI 0x514
1175 #define MP_GPIO_IMR_HI 0x518
1176 #define MP_GPIO_ISR_HI 0x520
1178 /* GPIO bits & masks */
1179 #define MP_GPIO_LCD_BRIGHTNESS 0x00070000
1180 #define MP_GPIO_I2C_DATA_BIT 29
1181 #define MP_GPIO_I2C_CLOCK_BIT 30
1183 /* LCD brightness bits in GPIO_OE_HI */
1184 #define MP_OE_LCD_BRIGHTNESS 0x0007
1186 #define TYPE_MUSICPAL_GPIO "musicpal_gpio"
1187 #define MUSICPAL_GPIO(obj) \
1188 OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO)
1190 typedef struct musicpal_gpio_state
{
1192 SysBusDevice parent_obj
;
1196 uint32_t lcd_brightness
;
1203 qemu_irq out
[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1204 } musicpal_gpio_state
;
1206 static void musicpal_gpio_brightness_update(musicpal_gpio_state
*s
) {
1208 uint32_t brightness
;
1210 /* compute brightness ratio */
1211 switch (s
->lcd_brightness
) {
1245 /* set lcd brightness GPIOs */
1246 for (i
= 0; i
<= 2; i
++) {
1247 qemu_set_irq(s
->out
[i
], (brightness
>> i
) & 1);
1251 static void musicpal_gpio_pin_event(void *opaque
, int pin
, int level
)
1253 musicpal_gpio_state
*s
= opaque
;
1254 uint32_t mask
= 1 << pin
;
1255 uint32_t delta
= level
<< pin
;
1256 uint32_t old
= s
->in_state
& mask
;
1258 s
->in_state
&= ~mask
;
1259 s
->in_state
|= delta
;
1261 if ((old
^ delta
) &&
1262 ((level
&& (s
->imr
& mask
)) || (!level
&& (s
->ier
& mask
)))) {
1264 qemu_irq_raise(s
->irq
);
1268 static uint64_t musicpal_gpio_read(void *opaque
, hwaddr offset
,
1271 musicpal_gpio_state
*s
= opaque
;
1274 case MP_GPIO_OE_HI
: /* used for LCD brightness control */
1275 return s
->lcd_brightness
& MP_OE_LCD_BRIGHTNESS
;
1277 case MP_GPIO_OUT_LO
:
1278 return s
->out_state
& 0xFFFF;
1279 case MP_GPIO_OUT_HI
:
1280 return s
->out_state
>> 16;
1283 return s
->in_state
& 0xFFFF;
1285 return s
->in_state
>> 16;
1287 case MP_GPIO_IER_LO
:
1288 return s
->ier
& 0xFFFF;
1289 case MP_GPIO_IER_HI
:
1290 return s
->ier
>> 16;
1292 case MP_GPIO_IMR_LO
:
1293 return s
->imr
& 0xFFFF;
1294 case MP_GPIO_IMR_HI
:
1295 return s
->imr
>> 16;
1297 case MP_GPIO_ISR_LO
:
1298 return s
->isr
& 0xFFFF;
1299 case MP_GPIO_ISR_HI
:
1300 return s
->isr
>> 16;
1307 static void musicpal_gpio_write(void *opaque
, hwaddr offset
,
1308 uint64_t value
, unsigned size
)
1310 musicpal_gpio_state
*s
= opaque
;
1312 case MP_GPIO_OE_HI
: /* used for LCD brightness control */
1313 s
->lcd_brightness
= (s
->lcd_brightness
& MP_GPIO_LCD_BRIGHTNESS
) |
1314 (value
& MP_OE_LCD_BRIGHTNESS
);
1315 musicpal_gpio_brightness_update(s
);
1318 case MP_GPIO_OUT_LO
:
1319 s
->out_state
= (s
->out_state
& 0xFFFF0000) | (value
& 0xFFFF);
1321 case MP_GPIO_OUT_HI
:
1322 s
->out_state
= (s
->out_state
& 0xFFFF) | (value
<< 16);
1323 s
->lcd_brightness
= (s
->lcd_brightness
& 0xFFFF) |
1324 (s
->out_state
& MP_GPIO_LCD_BRIGHTNESS
);
1325 musicpal_gpio_brightness_update(s
);
1326 qemu_set_irq(s
->out
[3], (s
->out_state
>> MP_GPIO_I2C_DATA_BIT
) & 1);
1327 qemu_set_irq(s
->out
[4], (s
->out_state
>> MP_GPIO_I2C_CLOCK_BIT
) & 1);
1330 case MP_GPIO_IER_LO
:
1331 s
->ier
= (s
->ier
& 0xFFFF0000) | (value
& 0xFFFF);
1333 case MP_GPIO_IER_HI
:
1334 s
->ier
= (s
->ier
& 0xFFFF) | (value
<< 16);
1337 case MP_GPIO_IMR_LO
:
1338 s
->imr
= (s
->imr
& 0xFFFF0000) | (value
& 0xFFFF);
1340 case MP_GPIO_IMR_HI
:
1341 s
->imr
= (s
->imr
& 0xFFFF) | (value
<< 16);
1346 static const MemoryRegionOps musicpal_gpio_ops
= {
1347 .read
= musicpal_gpio_read
,
1348 .write
= musicpal_gpio_write
,
1349 .endianness
= DEVICE_NATIVE_ENDIAN
,
1352 static void musicpal_gpio_reset(DeviceState
*d
)
1354 musicpal_gpio_state
*s
= MUSICPAL_GPIO(d
);
1356 s
->lcd_brightness
= 0;
1358 s
->in_state
= 0xffffffff;
1364 static int musicpal_gpio_init(SysBusDevice
*sbd
)
1366 DeviceState
*dev
= DEVICE(sbd
);
1367 musicpal_gpio_state
*s
= MUSICPAL_GPIO(dev
);
1369 sysbus_init_irq(sbd
, &s
->irq
);
1371 memory_region_init_io(&s
->iomem
, OBJECT(s
), &musicpal_gpio_ops
, s
,
1372 "musicpal-gpio", MP_GPIO_SIZE
);
1373 sysbus_init_mmio(sbd
, &s
->iomem
);
1375 qdev_init_gpio_out(dev
, s
->out
, ARRAY_SIZE(s
->out
));
1377 qdev_init_gpio_in(dev
, musicpal_gpio_pin_event
, 32);
1382 static const VMStateDescription musicpal_gpio_vmsd
= {
1383 .name
= "musicpal_gpio",
1385 .minimum_version_id
= 1,
1386 .minimum_version_id_old
= 1,
1387 .fields
= (VMStateField
[]) {
1388 VMSTATE_UINT32(lcd_brightness
, musicpal_gpio_state
),
1389 VMSTATE_UINT32(out_state
, musicpal_gpio_state
),
1390 VMSTATE_UINT32(in_state
, musicpal_gpio_state
),
1391 VMSTATE_UINT32(ier
, musicpal_gpio_state
),
1392 VMSTATE_UINT32(imr
, musicpal_gpio_state
),
1393 VMSTATE_UINT32(isr
, musicpal_gpio_state
),
1394 VMSTATE_END_OF_LIST()
1398 static void musicpal_gpio_class_init(ObjectClass
*klass
, void *data
)
1400 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1401 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1403 k
->init
= musicpal_gpio_init
;
1404 dc
->reset
= musicpal_gpio_reset
;
1405 dc
->vmsd
= &musicpal_gpio_vmsd
;
1408 static const TypeInfo musicpal_gpio_info
= {
1409 .name
= TYPE_MUSICPAL_GPIO
,
1410 .parent
= TYPE_SYS_BUS_DEVICE
,
1411 .instance_size
= sizeof(musicpal_gpio_state
),
1412 .class_init
= musicpal_gpio_class_init
,
1415 /* Keyboard codes & masks */
1416 #define KEY_RELEASED 0x80
1417 #define KEY_CODE 0x7f
1419 #define KEYCODE_TAB 0x0f
1420 #define KEYCODE_ENTER 0x1c
1421 #define KEYCODE_F 0x21
1422 #define KEYCODE_M 0x32
1424 #define KEYCODE_EXTENDED 0xe0
1425 #define KEYCODE_UP 0x48
1426 #define KEYCODE_DOWN 0x50
1427 #define KEYCODE_LEFT 0x4b
1428 #define KEYCODE_RIGHT 0x4d
1430 #define MP_KEY_WHEEL_VOL (1 << 0)
1431 #define MP_KEY_WHEEL_VOL_INV (1 << 1)
1432 #define MP_KEY_WHEEL_NAV (1 << 2)
1433 #define MP_KEY_WHEEL_NAV_INV (1 << 3)
1434 #define MP_KEY_BTN_FAVORITS (1 << 4)
1435 #define MP_KEY_BTN_MENU (1 << 5)
1436 #define MP_KEY_BTN_VOLUME (1 << 6)
1437 #define MP_KEY_BTN_NAVIGATION (1 << 7)
1439 #define TYPE_MUSICPAL_KEY "musicpal_key"
1440 #define MUSICPAL_KEY(obj) \
1441 OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY)
1443 typedef struct musicpal_key_state
{
1445 SysBusDevice parent_obj
;
1449 uint32_t kbd_extended
;
1450 uint32_t pressed_keys
;
1452 } musicpal_key_state
;
1454 static void musicpal_key_event(void *opaque
, int keycode
)
1456 musicpal_key_state
*s
= opaque
;
1460 if (keycode
== KEYCODE_EXTENDED
) {
1461 s
->kbd_extended
= 1;
1465 if (s
->kbd_extended
) {
1466 switch (keycode
& KEY_CODE
) {
1468 event
= MP_KEY_WHEEL_NAV
| MP_KEY_WHEEL_NAV_INV
;
1472 event
= MP_KEY_WHEEL_NAV
;
1476 event
= MP_KEY_WHEEL_VOL
| MP_KEY_WHEEL_VOL_INV
;
1480 event
= MP_KEY_WHEEL_VOL
;
1484 switch (keycode
& KEY_CODE
) {
1486 event
= MP_KEY_BTN_FAVORITS
;
1490 event
= MP_KEY_BTN_VOLUME
;
1494 event
= MP_KEY_BTN_NAVIGATION
;
1498 event
= MP_KEY_BTN_MENU
;
1501 /* Do not repeat already pressed buttons */
1502 if (!(keycode
& KEY_RELEASED
) && (s
->pressed_keys
& event
)) {
1508 /* Raise GPIO pin first if repeating a key */
1509 if (!(keycode
& KEY_RELEASED
) && (s
->pressed_keys
& event
)) {
1510 for (i
= 0; i
<= 7; i
++) {
1511 if (event
& (1 << i
)) {
1512 qemu_set_irq(s
->out
[i
], 1);
1516 for (i
= 0; i
<= 7; i
++) {
1517 if (event
& (1 << i
)) {
1518 qemu_set_irq(s
->out
[i
], !!(keycode
& KEY_RELEASED
));
1521 if (keycode
& KEY_RELEASED
) {
1522 s
->pressed_keys
&= ~event
;
1524 s
->pressed_keys
|= event
;
1528 s
->kbd_extended
= 0;
1531 static int musicpal_key_init(SysBusDevice
*sbd
)
1533 DeviceState
*dev
= DEVICE(sbd
);
1534 musicpal_key_state
*s
= MUSICPAL_KEY(dev
);
1536 memory_region_init(&s
->iomem
, OBJECT(s
), "dummy", 0);
1537 sysbus_init_mmio(sbd
, &s
->iomem
);
1539 s
->kbd_extended
= 0;
1540 s
->pressed_keys
= 0;
1542 qdev_init_gpio_out(dev
, s
->out
, ARRAY_SIZE(s
->out
));
1544 qemu_add_kbd_event_handler(musicpal_key_event
, s
);
1549 static const VMStateDescription musicpal_key_vmsd
= {
1550 .name
= "musicpal_key",
1552 .minimum_version_id
= 1,
1553 .minimum_version_id_old
= 1,
1554 .fields
= (VMStateField
[]) {
1555 VMSTATE_UINT32(kbd_extended
, musicpal_key_state
),
1556 VMSTATE_UINT32(pressed_keys
, musicpal_key_state
),
1557 VMSTATE_END_OF_LIST()
1561 static void musicpal_key_class_init(ObjectClass
*klass
, void *data
)
1563 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1564 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1566 k
->init
= musicpal_key_init
;
1567 dc
->vmsd
= &musicpal_key_vmsd
;
1570 static const TypeInfo musicpal_key_info
= {
1571 .name
= TYPE_MUSICPAL_KEY
,
1572 .parent
= TYPE_SYS_BUS_DEVICE
,
1573 .instance_size
= sizeof(musicpal_key_state
),
1574 .class_init
= musicpal_key_class_init
,
1577 static struct arm_boot_info musicpal_binfo
= {
1578 .loader_start
= 0x0,
1582 static void musicpal_init(QEMUMachineInitArgs
*args
)
1584 const char *cpu_model
= args
->cpu_model
;
1585 const char *kernel_filename
= args
->kernel_filename
;
1586 const char *kernel_cmdline
= args
->kernel_cmdline
;
1587 const char *initrd_filename
= args
->initrd_filename
;
1591 DeviceState
*i2c_dev
;
1592 DeviceState
*lcd_dev
;
1593 DeviceState
*key_dev
;
1594 DeviceState
*wm8750_dev
;
1598 unsigned long flash_size
;
1600 MemoryRegion
*address_space_mem
= get_system_memory();
1601 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1602 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
1605 cpu_model
= "arm926";
1607 cpu
= cpu_arm_init(cpu_model
);
1609 fprintf(stderr
, "Unable to find CPU definition\n");
1613 /* For now we use a fixed - the original - RAM size */
1614 memory_region_init_ram(ram
, NULL
, "musicpal.ram", MP_RAM_DEFAULT_SIZE
);
1615 vmstate_register_ram_global(ram
);
1616 memory_region_add_subregion(address_space_mem
, 0, ram
);
1618 memory_region_init_ram(sram
, NULL
, "musicpal.sram", MP_SRAM_SIZE
);
1619 vmstate_register_ram_global(sram
);
1620 memory_region_add_subregion(address_space_mem
, MP_SRAM_BASE
, sram
);
1622 dev
= sysbus_create_simple(TYPE_MV88W8618_PIC
, MP_PIC_BASE
,
1623 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
));
1624 for (i
= 0; i
< 32; i
++) {
1625 pic
[i
] = qdev_get_gpio_in(dev
, i
);
1627 sysbus_create_varargs(TYPE_MV88W8618_PIT
, MP_PIT_BASE
, pic
[MP_TIMER1_IRQ
],
1628 pic
[MP_TIMER2_IRQ
], pic
[MP_TIMER3_IRQ
],
1629 pic
[MP_TIMER4_IRQ
], NULL
);
1631 if (serial_hds
[0]) {
1632 serial_mm_init(address_space_mem
, MP_UART1_BASE
, 2, pic
[MP_UART1_IRQ
],
1633 1825000, serial_hds
[0], DEVICE_NATIVE_ENDIAN
);
1635 if (serial_hds
[1]) {
1636 serial_mm_init(address_space_mem
, MP_UART2_BASE
, 2, pic
[MP_UART2_IRQ
],
1637 1825000, serial_hds
[1], DEVICE_NATIVE_ENDIAN
);
1640 /* Register flash */
1641 dinfo
= drive_get(IF_PFLASH
, 0, 0);
1643 flash_size
= bdrv_getlength(dinfo
->bdrv
);
1644 if (flash_size
!= 8*1024*1024 && flash_size
!= 16*1024*1024 &&
1645 flash_size
!= 32*1024*1024) {
1646 fprintf(stderr
, "Invalid flash image size\n");
1651 * The original U-Boot accesses the flash at 0xFE000000 instead of
1652 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1653 * image is smaller than 32 MB.
1655 #ifdef TARGET_WORDS_BIGENDIAN
1656 pflash_cfi02_register(0x100000000ULL
-MP_FLASH_SIZE_MAX
, NULL
,
1657 "musicpal.flash", flash_size
,
1658 dinfo
->bdrv
, 0x10000,
1659 (flash_size
+ 0xffff) >> 16,
1660 MP_FLASH_SIZE_MAX
/ flash_size
,
1661 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1664 pflash_cfi02_register(0x100000000ULL
-MP_FLASH_SIZE_MAX
, NULL
,
1665 "musicpal.flash", flash_size
,
1666 dinfo
->bdrv
, 0x10000,
1667 (flash_size
+ 0xffff) >> 16,
1668 MP_FLASH_SIZE_MAX
/ flash_size
,
1669 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1674 sysbus_create_simple(TYPE_MV88W8618_FLASHCFG
, MP_FLASHCFG_BASE
, NULL
);
1676 qemu_check_nic_model(&nd_table
[0], "mv88w8618");
1677 dev
= qdev_create(NULL
, TYPE_MV88W8618_ETH
);
1678 qdev_set_nic_properties(dev
, &nd_table
[0]);
1679 qdev_init_nofail(dev
);
1680 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, MP_ETH_BASE
);
1681 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[MP_ETH_IRQ
]);
1683 sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE
, NULL
);
1685 sysbus_create_simple(TYPE_MUSICPAL_MISC
, MP_MISC_BASE
, NULL
);
1687 dev
= sysbus_create_simple(TYPE_MUSICPAL_GPIO
, MP_GPIO_BASE
,
1689 i2c_dev
= sysbus_create_simple("gpio_i2c", -1, NULL
);
1690 i2c
= (I2CBus
*)qdev_get_child_bus(i2c_dev
, "i2c");
1692 lcd_dev
= sysbus_create_simple(TYPE_MUSICPAL_LCD
, MP_LCD_BASE
, NULL
);
1693 key_dev
= sysbus_create_simple(TYPE_MUSICPAL_KEY
, -1, NULL
);
1696 qdev_connect_gpio_out(i2c_dev
, 0,
1697 qdev_get_gpio_in(dev
, MP_GPIO_I2C_DATA_BIT
));
1699 qdev_connect_gpio_out(dev
, 3, qdev_get_gpio_in(i2c_dev
, 0));
1701 qdev_connect_gpio_out(dev
, 4, qdev_get_gpio_in(i2c_dev
, 1));
1703 for (i
= 0; i
< 3; i
++) {
1704 qdev_connect_gpio_out(dev
, i
, qdev_get_gpio_in(lcd_dev
, i
));
1706 for (i
= 0; i
< 4; i
++) {
1707 qdev_connect_gpio_out(key_dev
, i
, qdev_get_gpio_in(dev
, i
+ 8));
1709 for (i
= 4; i
< 8; i
++) {
1710 qdev_connect_gpio_out(key_dev
, i
, qdev_get_gpio_in(dev
, i
+ 15));
1713 wm8750_dev
= i2c_create_slave(i2c
, "wm8750", MP_WM_ADDR
);
1714 dev
= qdev_create(NULL
, "mv88w8618_audio");
1715 s
= SYS_BUS_DEVICE(dev
);
1716 qdev_prop_set_ptr(dev
, "wm8750", wm8750_dev
);
1717 qdev_init_nofail(dev
);
1718 sysbus_mmio_map(s
, 0, MP_AUDIO_BASE
);
1719 sysbus_connect_irq(s
, 0, pic
[MP_AUDIO_IRQ
]);
1721 musicpal_binfo
.ram_size
= MP_RAM_DEFAULT_SIZE
;
1722 musicpal_binfo
.kernel_filename
= kernel_filename
;
1723 musicpal_binfo
.kernel_cmdline
= kernel_cmdline
;
1724 musicpal_binfo
.initrd_filename
= initrd_filename
;
1725 arm_load_kernel(cpu
, &musicpal_binfo
);
1728 static QEMUMachine musicpal_machine
= {
1730 .desc
= "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1731 .init
= musicpal_init
,
1734 static void musicpal_machine_init(void)
1736 qemu_register_machine(&musicpal_machine
);
1739 machine_init(musicpal_machine_init
);
1741 static void mv88w8618_wlan_class_init(ObjectClass
*klass
, void *data
)
1743 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
1745 sdc
->init
= mv88w8618_wlan_init
;
1748 static const TypeInfo mv88w8618_wlan_info
= {
1749 .name
= "mv88w8618_wlan",
1750 .parent
= TYPE_SYS_BUS_DEVICE
,
1751 .instance_size
= sizeof(SysBusDevice
),
1752 .class_init
= mv88w8618_wlan_class_init
,
1755 static void musicpal_register_types(void)
1757 type_register_static(&mv88w8618_pic_info
);
1758 type_register_static(&mv88w8618_pit_info
);
1759 type_register_static(&mv88w8618_flashcfg_info
);
1760 type_register_static(&mv88w8618_eth_info
);
1761 type_register_static(&mv88w8618_wlan_info
);
1762 type_register_static(&musicpal_lcd_info
);
1763 type_register_static(&musicpal_gpio_info
);
1764 type_register_static(&musicpal_key_info
);
1765 type_register_static(&musicpal_misc_info
);
1768 type_init(musicpal_register_types
)