hw/arm/npcm7xx_boards.c

   1 /*
   2  * Machine definitions for boards featuring an NPCM7xx SoC.
   3  *
   4  * Copyright 2020 Google LLC
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  * for more details.
  15  */
  16
  17 #include "qemu/osdep.h"
  18
  19 #include "hw/arm/npcm7xx.h"
  20 #include "hw/core/cpu.h"
  21 #include "hw/i2c/smbus_eeprom.h"
  22 #include "hw/loader.h"
  23 #include "hw/qdev-core.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/error.h"
  26 #include "qemu-common.h"
  27 #include "qemu/datadir.h"
  28 #include "qemu/units.h"
  29
  30 #define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
  31 #define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
  32
  33 static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
  34
  35 static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc)
  36 {
  37     const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom;
  38     g_autofree char *filename = NULL;
  39     int ret;
  40
  41     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
  42     if (!filename) {
  43         error_report("Could not find ROM image '%s'", bios_name);
  44         if (!machine->kernel_filename) {
  45             /* We can't boot without a bootrom or a kernel image. */
  46             exit(1);
  47         }
  48         return;
  49     }
  50     ret = load_image_mr(filename, &soc->irom);
  51     if (ret < 0) {
  52         error_report("Failed to load ROM image '%s'", filename);
  53         exit(1);
  54     }
  55 }
  56
  57 static void npcm7xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no,
  58                                   const char *flash_type, DriveInfo *dinfo)
  59 {
  60     DeviceState *flash;
  61     qemu_irq flash_cs;
  62
  63     flash = qdev_new(flash_type);
  64     if (dinfo) {
  65         qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo));
  66     }
  67     qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);
  68
  69     flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
  70     qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs);
  71 }
  72
  73 static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram)
  74 {
  75     memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram);
  76
  77     object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram),
  78                              &error_abort);
  79 }
  80
  81 static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
  82                                         uint32_t hw_straps)
  83 {
  84     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
  85     MachineClass *mc = MACHINE_CLASS(nmc);
  86     Object *obj;
  87
  88     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
  89         error_report("This board can only be used with %s",
  90                      mc->default_cpu_type);
  91         exit(1);
  92     }
  93
  94     obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
  95                                 &error_abort, NULL);
  96     object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);
  97
  98     return NPCM7XX(obj);
  99 }
 100
 101 static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num)
 102 {
 103     g_assert(num < ARRAY_SIZE(soc->smbus));
 104     return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
 105 }
 106
 107 static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr,
 108                               uint32_t rsize)
 109 {
 110     I2CBus *i2c_bus = npcm7xx_i2c_get_bus(soc, bus);
 111     I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
 112     DeviceState *dev = DEVICE(i2c_dev);
 113
 114     qdev_prop_set_uint32(dev, "rom-size", rsize);
 115     i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort);
 116 }
 117
 118 static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine,
 119                                       NPCM7xxState *soc, const int *fan_counts)
 120 {
 121     SplitIRQ *splitters = machine->fan_splitter;
 122
 123     /*
 124      * PWM 0~3 belong to module 0 output 0~3.
 125      * PWM 4~7 belong to module 1 output 0~3.
 126      */
 127     for (int i = 0; i < NPCM7XX_NR_PWM_MODULES; ++i) {
 128         for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) {
 129             int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j;
 130             DeviceState *splitter;
 131
 132             if (fan_counts[splitter_no] < 1) {
 133                 continue;
 134             }
 135             object_initialize_child(OBJECT(machine), "fan-splitter[*]",
 136                                     &splitters[splitter_no], TYPE_SPLIT_IRQ);
 137             splitter = DEVICE(&splitters[splitter_no]);
 138             qdev_prop_set_uint16(splitter, "num-lines",
 139                                  fan_counts[splitter_no]);
 140             qdev_realize(splitter, NULL, &error_abort);
 141             qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out",
 142                                         j, qdev_get_gpio_in(splitter, 0));
 143         }
 144     }
 145 }
 146
 147 static void npcm7xx_connect_pwm_fan(NPCM7xxState *soc, SplitIRQ *splitter,
 148                                     int fan_no, int output_no)
 149 {
 150     DeviceState *fan;
 151     int fan_input;
 152     qemu_irq fan_duty_gpio;
 153
 154     g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT);
 155     /*
 156      * Fan 0~1 belong to module 0 input 0~1.
 157      * Fan 2~3 belong to module 1 input 0~1.
 158      * ...
 159      * Fan 14~15 belong to module 7 input 0~1.
 160      * Fan 16~17 belong to module 0 input 2~3.
 161      * Fan 18~19 belong to module 1 input 2~3.
 162      */
 163     if (fan_no < 16) {
 164         fan = DEVICE(&soc->mft[fan_no / 2]);
 165         fan_input = fan_no % 2;
 166     } else {
 167         fan = DEVICE(&soc->mft[(fan_no - 16) / 2]);
 168         fan_input = fan_no % 2 + 2;
 169     }
 170
 171     /* Connect the Fan to PWM module */
 172     fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input);
 173     qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio);
 174 }
 175
 176 static void npcm750_evb_i2c_init(NPCM7xxState *soc)
 177 {
 178     /* lm75 temperature sensor on SVB, tmp105 is compatible */
 179     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 0), "tmp105", 0x48);
 180     /* lm75 temperature sensor on EB, tmp105 is compatible */
 181     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48);
 182     /* tmp100 temperature sensor on EB, tmp105 is compatible */
 183     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48);
 184     /* tmp100 temperature sensor on SVB, tmp105 is compatible */
 185     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48);
 186 }
 187
 188 static void npcm750_evb_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
 189 {
 190     SplitIRQ *splitter = machine->fan_splitter;
 191     static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2};
 192
 193     npcm7xx_init_pwm_splitter(machine, soc, fan_counts);
 194     npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
 195     npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
 196     npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
 197     npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
 198     npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
 199     npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
 200     npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0);
 201     npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1);
 202     npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0);
 203     npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1);
 204     npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0);
 205     npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1);
 206     npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0);
 207     npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1);
 208     npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0);
 209     npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1);
 210 }
 211
 212 static void quanta_gsj_i2c_init(NPCM7xxState *soc)
 213 {
 214     /* GSJ machine have 4 max31725 temperature sensors, tmp105 is compatible. */
 215     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x5c);
 216     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x5c);
 217     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c);
 218     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c);
 219
 220     at24c_eeprom_init(soc, 9, 0x55, 8192);
 221     at24c_eeprom_init(soc, 10, 0x55, 8192);
 222
 223     /* TODO: Add additional i2c devices. */
 224 }
 225
 226 static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
 227 {
 228     SplitIRQ *splitter = machine->fan_splitter;
 229     static const int fan_counts[] = {2, 2, 2, 0, 0, 0, 0, 0};
 230
 231     npcm7xx_init_pwm_splitter(machine, soc, fan_counts);
 232     npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
 233     npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
 234     npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
 235     npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
 236     npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
 237     npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
 238 }
 239
 240 static void npcm750_evb_init(MachineState *machine)
 241 {
 242     NPCM7xxState *soc;
 243
 244     soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS);
 245     npcm7xx_connect_dram(soc, machine->ram);
 246     qdev_realize(DEVICE(soc), NULL, &error_fatal);
 247
 248     npcm7xx_load_bootrom(machine, soc);
 249     npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
 250     npcm750_evb_i2c_init(soc);
 251     npcm750_evb_fan_init(NPCM7XX_MACHINE(machine), soc);
 252     npcm7xx_load_kernel(machine, soc);
 253 }
 254
 255 static void quanta_gsj_init(MachineState *machine)
 256 {
 257     NPCM7xxState *soc;
 258
 259     soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS);
 260     npcm7xx_connect_dram(soc, machine->ram);
 261     qdev_realize(DEVICE(soc), NULL, &error_fatal);
 262
 263     npcm7xx_load_bootrom(machine, soc);
 264     npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e",
 265                           drive_get(IF_MTD, 0, 0));
 266     quanta_gsj_i2c_init(soc);
 267     quanta_gsj_fan_init(NPCM7XX_MACHINE(machine), soc);
 268     npcm7xx_load_kernel(machine, soc);
 269 }
 270
 271 static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
 272 {
 273     NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));
 274     MachineClass *mc = MACHINE_CLASS(nmc);
 275
 276     nmc->soc_type = type;
 277     mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus;
 278 }
 279
 280 static void npcm7xx_machine_class_init(ObjectClass *oc, void *data)
 281 {
 282     MachineClass *mc = MACHINE_CLASS(oc);
 283
 284     mc->no_floppy = 1;
 285     mc->no_cdrom = 1;
 286     mc->no_parallel = 1;
 287     mc->default_ram_id = "ram";
 288     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 289 }
 290
 291 /*
 292  * Schematics:
 293  * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf
 294  */
 295 static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data)
 296 {
 297     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
 298     MachineClass *mc = MACHINE_CLASS(oc);
 299
 300     npcm7xx_set_soc_type(nmc, TYPE_NPCM750);
 301
 302     mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex A9)";
 303     mc->init = npcm750_evb_init;
 304     mc->default_ram_size = 512 * MiB;
 305 };
 306
 307 static void gsj_machine_class_init(ObjectClass *oc, void *data)
 308 {
 309     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
 310     MachineClass *mc = MACHINE_CLASS(oc);
 311
 312     npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
 313
 314     mc->desc = "Quanta GSJ (Cortex A9)";
 315     mc->init = quanta_gsj_init;
 316     mc->default_ram_size = 512 * MiB;
 317 };
 318
 319 static const TypeInfo npcm7xx_machine_types[] = {
 320     {
 321         .name           = TYPE_NPCM7XX_MACHINE,
 322         .parent         = TYPE_MACHINE,
 323         .instance_size  = sizeof(NPCM7xxMachine),
 324         .class_size     = sizeof(NPCM7xxMachineClass),
 325         .class_init     = npcm7xx_machine_class_init,
 326         .abstract       = true,
 327     }, {
 328         .name           = MACHINE_TYPE_NAME("npcm750-evb"),
 329         .parent         = TYPE_NPCM7XX_MACHINE,
 330         .class_init     = npcm750_evb_machine_class_init,
 331     }, {
 332         .name           = MACHINE_TYPE_NAME("quanta-gsj"),
 333         .parent         = TYPE_NPCM7XX_MACHINE,
 334         .class_init     = gsj_machine_class_init,
 335     },
 336 };
 337
 338 DEFINE_TYPES(npcm7xx_machine_types)