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hw: Convert from BlockDriverState to BlockBackend, mostly
[mirror_qemu.git] / hw / arm / omap2.c
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "sysemu/block-backend.h"
22 #include "sysemu/blockdev.h"
23 #include "hw/hw.h"
24 #include "hw/arm/arm.h"
25 #include "hw/arm/omap.h"
26 #include "sysemu/sysemu.h"
27 #include "qemu/timer.h"
28 #include "sysemu/char.h"
29 #include "hw/block/flash.h"
30 #include "hw/arm/soc_dma.h"
31 #include "hw/sysbus.h"
32 #include "audio/audio.h"
33
34 /* Enhanced Audio Controller (CODEC only) */
35 struct omap_eac_s {
36 qemu_irq irq;
37 MemoryRegion iomem;
38
39 uint16_t sysconfig;
40 uint8_t config[4];
41 uint8_t control;
42 uint8_t address;
43 uint16_t data;
44 uint8_t vtol;
45 uint8_t vtsl;
46 uint16_t mixer;
47 uint16_t gain[4];
48 uint8_t att;
49 uint16_t max[7];
50
51 struct {
52 qemu_irq txdrq;
53 qemu_irq rxdrq;
54 uint32_t (*txrx)(void *opaque, uint32_t, int);
55 void *opaque;
56
57 #define EAC_BUF_LEN 1024
58 uint32_t rxbuf[EAC_BUF_LEN];
59 int rxoff;
60 int rxlen;
61 int rxavail;
62 uint32_t txbuf[EAC_BUF_LEN];
63 int txlen;
64 int txavail;
65
66 int enable;
67 int rate;
68
69 uint16_t config[4];
70
71 /* These need to be moved to the actual codec */
72 QEMUSoundCard card;
73 SWVoiceIn *in_voice;
74 SWVoiceOut *out_voice;
75 int hw_enable;
76 } codec;
77
78 struct {
79 uint8_t control;
80 uint16_t config;
81 } modem, bt;
82 };
83
84 static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
85 {
86 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
87 }
88
89 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
90 {
91 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
92 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
93 }
94
95 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
96 {
97 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
98 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
99 }
100
101 static inline void omap_eac_in_refill(struct omap_eac_s *s)
102 {
103 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
104 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
105 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
106 int recv = 1;
107 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
108
109 left -= leftwrap;
110 start = 0;
111 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
112 leftwrap)) > 0) { /* Be defensive */
113 start += recv;
114 leftwrap -= recv;
115 }
116 if (recv <= 0)
117 s->codec.rxavail = 0;
118 else
119 s->codec.rxavail -= start >> 2;
120 s->codec.rxlen += start >> 2;
121
122 if (recv > 0 && left > 0) {
123 start = 0;
124 while (left && (recv = AUD_read(s->codec.in_voice,
125 (uint8_t *) s->codec.rxbuf + start,
126 left)) > 0) { /* Be defensive */
127 start += recv;
128 left -= recv;
129 }
130 if (recv <= 0)
131 s->codec.rxavail = 0;
132 else
133 s->codec.rxavail -= start >> 2;
134 s->codec.rxlen += start >> 2;
135 }
136 }
137
138 static inline void omap_eac_out_empty(struct omap_eac_s *s)
139 {
140 int left = s->codec.txlen << 2;
141 int start = 0;
142 int sent = 1;
143
144 while (left && (sent = AUD_write(s->codec.out_voice,
145 (uint8_t *) s->codec.txbuf + start,
146 left)) > 0) { /* Be defensive */
147 start += sent;
148 left -= sent;
149 }
150
151 if (!sent) {
152 s->codec.txavail = 0;
153 omap_eac_out_dmarequest_update(s);
154 }
155
156 if (start)
157 s->codec.txlen = 0;
158 }
159
160 static void omap_eac_in_cb(void *opaque, int avail_b)
161 {
162 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
163
164 s->codec.rxavail = avail_b >> 2;
165 omap_eac_in_refill(s);
166 /* TODO: possibly discard current buffer if overrun */
167 omap_eac_in_dmarequest_update(s);
168 }
169
170 static void omap_eac_out_cb(void *opaque, int free_b)
171 {
172 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
173
174 s->codec.txavail = free_b >> 2;
175 if (s->codec.txlen)
176 omap_eac_out_empty(s);
177 else
178 omap_eac_out_dmarequest_update(s);
179 }
180
181 static void omap_eac_enable_update(struct omap_eac_s *s)
182 {
183 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
184 (s->codec.config[1] & 2) && /* AUDEN */
185 s->codec.hw_enable;
186 }
187
188 static const int omap_eac_fsint[4] = {
189 8000,
190 11025,
191 22050,
192 44100,
193 };
194
195 static const int omap_eac_fsint2[8] = {
196 8000,
197 11025,
198 22050,
199 44100,
200 48000,
201 0, 0, 0,
202 };
203
204 static const int omap_eac_fsint3[16] = {
205 8000,
206 11025,
207 16000,
208 22050,
209 24000,
210 32000,
211 44100,
212 48000,
213 0, 0, 0, 0, 0, 0, 0, 0,
214 };
215
216 static void omap_eac_rate_update(struct omap_eac_s *s)
217 {
218 int fsint[3];
219
220 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
221 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
222 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
223 if (fsint[2] < 0xf)
224 s->codec.rate = omap_eac_fsint3[fsint[2]];
225 else if (fsint[1] < 0x7)
226 s->codec.rate = omap_eac_fsint2[fsint[1]];
227 else
228 s->codec.rate = omap_eac_fsint[fsint[0]];
229 }
230
231 static void omap_eac_volume_update(struct omap_eac_s *s)
232 {
233 /* TODO */
234 }
235
236 static void omap_eac_format_update(struct omap_eac_s *s)
237 {
238 struct audsettings fmt;
239
240 /* The hardware buffers at most one sample */
241 if (s->codec.rxlen)
242 s->codec.rxlen = 1;
243
244 if (s->codec.in_voice) {
245 AUD_set_active_in(s->codec.in_voice, 0);
246 AUD_close_in(&s->codec.card, s->codec.in_voice);
247 s->codec.in_voice = NULL;
248 }
249 if (s->codec.out_voice) {
250 omap_eac_out_empty(s);
251 AUD_set_active_out(s->codec.out_voice, 0);
252 AUD_close_out(&s->codec.card, s->codec.out_voice);
253 s->codec.out_voice = NULL;
254 s->codec.txavail = 0;
255 }
256 /* Discard what couldn't be written */
257 s->codec.txlen = 0;
258
259 omap_eac_enable_update(s);
260 if (!s->codec.enable)
261 return;
262
263 omap_eac_rate_update(s);
264 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
265 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
266 fmt.freq = s->codec.rate;
267 /* TODO: signedness possibly depends on the CODEC hardware - or
268 * does I2S specify it? */
269 /* All register writes are 16 bits so we we store 16-bit samples
270 * in the buffers regardless of AGCFR[B8_16] value. */
271 fmt.fmt = AUD_FMT_U16;
272
273 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
274 "eac.codec.in", s, omap_eac_in_cb, &fmt);
275 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
276 "eac.codec.out", s, omap_eac_out_cb, &fmt);
277
278 omap_eac_volume_update(s);
279
280 AUD_set_active_in(s->codec.in_voice, 1);
281 AUD_set_active_out(s->codec.out_voice, 1);
282 }
283
284 static void omap_eac_reset(struct omap_eac_s *s)
285 {
286 s->sysconfig = 0;
287 s->config[0] = 0x0c;
288 s->config[1] = 0x09;
289 s->config[2] = 0xab;
290 s->config[3] = 0x03;
291 s->control = 0x00;
292 s->address = 0x00;
293 s->data = 0x0000;
294 s->vtol = 0x00;
295 s->vtsl = 0x00;
296 s->mixer = 0x0000;
297 s->gain[0] = 0xe7e7;
298 s->gain[1] = 0x6767;
299 s->gain[2] = 0x6767;
300 s->gain[3] = 0x6767;
301 s->att = 0xce;
302 s->max[0] = 0;
303 s->max[1] = 0;
304 s->max[2] = 0;
305 s->max[3] = 0;
306 s->max[4] = 0;
307 s->max[5] = 0;
308 s->max[6] = 0;
309
310 s->modem.control = 0x00;
311 s->modem.config = 0x0000;
312 s->bt.control = 0x00;
313 s->bt.config = 0x0000;
314 s->codec.config[0] = 0x0649;
315 s->codec.config[1] = 0x0000;
316 s->codec.config[2] = 0x0007;
317 s->codec.config[3] = 0x1ffc;
318 s->codec.rxoff = 0;
319 s->codec.rxlen = 0;
320 s->codec.txlen = 0;
321 s->codec.rxavail = 0;
322 s->codec.txavail = 0;
323
324 omap_eac_format_update(s);
325 omap_eac_interrupt_update(s);
326 }
327
328 static uint64_t omap_eac_read(void *opaque, hwaddr addr,
329 unsigned size)
330 {
331 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
332 uint32_t ret;
333
334 if (size != 2) {
335 return omap_badwidth_read16(opaque, addr);
336 }
337
338 switch (addr) {
339 case 0x000: /* CPCFR1 */
340 return s->config[0];
341 case 0x004: /* CPCFR2 */
342 return s->config[1];
343 case 0x008: /* CPCFR3 */
344 return s->config[2];
345 case 0x00c: /* CPCFR4 */
346 return s->config[3];
347
348 case 0x010: /* CPTCTL */
349 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
350 ((s->codec.txlen < s->codec.txavail) << 5);
351
352 case 0x014: /* CPTTADR */
353 return s->address;
354 case 0x018: /* CPTDATL */
355 return s->data & 0xff;
356 case 0x01c: /* CPTDATH */
357 return s->data >> 8;
358 case 0x020: /* CPTVSLL */
359 return s->vtol;
360 case 0x024: /* CPTVSLH */
361 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
362 case 0x040: /* MPCTR */
363 return s->modem.control;
364 case 0x044: /* MPMCCFR */
365 return s->modem.config;
366 case 0x060: /* BPCTR */
367 return s->bt.control;
368 case 0x064: /* BPMCCFR */
369 return s->bt.config;
370 case 0x080: /* AMSCFR */
371 return s->mixer;
372 case 0x084: /* AMVCTR */
373 return s->gain[0];
374 case 0x088: /* AM1VCTR */
375 return s->gain[1];
376 case 0x08c: /* AM2VCTR */
377 return s->gain[2];
378 case 0x090: /* AM3VCTR */
379 return s->gain[3];
380 case 0x094: /* ASTCTR */
381 return s->att;
382 case 0x098: /* APD1LCR */
383 return s->max[0];
384 case 0x09c: /* APD1RCR */
385 return s->max[1];
386 case 0x0a0: /* APD2LCR */
387 return s->max[2];
388 case 0x0a4: /* APD2RCR */
389 return s->max[3];
390 case 0x0a8: /* APD3LCR */
391 return s->max[4];
392 case 0x0ac: /* APD3RCR */
393 return s->max[5];
394 case 0x0b0: /* APD4R */
395 return s->max[6];
396 case 0x0b4: /* ADWR */
397 /* This should be write-only? Docs list it as read-only. */
398 return 0x0000;
399 case 0x0b8: /* ADRDR */
400 if (likely(s->codec.rxlen > 1)) {
401 ret = s->codec.rxbuf[s->codec.rxoff ++];
402 s->codec.rxlen --;
403 s->codec.rxoff &= EAC_BUF_LEN - 1;
404 return ret;
405 } else if (s->codec.rxlen) {
406 ret = s->codec.rxbuf[s->codec.rxoff ++];
407 s->codec.rxlen --;
408 s->codec.rxoff &= EAC_BUF_LEN - 1;
409 if (s->codec.rxavail)
410 omap_eac_in_refill(s);
411 omap_eac_in_dmarequest_update(s);
412 return ret;
413 }
414 return 0x0000;
415 case 0x0bc: /* AGCFR */
416 return s->codec.config[0];
417 case 0x0c0: /* AGCTR */
418 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
419 case 0x0c4: /* AGCFR2 */
420 return s->codec.config[2];
421 case 0x0c8: /* AGCFR3 */
422 return s->codec.config[3];
423 case 0x0cc: /* MBPDMACTR */
424 case 0x0d0: /* MPDDMARR */
425 case 0x0d8: /* MPUDMARR */
426 case 0x0e4: /* BPDDMARR */
427 case 0x0ec: /* BPUDMARR */
428 return 0x0000;
429
430 case 0x100: /* VERSION_NUMBER */
431 return 0x0010;
432
433 case 0x104: /* SYSCONFIG */
434 return s->sysconfig;
435
436 case 0x108: /* SYSSTATUS */
437 return 1 | 0xe; /* RESETDONE | stuff */
438 }
439
440 OMAP_BAD_REG(addr);
441 return 0;
442 }
443
444 static void omap_eac_write(void *opaque, hwaddr addr,
445 uint64_t value, unsigned size)
446 {
447 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
448
449 if (size != 2) {
450 return omap_badwidth_write16(opaque, addr, value);
451 }
452
453 switch (addr) {
454 case 0x098: /* APD1LCR */
455 case 0x09c: /* APD1RCR */
456 case 0x0a0: /* APD2LCR */
457 case 0x0a4: /* APD2RCR */
458 case 0x0a8: /* APD3LCR */
459 case 0x0ac: /* APD3RCR */
460 case 0x0b0: /* APD4R */
461 case 0x0b8: /* ADRDR */
462 case 0x0d0: /* MPDDMARR */
463 case 0x0d8: /* MPUDMARR */
464 case 0x0e4: /* BPDDMARR */
465 case 0x0ec: /* BPUDMARR */
466 case 0x100: /* VERSION_NUMBER */
467 case 0x108: /* SYSSTATUS */
468 OMAP_RO_REG(addr);
469 return;
470
471 case 0x000: /* CPCFR1 */
472 s->config[0] = value & 0xff;
473 omap_eac_format_update(s);
474 break;
475 case 0x004: /* CPCFR2 */
476 s->config[1] = value & 0xff;
477 omap_eac_format_update(s);
478 break;
479 case 0x008: /* CPCFR3 */
480 s->config[2] = value & 0xff;
481 omap_eac_format_update(s);
482 break;
483 case 0x00c: /* CPCFR4 */
484 s->config[3] = value & 0xff;
485 omap_eac_format_update(s);
486 break;
487
488 case 0x010: /* CPTCTL */
489 /* Assuming TXF and TXE bits are read-only... */
490 s->control = value & 0x5f;
491 omap_eac_interrupt_update(s);
492 break;
493
494 case 0x014: /* CPTTADR */
495 s->address = value & 0xff;
496 break;
497 case 0x018: /* CPTDATL */
498 s->data &= 0xff00;
499 s->data |= value & 0xff;
500 break;
501 case 0x01c: /* CPTDATH */
502 s->data &= 0x00ff;
503 s->data |= value << 8;
504 break;
505 case 0x020: /* CPTVSLL */
506 s->vtol = value & 0xf8;
507 break;
508 case 0x024: /* CPTVSLH */
509 s->vtsl = value & 0x9f;
510 break;
511 case 0x040: /* MPCTR */
512 s->modem.control = value & 0x8f;
513 break;
514 case 0x044: /* MPMCCFR */
515 s->modem.config = value & 0x7fff;
516 break;
517 case 0x060: /* BPCTR */
518 s->bt.control = value & 0x8f;
519 break;
520 case 0x064: /* BPMCCFR */
521 s->bt.config = value & 0x7fff;
522 break;
523 case 0x080: /* AMSCFR */
524 s->mixer = value & 0x0fff;
525 break;
526 case 0x084: /* AMVCTR */
527 s->gain[0] = value & 0xffff;
528 break;
529 case 0x088: /* AM1VCTR */
530 s->gain[1] = value & 0xff7f;
531 break;
532 case 0x08c: /* AM2VCTR */
533 s->gain[2] = value & 0xff7f;
534 break;
535 case 0x090: /* AM3VCTR */
536 s->gain[3] = value & 0xff7f;
537 break;
538 case 0x094: /* ASTCTR */
539 s->att = value & 0xff;
540 break;
541
542 case 0x0b4: /* ADWR */
543 s->codec.txbuf[s->codec.txlen ++] = value;
544 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
545 s->codec.txlen == s->codec.txavail)) {
546 if (s->codec.txavail)
547 omap_eac_out_empty(s);
548 /* Discard what couldn't be written */
549 s->codec.txlen = 0;
550 }
551 break;
552
553 case 0x0bc: /* AGCFR */
554 s->codec.config[0] = value & 0x07ff;
555 omap_eac_format_update(s);
556 break;
557 case 0x0c0: /* AGCTR */
558 s->codec.config[1] = value & 0x780f;
559 omap_eac_format_update(s);
560 break;
561 case 0x0c4: /* AGCFR2 */
562 s->codec.config[2] = value & 0x003f;
563 omap_eac_format_update(s);
564 break;
565 case 0x0c8: /* AGCFR3 */
566 s->codec.config[3] = value & 0xffff;
567 omap_eac_format_update(s);
568 break;
569 case 0x0cc: /* MBPDMACTR */
570 case 0x0d4: /* MPDDMAWR */
571 case 0x0e0: /* MPUDMAWR */
572 case 0x0e8: /* BPDDMAWR */
573 case 0x0f0: /* BPUDMAWR */
574 break;
575
576 case 0x104: /* SYSCONFIG */
577 if (value & (1 << 1)) /* SOFTRESET */
578 omap_eac_reset(s);
579 s->sysconfig = value & 0x31d;
580 break;
581
582 default:
583 OMAP_BAD_REG(addr);
584 return;
585 }
586 }
587
588 static const MemoryRegionOps omap_eac_ops = {
589 .read = omap_eac_read,
590 .write = omap_eac_write,
591 .endianness = DEVICE_NATIVE_ENDIAN,
592 };
593
594 static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
595 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
596 {
597 struct omap_eac_s *s = (struct omap_eac_s *)
598 g_malloc0(sizeof(struct omap_eac_s));
599
600 s->irq = irq;
601 s->codec.rxdrq = *drq ++;
602 s->codec.txdrq = *drq;
603 omap_eac_reset(s);
604
605 AUD_register_card("OMAP EAC", &s->codec.card);
606
607 memory_region_init_io(&s->iomem, NULL, &omap_eac_ops, s, "omap.eac",
608 omap_l4_region_size(ta, 0));
609 omap_l4_attach(ta, 0, &s->iomem);
610
611 return s;
612 }
613
614 /* STI/XTI (emulation interface) console - reverse engineered only */
615 struct omap_sti_s {
616 qemu_irq irq;
617 MemoryRegion iomem;
618 MemoryRegion iomem_fifo;
619 CharDriverState *chr;
620
621 uint32_t sysconfig;
622 uint32_t systest;
623 uint32_t irqst;
624 uint32_t irqen;
625 uint32_t clkcontrol;
626 uint32_t serial_config;
627 };
628
629 #define STI_TRACE_CONSOLE_CHANNEL 239
630 #define STI_TRACE_CONTROL_CHANNEL 253
631
632 static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
633 {
634 qemu_set_irq(s->irq, s->irqst & s->irqen);
635 }
636
637 static void omap_sti_reset(struct omap_sti_s *s)
638 {
639 s->sysconfig = 0;
640 s->irqst = 0;
641 s->irqen = 0;
642 s->clkcontrol = 0;
643 s->serial_config = 0;
644
645 omap_sti_interrupt_update(s);
646 }
647
648 static uint64_t omap_sti_read(void *opaque, hwaddr addr,
649 unsigned size)
650 {
651 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
652
653 if (size != 4) {
654 return omap_badwidth_read32(opaque, addr);
655 }
656
657 switch (addr) {
658 case 0x00: /* STI_REVISION */
659 return 0x10;
660
661 case 0x10: /* STI_SYSCONFIG */
662 return s->sysconfig;
663
664 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
665 return 0x00;
666
667 case 0x18: /* STI_IRQSTATUS */
668 return s->irqst;
669
670 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
671 return s->irqen;
672
673 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
674 case 0x28: /* STI_RX_DR / XTI_RXDATA */
675 /* TODO */
676 return 0;
677
678 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
679 return s->clkcontrol;
680
681 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
682 return s->serial_config;
683 }
684
685 OMAP_BAD_REG(addr);
686 return 0;
687 }
688
689 static void omap_sti_write(void *opaque, hwaddr addr,
690 uint64_t value, unsigned size)
691 {
692 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
693
694 if (size != 4) {
695 return omap_badwidth_write32(opaque, addr, value);
696 }
697
698 switch (addr) {
699 case 0x00: /* STI_REVISION */
700 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
701 OMAP_RO_REG(addr);
702 return;
703
704 case 0x10: /* STI_SYSCONFIG */
705 if (value & (1 << 1)) /* SOFTRESET */
706 omap_sti_reset(s);
707 s->sysconfig = value & 0xfe;
708 break;
709
710 case 0x18: /* STI_IRQSTATUS */
711 s->irqst &= ~value;
712 omap_sti_interrupt_update(s);
713 break;
714
715 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
716 s->irqen = value & 0xffff;
717 omap_sti_interrupt_update(s);
718 break;
719
720 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
721 s->clkcontrol = value & 0xff;
722 break;
723
724 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
725 s->serial_config = value & 0xff;
726 break;
727
728 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
729 case 0x28: /* STI_RX_DR / XTI_RXDATA */
730 /* TODO */
731 return;
732
733 default:
734 OMAP_BAD_REG(addr);
735 return;
736 }
737 }
738
739 static const MemoryRegionOps omap_sti_ops = {
740 .read = omap_sti_read,
741 .write = omap_sti_write,
742 .endianness = DEVICE_NATIVE_ENDIAN,
743 };
744
745 static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
746 unsigned size)
747 {
748 OMAP_BAD_REG(addr);
749 return 0;
750 }
751
752 static void omap_sti_fifo_write(void *opaque, hwaddr addr,
753 uint64_t value, unsigned size)
754 {
755 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
756 int ch = addr >> 6;
757 uint8_t byte = value;
758
759 if (size != 1) {
760 return omap_badwidth_write8(opaque, addr, size);
761 }
762
763 if (ch == STI_TRACE_CONTROL_CHANNEL) {
764 /* Flush channel <i>value</i>. */
765 qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1);
766 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
767 if (value == 0xc0 || value == 0xc3) {
768 /* Open channel <i>ch</i>. */
769 } else if (value == 0x00)
770 qemu_chr_fe_write(s->chr, (const uint8_t *) "\n", 1);
771 else
772 qemu_chr_fe_write(s->chr, &byte, 1);
773 }
774 }
775
776 static const MemoryRegionOps omap_sti_fifo_ops = {
777 .read = omap_sti_fifo_read,
778 .write = omap_sti_fifo_write,
779 .endianness = DEVICE_NATIVE_ENDIAN,
780 };
781
782 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
783 MemoryRegion *sysmem,
784 hwaddr channel_base, qemu_irq irq, omap_clk clk,
785 CharDriverState *chr)
786 {
787 struct omap_sti_s *s = (struct omap_sti_s *)
788 g_malloc0(sizeof(struct omap_sti_s));
789
790 s->irq = irq;
791 omap_sti_reset(s);
792
793 s->chr = chr ?: qemu_chr_new("null", "null", NULL);
794
795 memory_region_init_io(&s->iomem, NULL, &omap_sti_ops, s, "omap.sti",
796 omap_l4_region_size(ta, 0));
797 omap_l4_attach(ta, 0, &s->iomem);
798
799 memory_region_init_io(&s->iomem_fifo, NULL, &omap_sti_fifo_ops, s,
800 "omap.sti.fifo", 0x10000);
801 memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo);
802
803 return s;
804 }
805
806 /* L4 Interconnect */
807 #define L4TA(n) (n)
808 #define L4TAO(n) ((n) + 39)
809
810 static const struct omap_l4_region_s omap_l4_region[125] = {
811 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
812 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
813 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
814 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
815 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
816 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
817 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
818 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
819 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
820 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
821 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
822 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
823 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
824 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
825 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
826 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
827 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
828 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
829 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
830 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
831 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
832 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
833 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
834 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
835 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
836 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
837 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
838 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
839 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
840 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
841 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
842 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
843 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
844 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
845 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
846 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
847 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
848 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
849 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
850 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
851 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
852 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
853 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
854 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
855 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
856 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
857 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
858 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
859 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
860 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
861 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
862 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
863 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
864 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
865 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
866 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
867 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
868 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
869 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
870 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
871 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
872 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
873 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
874 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
875 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
876 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
877 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
878 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
879 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
880 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
881 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
882 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
883 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
884 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
885 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
886 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
887 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
888 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
889 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
890 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
891 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
892 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
893 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
894 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
895 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
896 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
897 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
898 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
899 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
900 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
901 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
902 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
903 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
904 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
905 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
906 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
907 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
908 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
909 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
910 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
911 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
912 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
913 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
914 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
915 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
916 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
917 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
918 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
919 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
920 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
921 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
922 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
923 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
924 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
925 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
926 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
927 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
928 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
929 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
930 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
931 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
932 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
933 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
934 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
935 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
936 };
937
938 static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
939 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
940 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
941 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
942 { L4TAO(3), 7, 3, 2 }, /* PRCM */
943 { L4TA(1), 10, 2, 1 }, /* BCM */
944 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
945 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
946 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
947 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
948 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
949 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
950 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
951 { L4TA(12), 38, 2, 1 }, /* sDMA */
952 { L4TA(13), 40, 5, 4 }, /* SSI */
953 { L4TAO(4), 45, 2, 1 }, /* USB */
954 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
955 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
956 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
957 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
958 { L4TA(18), 55, 2, 1 }, /* XTI */
959 { L4TA(19), 57, 2, 1 }, /* UART1 */
960 { L4TA(20), 59, 2, 1 }, /* UART2 */
961 { L4TA(21), 61, 2, 1 }, /* UART3 */
962 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
963 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
964 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
965 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
966 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
967 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
968 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
969 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
970 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
971 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
972 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
973 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
974 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
975 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
976 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
977 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
978 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
979 { L4TA(32), 97, 2, 1 }, /* EAC */
980 { L4TA(33), 99, 2, 1 }, /* FAC */
981 { L4TA(34), 101, 2, 1 }, /* IPC */
982 { L4TA(35), 103, 2, 1 }, /* SPI1 */
983 { L4TA(36), 105, 2, 1 }, /* SPI2 */
984 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
985 { L4TAO(10), 109, 2, 1 },
986 { L4TAO(11), 111, 2, 1 }, /* RNG */
987 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
988 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
989 { L4TA(37), 117, 2, 1 }, /* AES */
990 { L4TA(38), 119, 2, 1 }, /* PKA */
991 { -1, 121, 2, 1 },
992 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
993 };
994
995 #define omap_l4ta(bus, cs) \
996 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs))
997 #define omap_l4tao(bus, cs) \
998 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs))
999
1000 /* Power, Reset, and Clock Management */
1001 struct omap_prcm_s {
1002 qemu_irq irq[3];
1003 struct omap_mpu_state_s *mpu;
1004 MemoryRegion iomem0;
1005 MemoryRegion iomem1;
1006
1007 uint32_t irqst[3];
1008 uint32_t irqen[3];
1009
1010 uint32_t sysconfig;
1011 uint32_t voltctrl;
1012 uint32_t scratch[20];
1013
1014 uint32_t clksrc[1];
1015 uint32_t clkout[1];
1016 uint32_t clkemul[1];
1017 uint32_t clkpol[1];
1018 uint32_t clksel[8];
1019 uint32_t clken[12];
1020 uint32_t clkctrl[4];
1021 uint32_t clkidle[7];
1022 uint32_t setuptime[2];
1023
1024 uint32_t wkup[3];
1025 uint32_t wken[3];
1026 uint32_t wkst[3];
1027 uint32_t rst[4];
1028 uint32_t rstctrl[1];
1029 uint32_t power[4];
1030 uint32_t rsttime_wkup;
1031
1032 uint32_t ev;
1033 uint32_t evtime[2];
1034
1035 int dpll_lock, apll_lock[2];
1036 };
1037
1038 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
1039 {
1040 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
1041 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
1042 }
1043
1044 static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
1045 unsigned size)
1046 {
1047 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1048 uint32_t ret;
1049
1050 if (size != 4) {
1051 return omap_badwidth_read32(opaque, addr);
1052 }
1053
1054 switch (addr) {
1055 case 0x000: /* PRCM_REVISION */
1056 return 0x10;
1057
1058 case 0x010: /* PRCM_SYSCONFIG */
1059 return s->sysconfig;
1060
1061 case 0x018: /* PRCM_IRQSTATUS_MPU */
1062 return s->irqst[0];
1063
1064 case 0x01c: /* PRCM_IRQENABLE_MPU */
1065 return s->irqen[0];
1066
1067 case 0x050: /* PRCM_VOLTCTRL */
1068 return s->voltctrl;
1069 case 0x054: /* PRCM_VOLTST */
1070 return s->voltctrl & 3;
1071
1072 case 0x060: /* PRCM_CLKSRC_CTRL */
1073 return s->clksrc[0];
1074 case 0x070: /* PRCM_CLKOUT_CTRL */
1075 return s->clkout[0];
1076 case 0x078: /* PRCM_CLKEMUL_CTRL */
1077 return s->clkemul[0];
1078 case 0x080: /* PRCM_CLKCFG_CTRL */
1079 case 0x084: /* PRCM_CLKCFG_STATUS */
1080 return 0;
1081
1082 case 0x090: /* PRCM_VOLTSETUP */
1083 return s->setuptime[0];
1084
1085 case 0x094: /* PRCM_CLKSSETUP */
1086 return s->setuptime[1];
1087
1088 case 0x098: /* PRCM_POLCTRL */
1089 return s->clkpol[0];
1090
1091 case 0x0b0: /* GENERAL_PURPOSE1 */
1092 case 0x0b4: /* GENERAL_PURPOSE2 */
1093 case 0x0b8: /* GENERAL_PURPOSE3 */
1094 case 0x0bc: /* GENERAL_PURPOSE4 */
1095 case 0x0c0: /* GENERAL_PURPOSE5 */
1096 case 0x0c4: /* GENERAL_PURPOSE6 */
1097 case 0x0c8: /* GENERAL_PURPOSE7 */
1098 case 0x0cc: /* GENERAL_PURPOSE8 */
1099 case 0x0d0: /* GENERAL_PURPOSE9 */
1100 case 0x0d4: /* GENERAL_PURPOSE10 */
1101 case 0x0d8: /* GENERAL_PURPOSE11 */
1102 case 0x0dc: /* GENERAL_PURPOSE12 */
1103 case 0x0e0: /* GENERAL_PURPOSE13 */
1104 case 0x0e4: /* GENERAL_PURPOSE14 */
1105 case 0x0e8: /* GENERAL_PURPOSE15 */
1106 case 0x0ec: /* GENERAL_PURPOSE16 */
1107 case 0x0f0: /* GENERAL_PURPOSE17 */
1108 case 0x0f4: /* GENERAL_PURPOSE18 */
1109 case 0x0f8: /* GENERAL_PURPOSE19 */
1110 case 0x0fc: /* GENERAL_PURPOSE20 */
1111 return s->scratch[(addr - 0xb0) >> 2];
1112
1113 case 0x140: /* CM_CLKSEL_MPU */
1114 return s->clksel[0];
1115 case 0x148: /* CM_CLKSTCTRL_MPU */
1116 return s->clkctrl[0];
1117
1118 case 0x158: /* RM_RSTST_MPU */
1119 return s->rst[0];
1120 case 0x1c8: /* PM_WKDEP_MPU */
1121 return s->wkup[0];
1122 case 0x1d4: /* PM_EVGENCTRL_MPU */
1123 return s->ev;
1124 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1125 return s->evtime[0];
1126 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1127 return s->evtime[1];
1128 case 0x1e0: /* PM_PWSTCTRL_MPU */
1129 return s->power[0];
1130 case 0x1e4: /* PM_PWSTST_MPU */
1131 return 0;
1132
1133 case 0x200: /* CM_FCLKEN1_CORE */
1134 return s->clken[0];
1135 case 0x204: /* CM_FCLKEN2_CORE */
1136 return s->clken[1];
1137 case 0x210: /* CM_ICLKEN1_CORE */
1138 return s->clken[2];
1139 case 0x214: /* CM_ICLKEN2_CORE */
1140 return s->clken[3];
1141 case 0x21c: /* CM_ICLKEN4_CORE */
1142 return s->clken[4];
1143
1144 case 0x220: /* CM_IDLEST1_CORE */
1145 /* TODO: check the actual iclk status */
1146 return 0x7ffffff9;
1147 case 0x224: /* CM_IDLEST2_CORE */
1148 /* TODO: check the actual iclk status */
1149 return 0x00000007;
1150 case 0x22c: /* CM_IDLEST4_CORE */
1151 /* TODO: check the actual iclk status */
1152 return 0x0000001f;
1153
1154 case 0x230: /* CM_AUTOIDLE1_CORE */
1155 return s->clkidle[0];
1156 case 0x234: /* CM_AUTOIDLE2_CORE */
1157 return s->clkidle[1];
1158 case 0x238: /* CM_AUTOIDLE3_CORE */
1159 return s->clkidle[2];
1160 case 0x23c: /* CM_AUTOIDLE4_CORE */
1161 return s->clkidle[3];
1162
1163 case 0x240: /* CM_CLKSEL1_CORE */
1164 return s->clksel[1];
1165 case 0x244: /* CM_CLKSEL2_CORE */
1166 return s->clksel[2];
1167
1168 case 0x248: /* CM_CLKSTCTRL_CORE */
1169 return s->clkctrl[1];
1170
1171 case 0x2a0: /* PM_WKEN1_CORE */
1172 return s->wken[0];
1173 case 0x2a4: /* PM_WKEN2_CORE */
1174 return s->wken[1];
1175
1176 case 0x2b0: /* PM_WKST1_CORE */
1177 return s->wkst[0];
1178 case 0x2b4: /* PM_WKST2_CORE */
1179 return s->wkst[1];
1180 case 0x2c8: /* PM_WKDEP_CORE */
1181 return 0x1e;
1182
1183 case 0x2e0: /* PM_PWSTCTRL_CORE */
1184 return s->power[1];
1185 case 0x2e4: /* PM_PWSTST_CORE */
1186 return 0x000030 | (s->power[1] & 0xfc00);
1187
1188 case 0x300: /* CM_FCLKEN_GFX */
1189 return s->clken[5];
1190 case 0x310: /* CM_ICLKEN_GFX */
1191 return s->clken[6];
1192 case 0x320: /* CM_IDLEST_GFX */
1193 /* TODO: check the actual iclk status */
1194 return 0x00000001;
1195 case 0x340: /* CM_CLKSEL_GFX */
1196 return s->clksel[3];
1197 case 0x348: /* CM_CLKSTCTRL_GFX */
1198 return s->clkctrl[2];
1199 case 0x350: /* RM_RSTCTRL_GFX */
1200 return s->rstctrl[0];
1201 case 0x358: /* RM_RSTST_GFX */
1202 return s->rst[1];
1203 case 0x3c8: /* PM_WKDEP_GFX */
1204 return s->wkup[1];
1205
1206 case 0x3e0: /* PM_PWSTCTRL_GFX */
1207 return s->power[2];
1208 case 0x3e4: /* PM_PWSTST_GFX */
1209 return s->power[2] & 3;
1210
1211 case 0x400: /* CM_FCLKEN_WKUP */
1212 return s->clken[7];
1213 case 0x410: /* CM_ICLKEN_WKUP */
1214 return s->clken[8];
1215 case 0x420: /* CM_IDLEST_WKUP */
1216 /* TODO: check the actual iclk status */
1217 return 0x0000003f;
1218 case 0x430: /* CM_AUTOIDLE_WKUP */
1219 return s->clkidle[4];
1220 case 0x440: /* CM_CLKSEL_WKUP */
1221 return s->clksel[4];
1222 case 0x450: /* RM_RSTCTRL_WKUP */
1223 return 0;
1224 case 0x454: /* RM_RSTTIME_WKUP */
1225 return s->rsttime_wkup;
1226 case 0x458: /* RM_RSTST_WKUP */
1227 return s->rst[2];
1228 case 0x4a0: /* PM_WKEN_WKUP */
1229 return s->wken[2];
1230 case 0x4b0: /* PM_WKST_WKUP */
1231 return s->wkst[2];
1232
1233 case 0x500: /* CM_CLKEN_PLL */
1234 return s->clken[9];
1235 case 0x520: /* CM_IDLEST_CKGEN */
1236 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
1237 if (!(s->clksel[6] & 3))
1238 /* Core uses 32-kHz clock */
1239 ret |= 3 << 0;
1240 else if (!s->dpll_lock)
1241 /* DPLL not locked, core uses ref_clk */
1242 ret |= 1 << 0;
1243 else
1244 /* Core uses DPLL */
1245 ret |= 2 << 0;
1246 return ret;
1247 case 0x530: /* CM_AUTOIDLE_PLL */
1248 return s->clkidle[5];
1249 case 0x540: /* CM_CLKSEL1_PLL */
1250 return s->clksel[5];
1251 case 0x544: /* CM_CLKSEL2_PLL */
1252 return s->clksel[6];
1253
1254 case 0x800: /* CM_FCLKEN_DSP */
1255 return s->clken[10];
1256 case 0x810: /* CM_ICLKEN_DSP */
1257 return s->clken[11];
1258 case 0x820: /* CM_IDLEST_DSP */
1259 /* TODO: check the actual iclk status */
1260 return 0x00000103;
1261 case 0x830: /* CM_AUTOIDLE_DSP */
1262 return s->clkidle[6];
1263 case 0x840: /* CM_CLKSEL_DSP */
1264 return s->clksel[7];
1265 case 0x848: /* CM_CLKSTCTRL_DSP */
1266 return s->clkctrl[3];
1267 case 0x850: /* RM_RSTCTRL_DSP */
1268 return 0;
1269 case 0x858: /* RM_RSTST_DSP */
1270 return s->rst[3];
1271 case 0x8c8: /* PM_WKDEP_DSP */
1272 return s->wkup[2];
1273 case 0x8e0: /* PM_PWSTCTRL_DSP */
1274 return s->power[3];
1275 case 0x8e4: /* PM_PWSTST_DSP */
1276 return 0x008030 | (s->power[3] & 0x3003);
1277
1278 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1279 return s->irqst[1];
1280 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1281 return s->irqen[1];
1282
1283 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1284 return s->irqst[2];
1285 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1286 return s->irqen[2];
1287 }
1288
1289 OMAP_BAD_REG(addr);
1290 return 0;
1291 }
1292
1293 static void omap_prcm_apll_update(struct omap_prcm_s *s)
1294 {
1295 int mode[2];
1296
1297 mode[0] = (s->clken[9] >> 6) & 3;
1298 s->apll_lock[0] = (mode[0] == 3);
1299 mode[1] = (s->clken[9] >> 2) & 3;
1300 s->apll_lock[1] = (mode[1] == 3);
1301 /* TODO: update clocks */
1302
1303 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2)
1304 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
1305 __FUNCTION__);
1306 }
1307
1308 static void omap_prcm_dpll_update(struct omap_prcm_s *s)
1309 {
1310 omap_clk dpll = omap_findclk(s->mpu, "dpll");
1311 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
1312 omap_clk core = omap_findclk(s->mpu, "core_clk");
1313 int mode = (s->clken[9] >> 0) & 3;
1314 int mult, div;
1315
1316 mult = (s->clksel[5] >> 12) & 0x3ff;
1317 div = (s->clksel[5] >> 8) & 0xf;
1318 if (mult == 0 || mult == 1)
1319 mode = 1; /* Bypass */
1320
1321 s->dpll_lock = 0;
1322 switch (mode) {
1323 case 0:
1324 fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
1325 break;
1326 case 1: /* Low-power bypass mode (Default) */
1327 case 2: /* Fast-relock bypass mode */
1328 omap_clk_setrate(dpll, 1, 1);
1329 omap_clk_setrate(dpll_x2, 1, 1);
1330 break;
1331 case 3: /* Lock mode */
1332 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
1333
1334 omap_clk_setrate(dpll, div + 1, mult);
1335 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
1336 break;
1337 }
1338
1339 switch ((s->clksel[6] >> 0) & 3) {
1340 case 0:
1341 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
1342 break;
1343 case 1:
1344 omap_clk_reparent(core, dpll);
1345 break;
1346 case 2:
1347 /* Default */
1348 omap_clk_reparent(core, dpll_x2);
1349 break;
1350 case 3:
1351 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
1352 break;
1353 }
1354 }
1355
1356 static void omap_prcm_write(void *opaque, hwaddr addr,
1357 uint64_t value, unsigned size)
1358 {
1359 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1360
1361 if (size != 4) {
1362 return omap_badwidth_write32(opaque, addr, value);
1363 }
1364
1365 switch (addr) {
1366 case 0x000: /* PRCM_REVISION */
1367 case 0x054: /* PRCM_VOLTST */
1368 case 0x084: /* PRCM_CLKCFG_STATUS */
1369 case 0x1e4: /* PM_PWSTST_MPU */
1370 case 0x220: /* CM_IDLEST1_CORE */
1371 case 0x224: /* CM_IDLEST2_CORE */
1372 case 0x22c: /* CM_IDLEST4_CORE */
1373 case 0x2c8: /* PM_WKDEP_CORE */
1374 case 0x2e4: /* PM_PWSTST_CORE */
1375 case 0x320: /* CM_IDLEST_GFX */
1376 case 0x3e4: /* PM_PWSTST_GFX */
1377 case 0x420: /* CM_IDLEST_WKUP */
1378 case 0x520: /* CM_IDLEST_CKGEN */
1379 case 0x820: /* CM_IDLEST_DSP */
1380 case 0x8e4: /* PM_PWSTST_DSP */
1381 OMAP_RO_REG(addr);
1382 return;
1383
1384 case 0x010: /* PRCM_SYSCONFIG */
1385 s->sysconfig = value & 1;
1386 break;
1387
1388 case 0x018: /* PRCM_IRQSTATUS_MPU */
1389 s->irqst[0] &= ~value;
1390 omap_prcm_int_update(s, 0);
1391 break;
1392 case 0x01c: /* PRCM_IRQENABLE_MPU */
1393 s->irqen[0] = value & 0x3f;
1394 omap_prcm_int_update(s, 0);
1395 break;
1396
1397 case 0x050: /* PRCM_VOLTCTRL */
1398 s->voltctrl = value & 0xf1c3;
1399 break;
1400
1401 case 0x060: /* PRCM_CLKSRC_CTRL */
1402 s->clksrc[0] = value & 0xdb;
1403 /* TODO update clocks */
1404 break;
1405
1406 case 0x070: /* PRCM_CLKOUT_CTRL */
1407 s->clkout[0] = value & 0xbbbb;
1408 /* TODO update clocks */
1409 break;
1410
1411 case 0x078: /* PRCM_CLKEMUL_CTRL */
1412 s->clkemul[0] = value & 1;
1413 /* TODO update clocks */
1414 break;
1415
1416 case 0x080: /* PRCM_CLKCFG_CTRL */
1417 break;
1418
1419 case 0x090: /* PRCM_VOLTSETUP */
1420 s->setuptime[0] = value & 0xffff;
1421 break;
1422 case 0x094: /* PRCM_CLKSSETUP */
1423 s->setuptime[1] = value & 0xffff;
1424 break;
1425
1426 case 0x098: /* PRCM_POLCTRL */
1427 s->clkpol[0] = value & 0x701;
1428 break;
1429
1430 case 0x0b0: /* GENERAL_PURPOSE1 */
1431 case 0x0b4: /* GENERAL_PURPOSE2 */
1432 case 0x0b8: /* GENERAL_PURPOSE3 */
1433 case 0x0bc: /* GENERAL_PURPOSE4 */
1434 case 0x0c0: /* GENERAL_PURPOSE5 */
1435 case 0x0c4: /* GENERAL_PURPOSE6 */
1436 case 0x0c8: /* GENERAL_PURPOSE7 */
1437 case 0x0cc: /* GENERAL_PURPOSE8 */
1438 case 0x0d0: /* GENERAL_PURPOSE9 */
1439 case 0x0d4: /* GENERAL_PURPOSE10 */
1440 case 0x0d8: /* GENERAL_PURPOSE11 */
1441 case 0x0dc: /* GENERAL_PURPOSE12 */
1442 case 0x0e0: /* GENERAL_PURPOSE13 */
1443 case 0x0e4: /* GENERAL_PURPOSE14 */
1444 case 0x0e8: /* GENERAL_PURPOSE15 */
1445 case 0x0ec: /* GENERAL_PURPOSE16 */
1446 case 0x0f0: /* GENERAL_PURPOSE17 */
1447 case 0x0f4: /* GENERAL_PURPOSE18 */
1448 case 0x0f8: /* GENERAL_PURPOSE19 */
1449 case 0x0fc: /* GENERAL_PURPOSE20 */
1450 s->scratch[(addr - 0xb0) >> 2] = value;
1451 break;
1452
1453 case 0x140: /* CM_CLKSEL_MPU */
1454 s->clksel[0] = value & 0x1f;
1455 /* TODO update clocks */
1456 break;
1457 case 0x148: /* CM_CLKSTCTRL_MPU */
1458 s->clkctrl[0] = value & 0x1f;
1459 break;
1460
1461 case 0x158: /* RM_RSTST_MPU */
1462 s->rst[0] &= ~value;
1463 break;
1464 case 0x1c8: /* PM_WKDEP_MPU */
1465 s->wkup[0] = value & 0x15;
1466 break;
1467
1468 case 0x1d4: /* PM_EVGENCTRL_MPU */
1469 s->ev = value & 0x1f;
1470 break;
1471 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1472 s->evtime[0] = value;
1473 break;
1474 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1475 s->evtime[1] = value;
1476 break;
1477
1478 case 0x1e0: /* PM_PWSTCTRL_MPU */
1479 s->power[0] = value & 0xc0f;
1480 break;
1481
1482 case 0x200: /* CM_FCLKEN1_CORE */
1483 s->clken[0] = value & 0xbfffffff;
1484 /* TODO update clocks */
1485 /* The EN_EAC bit only gets/puts func_96m_clk. */
1486 break;
1487 case 0x204: /* CM_FCLKEN2_CORE */
1488 s->clken[1] = value & 0x00000007;
1489 /* TODO update clocks */
1490 break;
1491 case 0x210: /* CM_ICLKEN1_CORE */
1492 s->clken[2] = value & 0xfffffff9;
1493 /* TODO update clocks */
1494 /* The EN_EAC bit only gets/puts core_l4_iclk. */
1495 break;
1496 case 0x214: /* CM_ICLKEN2_CORE */
1497 s->clken[3] = value & 0x00000007;
1498 /* TODO update clocks */
1499 break;
1500 case 0x21c: /* CM_ICLKEN4_CORE */
1501 s->clken[4] = value & 0x0000001f;
1502 /* TODO update clocks */
1503 break;
1504
1505 case 0x230: /* CM_AUTOIDLE1_CORE */
1506 s->clkidle[0] = value & 0xfffffff9;
1507 /* TODO update clocks */
1508 break;
1509 case 0x234: /* CM_AUTOIDLE2_CORE */
1510 s->clkidle[1] = value & 0x00000007;
1511 /* TODO update clocks */
1512 break;
1513 case 0x238: /* CM_AUTOIDLE3_CORE */
1514 s->clkidle[2] = value & 0x00000007;
1515 /* TODO update clocks */
1516 break;
1517 case 0x23c: /* CM_AUTOIDLE4_CORE */
1518 s->clkidle[3] = value & 0x0000001f;
1519 /* TODO update clocks */
1520 break;
1521
1522 case 0x240: /* CM_CLKSEL1_CORE */
1523 s->clksel[1] = value & 0x0fffbf7f;
1524 /* TODO update clocks */
1525 break;
1526
1527 case 0x244: /* CM_CLKSEL2_CORE */
1528 s->clksel[2] = value & 0x00fffffc;
1529 /* TODO update clocks */
1530 break;
1531
1532 case 0x248: /* CM_CLKSTCTRL_CORE */
1533 s->clkctrl[1] = value & 0x7;
1534 break;
1535
1536 case 0x2a0: /* PM_WKEN1_CORE */
1537 s->wken[0] = value & 0x04667ff8;
1538 break;
1539 case 0x2a4: /* PM_WKEN2_CORE */
1540 s->wken[1] = value & 0x00000005;
1541 break;
1542
1543 case 0x2b0: /* PM_WKST1_CORE */
1544 s->wkst[0] &= ~value;
1545 break;
1546 case 0x2b4: /* PM_WKST2_CORE */
1547 s->wkst[1] &= ~value;
1548 break;
1549
1550 case 0x2e0: /* PM_PWSTCTRL_CORE */
1551 s->power[1] = (value & 0x00fc3f) | (1 << 2);
1552 break;
1553
1554 case 0x300: /* CM_FCLKEN_GFX */
1555 s->clken[5] = value & 6;
1556 /* TODO update clocks */
1557 break;
1558 case 0x310: /* CM_ICLKEN_GFX */
1559 s->clken[6] = value & 1;
1560 /* TODO update clocks */
1561 break;
1562 case 0x340: /* CM_CLKSEL_GFX */
1563 s->clksel[3] = value & 7;
1564 /* TODO update clocks */
1565 break;
1566 case 0x348: /* CM_CLKSTCTRL_GFX */
1567 s->clkctrl[2] = value & 1;
1568 break;
1569 case 0x350: /* RM_RSTCTRL_GFX */
1570 s->rstctrl[0] = value & 1;
1571 /* TODO: reset */
1572 break;
1573 case 0x358: /* RM_RSTST_GFX */
1574 s->rst[1] &= ~value;
1575 break;
1576 case 0x3c8: /* PM_WKDEP_GFX */
1577 s->wkup[1] = value & 0x13;
1578 break;
1579 case 0x3e0: /* PM_PWSTCTRL_GFX */
1580 s->power[2] = (value & 0x00c0f) | (3 << 2);
1581 break;
1582
1583 case 0x400: /* CM_FCLKEN_WKUP */
1584 s->clken[7] = value & 0xd;
1585 /* TODO update clocks */
1586 break;
1587 case 0x410: /* CM_ICLKEN_WKUP */
1588 s->clken[8] = value & 0x3f;
1589 /* TODO update clocks */
1590 break;
1591 case 0x430: /* CM_AUTOIDLE_WKUP */
1592 s->clkidle[4] = value & 0x0000003f;
1593 /* TODO update clocks */
1594 break;
1595 case 0x440: /* CM_CLKSEL_WKUP */
1596 s->clksel[4] = value & 3;
1597 /* TODO update clocks */
1598 break;
1599 case 0x450: /* RM_RSTCTRL_WKUP */
1600 /* TODO: reset */
1601 if (value & 2)
1602 qemu_system_reset_request();
1603 break;
1604 case 0x454: /* RM_RSTTIME_WKUP */
1605 s->rsttime_wkup = value & 0x1fff;
1606 break;
1607 case 0x458: /* RM_RSTST_WKUP */
1608 s->rst[2] &= ~value;
1609 break;
1610 case 0x4a0: /* PM_WKEN_WKUP */
1611 s->wken[2] = value & 0x00000005;
1612 break;
1613 case 0x4b0: /* PM_WKST_WKUP */
1614 s->wkst[2] &= ~value;
1615 break;
1616
1617 case 0x500: /* CM_CLKEN_PLL */
1618 if (value & 0xffffff30)
1619 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
1620 "future compatibility\n", __FUNCTION__);
1621 if ((s->clken[9] ^ value) & 0xcc) {
1622 s->clken[9] &= ~0xcc;
1623 s->clken[9] |= value & 0xcc;
1624 omap_prcm_apll_update(s);
1625 }
1626 if ((s->clken[9] ^ value) & 3) {
1627 s->clken[9] &= ~3;
1628 s->clken[9] |= value & 3;
1629 omap_prcm_dpll_update(s);
1630 }
1631 break;
1632 case 0x530: /* CM_AUTOIDLE_PLL */
1633 s->clkidle[5] = value & 0x000000cf;
1634 /* TODO update clocks */
1635 break;
1636 case 0x540: /* CM_CLKSEL1_PLL */
1637 if (value & 0xfc4000d7)
1638 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
1639 "future compatibility\n", __FUNCTION__);
1640 if ((s->clksel[5] ^ value) & 0x003fff00) {
1641 s->clksel[5] = value & 0x03bfff28;
1642 omap_prcm_dpll_update(s);
1643 }
1644 /* TODO update the other clocks */
1645
1646 s->clksel[5] = value & 0x03bfff28;
1647 break;
1648 case 0x544: /* CM_CLKSEL2_PLL */
1649 if (value & ~3)
1650 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
1651 "future compatibility\n", __FUNCTION__);
1652 if (s->clksel[6] != (value & 3)) {
1653 s->clksel[6] = value & 3;
1654 omap_prcm_dpll_update(s);
1655 }
1656 break;
1657
1658 case 0x800: /* CM_FCLKEN_DSP */
1659 s->clken[10] = value & 0x501;
1660 /* TODO update clocks */
1661 break;
1662 case 0x810: /* CM_ICLKEN_DSP */
1663 s->clken[11] = value & 0x2;
1664 /* TODO update clocks */
1665 break;
1666 case 0x830: /* CM_AUTOIDLE_DSP */
1667 s->clkidle[6] = value & 0x2;
1668 /* TODO update clocks */
1669 break;
1670 case 0x840: /* CM_CLKSEL_DSP */
1671 s->clksel[7] = value & 0x3fff;
1672 /* TODO update clocks */
1673 break;
1674 case 0x848: /* CM_CLKSTCTRL_DSP */
1675 s->clkctrl[3] = value & 0x101;
1676 break;
1677 case 0x850: /* RM_RSTCTRL_DSP */
1678 /* TODO: reset */
1679 break;
1680 case 0x858: /* RM_RSTST_DSP */
1681 s->rst[3] &= ~value;
1682 break;
1683 case 0x8c8: /* PM_WKDEP_DSP */
1684 s->wkup[2] = value & 0x13;
1685 break;
1686 case 0x8e0: /* PM_PWSTCTRL_DSP */
1687 s->power[3] = (value & 0x03017) | (3 << 2);
1688 break;
1689
1690 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1691 s->irqst[1] &= ~value;
1692 omap_prcm_int_update(s, 1);
1693 break;
1694 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1695 s->irqen[1] = value & 0x7;
1696 omap_prcm_int_update(s, 1);
1697 break;
1698
1699 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1700 s->irqst[2] &= ~value;
1701 omap_prcm_int_update(s, 2);
1702 break;
1703 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1704 s->irqen[2] = value & 0x7;
1705 omap_prcm_int_update(s, 2);
1706 break;
1707
1708 default:
1709 OMAP_BAD_REG(addr);
1710 return;
1711 }
1712 }
1713
1714 static const MemoryRegionOps omap_prcm_ops = {
1715 .read = omap_prcm_read,
1716 .write = omap_prcm_write,
1717 .endianness = DEVICE_NATIVE_ENDIAN,
1718 };
1719
1720 static void omap_prcm_reset(struct omap_prcm_s *s)
1721 {
1722 s->sysconfig = 0;
1723 s->irqst[0] = 0;
1724 s->irqst[1] = 0;
1725 s->irqst[2] = 0;
1726 s->irqen[0] = 0;
1727 s->irqen[1] = 0;
1728 s->irqen[2] = 0;
1729 s->voltctrl = 0x1040;
1730 s->ev = 0x14;
1731 s->evtime[0] = 0;
1732 s->evtime[1] = 0;
1733 s->clkctrl[0] = 0;
1734 s->clkctrl[1] = 0;
1735 s->clkctrl[2] = 0;
1736 s->clkctrl[3] = 0;
1737 s->clken[1] = 7;
1738 s->clken[3] = 7;
1739 s->clken[4] = 0;
1740 s->clken[5] = 0;
1741 s->clken[6] = 0;
1742 s->clken[7] = 0xc;
1743 s->clken[8] = 0x3e;
1744 s->clken[9] = 0x0d;
1745 s->clken[10] = 0;
1746 s->clken[11] = 0;
1747 s->clkidle[0] = 0;
1748 s->clkidle[2] = 7;
1749 s->clkidle[3] = 0;
1750 s->clkidle[4] = 0;
1751 s->clkidle[5] = 0x0c;
1752 s->clkidle[6] = 0;
1753 s->clksel[0] = 0x01;
1754 s->clksel[1] = 0x02100121;
1755 s->clksel[2] = 0x00000000;
1756 s->clksel[3] = 0x01;
1757 s->clksel[4] = 0;
1758 s->clksel[7] = 0x0121;
1759 s->wkup[0] = 0x15;
1760 s->wkup[1] = 0x13;
1761 s->wkup[2] = 0x13;
1762 s->wken[0] = 0x04667ff8;
1763 s->wken[1] = 0x00000005;
1764 s->wken[2] = 5;
1765 s->wkst[0] = 0;
1766 s->wkst[1] = 0;
1767 s->wkst[2] = 0;
1768 s->power[0] = 0x00c;
1769 s->power[1] = 4;
1770 s->power[2] = 0x0000c;
1771 s->power[3] = 0x14;
1772 s->rstctrl[0] = 1;
1773 s->rst[3] = 1;
1774 omap_prcm_apll_update(s);
1775 omap_prcm_dpll_update(s);
1776 }
1777
1778 static void omap_prcm_coldreset(struct omap_prcm_s *s)
1779 {
1780 s->setuptime[0] = 0;
1781 s->setuptime[1] = 0;
1782 memset(&s->scratch, 0, sizeof(s->scratch));
1783 s->rst[0] = 0x01;
1784 s->rst[1] = 0x00;
1785 s->rst[2] = 0x01;
1786 s->clken[0] = 0;
1787 s->clken[2] = 0;
1788 s->clkidle[1] = 0;
1789 s->clksel[5] = 0;
1790 s->clksel[6] = 2;
1791 s->clksrc[0] = 0x43;
1792 s->clkout[0] = 0x0303;
1793 s->clkemul[0] = 0;
1794 s->clkpol[0] = 0x100;
1795 s->rsttime_wkup = 0x1002;
1796
1797 omap_prcm_reset(s);
1798 }
1799
1800 static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
1801 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
1802 struct omap_mpu_state_s *mpu)
1803 {
1804 struct omap_prcm_s *s = (struct omap_prcm_s *)
1805 g_malloc0(sizeof(struct omap_prcm_s));
1806
1807 s->irq[0] = mpu_int;
1808 s->irq[1] = dsp_int;
1809 s->irq[2] = iva_int;
1810 s->mpu = mpu;
1811 omap_prcm_coldreset(s);
1812
1813 memory_region_init_io(&s->iomem0, NULL, &omap_prcm_ops, s, "omap.pcrm0",
1814 omap_l4_region_size(ta, 0));
1815 memory_region_init_io(&s->iomem1, NULL, &omap_prcm_ops, s, "omap.pcrm1",
1816 omap_l4_region_size(ta, 1));
1817 omap_l4_attach(ta, 0, &s->iomem0);
1818 omap_l4_attach(ta, 1, &s->iomem1);
1819
1820 return s;
1821 }
1822
1823 /* System and Pinout control */
1824 struct omap_sysctl_s {
1825 struct omap_mpu_state_s *mpu;
1826 MemoryRegion iomem;
1827
1828 uint32_t sysconfig;
1829 uint32_t devconfig;
1830 uint32_t psaconfig;
1831 uint32_t padconf[0x45];
1832 uint8_t obs;
1833 uint32_t msuspendmux[5];
1834 };
1835
1836 static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
1837 {
1838
1839 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1840 int pad_offset, byte_offset;
1841 int value;
1842
1843 switch (addr) {
1844 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1845 pad_offset = (addr - 0x30) >> 2;
1846 byte_offset = (addr - 0x30) & (4 - 1);
1847
1848 value = s->padconf[pad_offset];
1849 value = (value >> (byte_offset * 8)) & 0xff;
1850
1851 return value;
1852
1853 default:
1854 break;
1855 }
1856
1857 OMAP_BAD_REG(addr);
1858 return 0;
1859 }
1860
1861 static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
1862 {
1863 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1864
1865 switch (addr) {
1866 case 0x000: /* CONTROL_REVISION */
1867 return 0x20;
1868
1869 case 0x010: /* CONTROL_SYSCONFIG */
1870 return s->sysconfig;
1871
1872 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1873 return s->padconf[(addr - 0x30) >> 2];
1874
1875 case 0x270: /* CONTROL_DEBOBS */
1876 return s->obs;
1877
1878 case 0x274: /* CONTROL_DEVCONF */
1879 return s->devconfig;
1880
1881 case 0x28c: /* CONTROL_EMU_SUPPORT */
1882 return 0;
1883
1884 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
1885 return s->msuspendmux[0];
1886 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
1887 return s->msuspendmux[1];
1888 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
1889 return s->msuspendmux[2];
1890 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
1891 return s->msuspendmux[3];
1892 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
1893 return s->msuspendmux[4];
1894 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1895 return 0;
1896
1897 case 0x2b8: /* CONTROL_PSA_CTRL */
1898 return s->psaconfig;
1899 case 0x2bc: /* CONTROL_PSA_CMD */
1900 case 0x2c0: /* CONTROL_PSA_VALUE */
1901 return 0;
1902
1903 case 0x2b0: /* CONTROL_SEC_CTRL */
1904 return 0x800000f1;
1905 case 0x2d0: /* CONTROL_SEC_EMU */
1906 return 0x80000015;
1907 case 0x2d4: /* CONTROL_SEC_TAP */
1908 return 0x8000007f;
1909 case 0x2b4: /* CONTROL_SEC_TEST */
1910 case 0x2f0: /* CONTROL_SEC_STATUS */
1911 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
1912 /* Secure mode is not present on general-pusrpose device. Outside
1913 * secure mode these values cannot be read or written. */
1914 return 0;
1915
1916 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
1917 return 0xff;
1918 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
1919 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
1920 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
1921 /* No secure mode so no Extended Secure RAM present. */
1922 return 0;
1923
1924 case 0x2f8: /* CONTROL_STATUS */
1925 /* Device Type => General-purpose */
1926 return 0x0300;
1927 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
1928
1929 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
1930 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
1931 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
1932 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
1933 return 0xdecafbad;
1934
1935 case 0x310: /* CONTROL_RAND_KEY_0 */
1936 case 0x314: /* CONTROL_RAND_KEY_1 */
1937 case 0x318: /* CONTROL_RAND_KEY_2 */
1938 case 0x31c: /* CONTROL_RAND_KEY_3 */
1939 case 0x320: /* CONTROL_CUST_KEY_0 */
1940 case 0x324: /* CONTROL_CUST_KEY_1 */
1941 case 0x330: /* CONTROL_TEST_KEY_0 */
1942 case 0x334: /* CONTROL_TEST_KEY_1 */
1943 case 0x338: /* CONTROL_TEST_KEY_2 */
1944 case 0x33c: /* CONTROL_TEST_KEY_3 */
1945 case 0x340: /* CONTROL_TEST_KEY_4 */
1946 case 0x344: /* CONTROL_TEST_KEY_5 */
1947 case 0x348: /* CONTROL_TEST_KEY_6 */
1948 case 0x34c: /* CONTROL_TEST_KEY_7 */
1949 case 0x350: /* CONTROL_TEST_KEY_8 */
1950 case 0x354: /* CONTROL_TEST_KEY_9 */
1951 /* Can only be accessed in secure mode and when C_FieldAccEnable
1952 * bit is set in CONTROL_SEC_CTRL.
1953 * TODO: otherwise an interconnect access error is generated. */
1954 return 0;
1955 }
1956
1957 OMAP_BAD_REG(addr);
1958 return 0;
1959 }
1960
1961 static void omap_sysctl_write8(void *opaque, hwaddr addr,
1962 uint32_t value)
1963 {
1964 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1965 int pad_offset, byte_offset;
1966 int prev_value;
1967
1968 switch (addr) {
1969 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1970 pad_offset = (addr - 0x30) >> 2;
1971 byte_offset = (addr - 0x30) & (4 - 1);
1972
1973 prev_value = s->padconf[pad_offset];
1974 prev_value &= ~(0xff << (byte_offset * 8));
1975 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
1976 s->padconf[pad_offset] = prev_value;
1977 break;
1978
1979 default:
1980 OMAP_BAD_REG(addr);
1981 break;
1982 }
1983 }
1984
1985 static void omap_sysctl_write(void *opaque, hwaddr addr,
1986 uint32_t value)
1987 {
1988 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1989
1990 switch (addr) {
1991 case 0x000: /* CONTROL_REVISION */
1992 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1993 case 0x2c0: /* CONTROL_PSA_VALUE */
1994 case 0x2f8: /* CONTROL_STATUS */
1995 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
1996 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
1997 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
1998 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
1999 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2000 case 0x310: /* CONTROL_RAND_KEY_0 */
2001 case 0x314: /* CONTROL_RAND_KEY_1 */
2002 case 0x318: /* CONTROL_RAND_KEY_2 */
2003 case 0x31c: /* CONTROL_RAND_KEY_3 */
2004 case 0x320: /* CONTROL_CUST_KEY_0 */
2005 case 0x324: /* CONTROL_CUST_KEY_1 */
2006 case 0x330: /* CONTROL_TEST_KEY_0 */
2007 case 0x334: /* CONTROL_TEST_KEY_1 */
2008 case 0x338: /* CONTROL_TEST_KEY_2 */
2009 case 0x33c: /* CONTROL_TEST_KEY_3 */
2010 case 0x340: /* CONTROL_TEST_KEY_4 */
2011 case 0x344: /* CONTROL_TEST_KEY_5 */
2012 case 0x348: /* CONTROL_TEST_KEY_6 */
2013 case 0x34c: /* CONTROL_TEST_KEY_7 */
2014 case 0x350: /* CONTROL_TEST_KEY_8 */
2015 case 0x354: /* CONTROL_TEST_KEY_9 */
2016 OMAP_RO_REG(addr);
2017 return;
2018
2019 case 0x010: /* CONTROL_SYSCONFIG */
2020 s->sysconfig = value & 0x1e;
2021 break;
2022
2023 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2024 /* XXX: should check constant bits */
2025 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
2026 break;
2027
2028 case 0x270: /* CONTROL_DEBOBS */
2029 s->obs = value & 0xff;
2030 break;
2031
2032 case 0x274: /* CONTROL_DEVCONF */
2033 s->devconfig = value & 0xffffc7ff;
2034 break;
2035
2036 case 0x28c: /* CONTROL_EMU_SUPPORT */
2037 break;
2038
2039 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2040 s->msuspendmux[0] = value & 0x3fffffff;
2041 break;
2042 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2043 s->msuspendmux[1] = value & 0x3fffffff;
2044 break;
2045 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2046 s->msuspendmux[2] = value & 0x3fffffff;
2047 break;
2048 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2049 s->msuspendmux[3] = value & 0x3fffffff;
2050 break;
2051 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2052 s->msuspendmux[4] = value & 0x3fffffff;
2053 break;
2054
2055 case 0x2b8: /* CONTROL_PSA_CTRL */
2056 s->psaconfig = value & 0x1c;
2057 s->psaconfig |= (value & 0x20) ? 2 : 1;
2058 break;
2059 case 0x2bc: /* CONTROL_PSA_CMD */
2060 break;
2061
2062 case 0x2b0: /* CONTROL_SEC_CTRL */
2063 case 0x2b4: /* CONTROL_SEC_TEST */
2064 case 0x2d0: /* CONTROL_SEC_EMU */
2065 case 0x2d4: /* CONTROL_SEC_TAP */
2066 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2067 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2068 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2069 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2070 case 0x2f0: /* CONTROL_SEC_STATUS */
2071 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2072 break;
2073
2074 default:
2075 OMAP_BAD_REG(addr);
2076 return;
2077 }
2078 }
2079
2080 static const MemoryRegionOps omap_sysctl_ops = {
2081 .old_mmio = {
2082 .read = {
2083 omap_sysctl_read8,
2084 omap_badwidth_read32, /* TODO */
2085 omap_sysctl_read,
2086 },
2087 .write = {
2088 omap_sysctl_write8,
2089 omap_badwidth_write32, /* TODO */
2090 omap_sysctl_write,
2091 },
2092 },
2093 .endianness = DEVICE_NATIVE_ENDIAN,
2094 };
2095
2096 static void omap_sysctl_reset(struct omap_sysctl_s *s)
2097 {
2098 /* (power-on reset) */
2099 s->sysconfig = 0;
2100 s->obs = 0;
2101 s->devconfig = 0x0c000000;
2102 s->msuspendmux[0] = 0x00000000;
2103 s->msuspendmux[1] = 0x00000000;
2104 s->msuspendmux[2] = 0x00000000;
2105 s->msuspendmux[3] = 0x00000000;
2106 s->msuspendmux[4] = 0x00000000;
2107 s->psaconfig = 1;
2108
2109 s->padconf[0x00] = 0x000f0f0f;
2110 s->padconf[0x01] = 0x00000000;
2111 s->padconf[0x02] = 0x00000000;
2112 s->padconf[0x03] = 0x00000000;
2113 s->padconf[0x04] = 0x00000000;
2114 s->padconf[0x05] = 0x00000000;
2115 s->padconf[0x06] = 0x00000000;
2116 s->padconf[0x07] = 0x00000000;
2117 s->padconf[0x08] = 0x08080800;
2118 s->padconf[0x09] = 0x08080808;
2119 s->padconf[0x0a] = 0x08080808;
2120 s->padconf[0x0b] = 0x08080808;
2121 s->padconf[0x0c] = 0x08080808;
2122 s->padconf[0x0d] = 0x08080800;
2123 s->padconf[0x0e] = 0x08080808;
2124 s->padconf[0x0f] = 0x08080808;
2125 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
2126 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
2127 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
2128 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
2129 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
2130 s->padconf[0x15] = 0x18181818;
2131 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
2132 s->padconf[0x17] = 0x1f001f00;
2133 s->padconf[0x18] = 0x1f1f1f1f;
2134 s->padconf[0x19] = 0x00000000;
2135 s->padconf[0x1a] = 0x1f180000;
2136 s->padconf[0x1b] = 0x00001f1f;
2137 s->padconf[0x1c] = 0x1f001f00;
2138 s->padconf[0x1d] = 0x00000000;
2139 s->padconf[0x1e] = 0x00000000;
2140 s->padconf[0x1f] = 0x08000000;
2141 s->padconf[0x20] = 0x08080808;
2142 s->padconf[0x21] = 0x08080808;
2143 s->padconf[0x22] = 0x0f080808;
2144 s->padconf[0x23] = 0x0f0f0f0f;
2145 s->padconf[0x24] = 0x000f0f0f;
2146 s->padconf[0x25] = 0x1f1f1f0f;
2147 s->padconf[0x26] = 0x080f0f1f;
2148 s->padconf[0x27] = 0x070f1808;
2149 s->padconf[0x28] = 0x0f070707;
2150 s->padconf[0x29] = 0x000f0f1f;
2151 s->padconf[0x2a] = 0x0f0f0f1f;
2152 s->padconf[0x2b] = 0x08000000;
2153 s->padconf[0x2c] = 0x0000001f;
2154 s->padconf[0x2d] = 0x0f0f1f00;
2155 s->padconf[0x2e] = 0x1f1f0f0f;
2156 s->padconf[0x2f] = 0x0f1f1f1f;
2157 s->padconf[0x30] = 0x0f0f0f0f;
2158 s->padconf[0x31] = 0x0f1f0f1f;
2159 s->padconf[0x32] = 0x0f0f0f0f;
2160 s->padconf[0x33] = 0x0f1f0f1f;
2161 s->padconf[0x34] = 0x1f1f0f0f;
2162 s->padconf[0x35] = 0x0f0f1f1f;
2163 s->padconf[0x36] = 0x0f0f1f0f;
2164 s->padconf[0x37] = 0x0f0f0f0f;
2165 s->padconf[0x38] = 0x1f18180f;
2166 s->padconf[0x39] = 0x1f1f1f1f;
2167 s->padconf[0x3a] = 0x00001f1f;
2168 s->padconf[0x3b] = 0x00000000;
2169 s->padconf[0x3c] = 0x00000000;
2170 s->padconf[0x3d] = 0x0f0f0f0f;
2171 s->padconf[0x3e] = 0x18000f0f;
2172 s->padconf[0x3f] = 0x00070000;
2173 s->padconf[0x40] = 0x00000707;
2174 s->padconf[0x41] = 0x0f1f0700;
2175 s->padconf[0x42] = 0x1f1f070f;
2176 s->padconf[0x43] = 0x0008081f;
2177 s->padconf[0x44] = 0x00000800;
2178 }
2179
2180 static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
2181 omap_clk iclk, struct omap_mpu_state_s *mpu)
2182 {
2183 struct omap_sysctl_s *s = (struct omap_sysctl_s *)
2184 g_malloc0(sizeof(struct omap_sysctl_s));
2185
2186 s->mpu = mpu;
2187 omap_sysctl_reset(s);
2188
2189 memory_region_init_io(&s->iomem, NULL, &omap_sysctl_ops, s, "omap.sysctl",
2190 omap_l4_region_size(ta, 0));
2191 omap_l4_attach(ta, 0, &s->iomem);
2192
2193 return s;
2194 }
2195
2196 /* General chip reset */
2197 static void omap2_mpu_reset(void *opaque)
2198 {
2199 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
2200
2201 omap_dma_reset(mpu->dma);
2202 omap_prcm_reset(mpu->prcm);
2203 omap_sysctl_reset(mpu->sysc);
2204 omap_gp_timer_reset(mpu->gptimer[0]);
2205 omap_gp_timer_reset(mpu->gptimer[1]);
2206 omap_gp_timer_reset(mpu->gptimer[2]);
2207 omap_gp_timer_reset(mpu->gptimer[3]);
2208 omap_gp_timer_reset(mpu->gptimer[4]);
2209 omap_gp_timer_reset(mpu->gptimer[5]);
2210 omap_gp_timer_reset(mpu->gptimer[6]);
2211 omap_gp_timer_reset(mpu->gptimer[7]);
2212 omap_gp_timer_reset(mpu->gptimer[8]);
2213 omap_gp_timer_reset(mpu->gptimer[9]);
2214 omap_gp_timer_reset(mpu->gptimer[10]);
2215 omap_gp_timer_reset(mpu->gptimer[11]);
2216 omap_synctimer_reset(mpu->synctimer);
2217 omap_sdrc_reset(mpu->sdrc);
2218 omap_gpmc_reset(mpu->gpmc);
2219 omap_dss_reset(mpu->dss);
2220 omap_uart_reset(mpu->uart[0]);
2221 omap_uart_reset(mpu->uart[1]);
2222 omap_uart_reset(mpu->uart[2]);
2223 omap_mmc_reset(mpu->mmc);
2224 omap_mcspi_reset(mpu->mcspi[0]);
2225 omap_mcspi_reset(mpu->mcspi[1]);
2226 cpu_reset(CPU(mpu->cpu));
2227 }
2228
2229 static int omap2_validate_addr(struct omap_mpu_state_s *s,
2230 hwaddr addr)
2231 {
2232 return 1;
2233 }
2234
2235 static const struct dma_irq_map omap2_dma_irq_map[] = {
2236 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
2237 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
2238 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
2239 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
2240 };
2241
2242 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
2243 unsigned long sdram_size,
2244 const char *core)
2245 {
2246 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
2247 g_malloc0(sizeof(struct omap_mpu_state_s));
2248 qemu_irq dma_irqs[4];
2249 DriveInfo *dinfo;
2250 int i;
2251 SysBusDevice *busdev;
2252 struct omap_target_agent_s *ta;
2253
2254 /* Core */
2255 s->mpu_model = omap2420;
2256 s->cpu = cpu_arm_init(core ?: "arm1136-r2");
2257 if (s->cpu == NULL) {
2258 fprintf(stderr, "Unable to find CPU definition\n");
2259 exit(1);
2260 }
2261 s->sdram_size = sdram_size;
2262 s->sram_size = OMAP242X_SRAM_SIZE;
2263
2264 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
2265
2266 /* Clocks */
2267 omap_clk_init(s);
2268
2269 /* Memory-mapped stuff */
2270 memory_region_init_ram(&s->sdram, NULL, "omap2.dram", s->sdram_size,
2271 &error_abort);
2272 vmstate_register_ram_global(&s->sdram);
2273 memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
2274 memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size,
2275 &error_abort);
2276 vmstate_register_ram_global(&s->sram);
2277 memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
2278
2279 s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
2280
2281 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
2282 s->ih[0] = qdev_create(NULL, "omap2-intc");
2283 qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
2284 qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk"));
2285 qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk"));
2286 qdev_init_nofail(s->ih[0]);
2287 busdev = SYS_BUS_DEVICE(s->ih[0]);
2288 sysbus_connect_irq(busdev, 0,
2289 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
2290 sysbus_connect_irq(busdev, 1,
2291 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
2292 sysbus_mmio_map(busdev, 0, 0x480fe000);
2293 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
2294 qdev_get_gpio_in(s->ih[0],
2295 OMAP_INT_24XX_PRCM_MPU_IRQ),
2296 NULL, NULL, s);
2297
2298 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
2299 omap_findclk(s, "omapctrl_iclk"), s);
2300
2301 for (i = 0; i < 4; i++) {
2302 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih],
2303 omap2_dma_irq_map[i].intr);
2304 }
2305 s->dma = omap_dma4_init(0x48056000, dma_irqs, sysmem, s, 256, 32,
2306 omap_findclk(s, "sdma_iclk"),
2307 omap_findclk(s, "sdma_fclk"));
2308 s->port->addr_valid = omap2_validate_addr;
2309
2310 /* Register SDRAM and SRAM ports for fast DMA transfers. */
2311 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram),
2312 OMAP2_Q2_BASE, s->sdram_size);
2313 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram),
2314 OMAP2_SRAM_BASE, s->sram_size);
2315
2316 s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19),
2317 qdev_get_gpio_in(s->ih[0],
2318 OMAP_INT_24XX_UART1_IRQ),
2319 omap_findclk(s, "uart1_fclk"),
2320 omap_findclk(s, "uart1_iclk"),
2321 s->drq[OMAP24XX_DMA_UART1_TX],
2322 s->drq[OMAP24XX_DMA_UART1_RX],
2323 "uart1",
2324 serial_hds[0]);
2325 s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20),
2326 qdev_get_gpio_in(s->ih[0],
2327 OMAP_INT_24XX_UART2_IRQ),
2328 omap_findclk(s, "uart2_fclk"),
2329 omap_findclk(s, "uart2_iclk"),
2330 s->drq[OMAP24XX_DMA_UART2_TX],
2331 s->drq[OMAP24XX_DMA_UART2_RX],
2332 "uart2",
2333 serial_hds[0] ? serial_hds[1] : NULL);
2334 s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21),
2335 qdev_get_gpio_in(s->ih[0],
2336 OMAP_INT_24XX_UART3_IRQ),
2337 omap_findclk(s, "uart3_fclk"),
2338 omap_findclk(s, "uart3_iclk"),
2339 s->drq[OMAP24XX_DMA_UART3_TX],
2340 s->drq[OMAP24XX_DMA_UART3_RX],
2341 "uart3",
2342 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
2343
2344 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
2345 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1),
2346 omap_findclk(s, "wu_gpt1_clk"),
2347 omap_findclk(s, "wu_l4_iclk"));
2348 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
2349 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2),
2350 omap_findclk(s, "core_gpt2_clk"),
2351 omap_findclk(s, "core_l4_iclk"));
2352 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
2353 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3),
2354 omap_findclk(s, "core_gpt3_clk"),
2355 omap_findclk(s, "core_l4_iclk"));
2356 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
2357 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4),
2358 omap_findclk(s, "core_gpt4_clk"),
2359 omap_findclk(s, "core_l4_iclk"));
2360 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
2361 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5),
2362 omap_findclk(s, "core_gpt5_clk"),
2363 omap_findclk(s, "core_l4_iclk"));
2364 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
2365 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6),
2366 omap_findclk(s, "core_gpt6_clk"),
2367 omap_findclk(s, "core_l4_iclk"));
2368 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
2369 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7),
2370 omap_findclk(s, "core_gpt7_clk"),
2371 omap_findclk(s, "core_l4_iclk"));
2372 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
2373 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8),
2374 omap_findclk(s, "core_gpt8_clk"),
2375 omap_findclk(s, "core_l4_iclk"));
2376 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
2377 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9),
2378 omap_findclk(s, "core_gpt9_clk"),
2379 omap_findclk(s, "core_l4_iclk"));
2380 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
2381 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10),
2382 omap_findclk(s, "core_gpt10_clk"),
2383 omap_findclk(s, "core_l4_iclk"));
2384 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
2385 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11),
2386 omap_findclk(s, "core_gpt11_clk"),
2387 omap_findclk(s, "core_l4_iclk"));
2388 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
2389 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12),
2390 omap_findclk(s, "core_gpt12_clk"),
2391 omap_findclk(s, "core_l4_iclk"));
2392
2393 omap_tap_init(omap_l4ta(s->l4, 2), s);
2394
2395 s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s,
2396 omap_findclk(s, "clk32-kHz"),
2397 omap_findclk(s, "core_l4_iclk"));
2398
2399 s->i2c[0] = qdev_create(NULL, "omap_i2c");
2400 qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
2401 qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk"));
2402 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk"));
2403 qdev_init_nofail(s->i2c[0]);
2404 busdev = SYS_BUS_DEVICE(s->i2c[0]);
2405 sysbus_connect_irq(busdev, 0,
2406 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ));
2407 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]);
2408 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]);
2409 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0));
2410
2411 s->i2c[1] = qdev_create(NULL, "omap_i2c");
2412 qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
2413 qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk"));
2414 qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk"));
2415 qdev_init_nofail(s->i2c[1]);
2416 busdev = SYS_BUS_DEVICE(s->i2c[1]);
2417 sysbus_connect_irq(busdev, 0,
2418 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ));
2419 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]);
2420 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]);
2421 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0));
2422
2423 s->gpio = qdev_create(NULL, "omap2-gpio");
2424 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
2425 qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk"));
2426 qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk"));
2427 qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk"));
2428 qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk"));
2429 qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk"));
2430 if (s->mpu_model == omap2430) {
2431 qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk"));
2432 }
2433 qdev_init_nofail(s->gpio);
2434 busdev = SYS_BUS_DEVICE(s->gpio);
2435 sysbus_connect_irq(busdev, 0,
2436 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
2437 sysbus_connect_irq(busdev, 3,
2438 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2));
2439 sysbus_connect_irq(busdev, 6,
2440 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3));
2441 sysbus_connect_irq(busdev, 9,
2442 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4));
2443 if (s->mpu_model == omap2430) {
2444 sysbus_connect_irq(busdev, 12,
2445 qdev_get_gpio_in(s->ih[0],
2446 OMAP_INT_243X_GPIO_BANK5));
2447 }
2448 ta = omap_l4ta(s->l4, 3);
2449 sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1));
2450 sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0));
2451 sysbus_mmio_map(busdev, 2, omap_l4_region_base(ta, 2));
2452 sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4));
2453 sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5));
2454
2455 s->sdrc = omap_sdrc_init(sysmem, 0x68009000);
2456 s->gpmc = omap_gpmc_init(s, 0x6800a000,
2457 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ),
2458 s->drq[OMAP24XX_DMA_GPMC]);
2459
2460 dinfo = drive_get(IF_SD, 0, 0);
2461 if (!dinfo) {
2462 fprintf(stderr, "qemu: missing SecureDigital device\n");
2463 exit(1);
2464 }
2465 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9),
2466 blk_by_legacy_dinfo(dinfo),
2467 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ),
2468 &s->drq[OMAP24XX_DMA_MMC1_TX],
2469 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
2470
2471 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
2472 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ),
2473 &s->drq[OMAP24XX_DMA_SPI1_TX0],
2474 omap_findclk(s, "spi1_fclk"),
2475 omap_findclk(s, "spi1_iclk"));
2476 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
2477 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ),
2478 &s->drq[OMAP24XX_DMA_SPI2_TX0],
2479 omap_findclk(s, "spi2_fclk"),
2480 omap_findclk(s, "spi2_iclk"));
2481
2482 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800,
2483 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
2484 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ),
2485 s->drq[OMAP24XX_DMA_DSS],
2486 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
2487 omap_findclk(s, "dss_54m_clk"),
2488 omap_findclk(s, "dss_l3_iclk"),
2489 omap_findclk(s, "dss_l4_iclk"));
2490
2491 omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000,
2492 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI),
2493 omap_findclk(s, "emul_ck"),
2494 serial_hds[0] && serial_hds[1] && serial_hds[2] ?
2495 serial_hds[3] : NULL);
2496
2497 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
2498 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ),
2499 /* Ten consecutive lines */
2500 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
2501 omap_findclk(s, "func_96m_clk"),
2502 omap_findclk(s, "core_l4_iclk"));
2503
2504 /* All register mappings (includin those not currenlty implemented):
2505 * SystemControlMod 48000000 - 48000fff
2506 * SystemControlL4 48001000 - 48001fff
2507 * 32kHz Timer Mod 48004000 - 48004fff
2508 * 32kHz Timer L4 48005000 - 48005fff
2509 * PRCM ModA 48008000 - 480087ff
2510 * PRCM ModB 48008800 - 48008fff
2511 * PRCM L4 48009000 - 48009fff
2512 * TEST-BCM Mod 48012000 - 48012fff
2513 * TEST-BCM L4 48013000 - 48013fff
2514 * TEST-TAP Mod 48014000 - 48014fff
2515 * TEST-TAP L4 48015000 - 48015fff
2516 * GPIO1 Mod 48018000 - 48018fff
2517 * GPIO Top 48019000 - 48019fff
2518 * GPIO2 Mod 4801a000 - 4801afff
2519 * GPIO L4 4801b000 - 4801bfff
2520 * GPIO3 Mod 4801c000 - 4801cfff
2521 * GPIO4 Mod 4801e000 - 4801efff
2522 * WDTIMER1 Mod 48020000 - 48010fff
2523 * WDTIMER Top 48021000 - 48011fff
2524 * WDTIMER2 Mod 48022000 - 48012fff
2525 * WDTIMER L4 48023000 - 48013fff
2526 * WDTIMER3 Mod 48024000 - 48014fff
2527 * WDTIMER3 L4 48025000 - 48015fff
2528 * WDTIMER4 Mod 48026000 - 48016fff
2529 * WDTIMER4 L4 48027000 - 48017fff
2530 * GPTIMER1 Mod 48028000 - 48018fff
2531 * GPTIMER1 L4 48029000 - 48019fff
2532 * GPTIMER2 Mod 4802a000 - 4801afff
2533 * GPTIMER2 L4 4802b000 - 4801bfff
2534 * L4-Config AP 48040000 - 480407ff
2535 * L4-Config IP 48040800 - 48040fff
2536 * L4-Config LA 48041000 - 48041fff
2537 * ARM11ETB Mod 48048000 - 48049fff
2538 * ARM11ETB L4 4804a000 - 4804afff
2539 * DISPLAY Top 48050000 - 480503ff
2540 * DISPLAY DISPC 48050400 - 480507ff
2541 * DISPLAY RFBI 48050800 - 48050bff
2542 * DISPLAY VENC 48050c00 - 48050fff
2543 * DISPLAY L4 48051000 - 48051fff
2544 * CAMERA Top 48052000 - 480523ff
2545 * CAMERA core 48052400 - 480527ff
2546 * CAMERA DMA 48052800 - 48052bff
2547 * CAMERA MMU 48052c00 - 48052fff
2548 * CAMERA L4 48053000 - 48053fff
2549 * SDMA Mod 48056000 - 48056fff
2550 * SDMA L4 48057000 - 48057fff
2551 * SSI Top 48058000 - 48058fff
2552 * SSI GDD 48059000 - 48059fff
2553 * SSI Port1 4805a000 - 4805afff
2554 * SSI Port2 4805b000 - 4805bfff
2555 * SSI L4 4805c000 - 4805cfff
2556 * USB Mod 4805e000 - 480fefff
2557 * USB L4 4805f000 - 480fffff
2558 * WIN_TRACER1 Mod 48060000 - 48060fff
2559 * WIN_TRACER1 L4 48061000 - 48061fff
2560 * WIN_TRACER2 Mod 48062000 - 48062fff
2561 * WIN_TRACER2 L4 48063000 - 48063fff
2562 * WIN_TRACER3 Mod 48064000 - 48064fff
2563 * WIN_TRACER3 L4 48065000 - 48065fff
2564 * WIN_TRACER4 Top 48066000 - 480660ff
2565 * WIN_TRACER4 ETT 48066100 - 480661ff
2566 * WIN_TRACER4 WT 48066200 - 480662ff
2567 * WIN_TRACER4 L4 48067000 - 48067fff
2568 * XTI Mod 48068000 - 48068fff
2569 * XTI L4 48069000 - 48069fff
2570 * UART1 Mod 4806a000 - 4806afff
2571 * UART1 L4 4806b000 - 4806bfff
2572 * UART2 Mod 4806c000 - 4806cfff
2573 * UART2 L4 4806d000 - 4806dfff
2574 * UART3 Mod 4806e000 - 4806efff
2575 * UART3 L4 4806f000 - 4806ffff
2576 * I2C1 Mod 48070000 - 48070fff
2577 * I2C1 L4 48071000 - 48071fff
2578 * I2C2 Mod 48072000 - 48072fff
2579 * I2C2 L4 48073000 - 48073fff
2580 * McBSP1 Mod 48074000 - 48074fff
2581 * McBSP1 L4 48075000 - 48075fff
2582 * McBSP2 Mod 48076000 - 48076fff
2583 * McBSP2 L4 48077000 - 48077fff
2584 * GPTIMER3 Mod 48078000 - 48078fff
2585 * GPTIMER3 L4 48079000 - 48079fff
2586 * GPTIMER4 Mod 4807a000 - 4807afff
2587 * GPTIMER4 L4 4807b000 - 4807bfff
2588 * GPTIMER5 Mod 4807c000 - 4807cfff
2589 * GPTIMER5 L4 4807d000 - 4807dfff
2590 * GPTIMER6 Mod 4807e000 - 4807efff
2591 * GPTIMER6 L4 4807f000 - 4807ffff
2592 * GPTIMER7 Mod 48080000 - 48080fff
2593 * GPTIMER7 L4 48081000 - 48081fff
2594 * GPTIMER8 Mod 48082000 - 48082fff
2595 * GPTIMER8 L4 48083000 - 48083fff
2596 * GPTIMER9 Mod 48084000 - 48084fff
2597 * GPTIMER9 L4 48085000 - 48085fff
2598 * GPTIMER10 Mod 48086000 - 48086fff
2599 * GPTIMER10 L4 48087000 - 48087fff
2600 * GPTIMER11 Mod 48088000 - 48088fff
2601 * GPTIMER11 L4 48089000 - 48089fff
2602 * GPTIMER12 Mod 4808a000 - 4808afff
2603 * GPTIMER12 L4 4808b000 - 4808bfff
2604 * EAC Mod 48090000 - 48090fff
2605 * EAC L4 48091000 - 48091fff
2606 * FAC Mod 48092000 - 48092fff
2607 * FAC L4 48093000 - 48093fff
2608 * MAILBOX Mod 48094000 - 48094fff
2609 * MAILBOX L4 48095000 - 48095fff
2610 * SPI1 Mod 48098000 - 48098fff
2611 * SPI1 L4 48099000 - 48099fff
2612 * SPI2 Mod 4809a000 - 4809afff
2613 * SPI2 L4 4809b000 - 4809bfff
2614 * MMC/SDIO Mod 4809c000 - 4809cfff
2615 * MMC/SDIO L4 4809d000 - 4809dfff
2616 * MS_PRO Mod 4809e000 - 4809efff
2617 * MS_PRO L4 4809f000 - 4809ffff
2618 * RNG Mod 480a0000 - 480a0fff
2619 * RNG L4 480a1000 - 480a1fff
2620 * DES3DES Mod 480a2000 - 480a2fff
2621 * DES3DES L4 480a3000 - 480a3fff
2622 * SHA1MD5 Mod 480a4000 - 480a4fff
2623 * SHA1MD5 L4 480a5000 - 480a5fff
2624 * AES Mod 480a6000 - 480a6fff
2625 * AES L4 480a7000 - 480a7fff
2626 * PKA Mod 480a8000 - 480a9fff
2627 * PKA L4 480aa000 - 480aafff
2628 * MG Mod 480b0000 - 480b0fff
2629 * MG L4 480b1000 - 480b1fff
2630 * HDQ/1-wire Mod 480b2000 - 480b2fff
2631 * HDQ/1-wire L4 480b3000 - 480b3fff
2632 * MPU interrupt 480fe000 - 480fefff
2633 * STI channel base 54000000 - 5400ffff
2634 * IVA RAM 5c000000 - 5c01ffff
2635 * IVA ROM 5c020000 - 5c027fff
2636 * IMG_BUF_A 5c040000 - 5c040fff
2637 * IMG_BUF_B 5c042000 - 5c042fff
2638 * VLCDS 5c048000 - 5c0487ff
2639 * IMX_COEF 5c049000 - 5c04afff
2640 * IMX_CMD 5c051000 - 5c051fff
2641 * VLCDQ 5c053000 - 5c0533ff
2642 * VLCDH 5c054000 - 5c054fff
2643 * SEQ_CMD 5c055000 - 5c055fff
2644 * IMX_REG 5c056000 - 5c0560ff
2645 * VLCD_REG 5c056100 - 5c0561ff
2646 * SEQ_REG 5c056200 - 5c0562ff
2647 * IMG_BUF_REG 5c056300 - 5c0563ff
2648 * SEQIRQ_REG 5c056400 - 5c0564ff
2649 * OCP_REG 5c060000 - 5c060fff
2650 * SYSC_REG 5c070000 - 5c070fff
2651 * MMU_REG 5d000000 - 5d000fff
2652 * sDMA R 68000400 - 680005ff
2653 * sDMA W 68000600 - 680007ff
2654 * Display Control 68000800 - 680009ff
2655 * DSP subsystem 68000a00 - 68000bff
2656 * MPU subsystem 68000c00 - 68000dff
2657 * IVA subsystem 68001000 - 680011ff
2658 * USB 68001200 - 680013ff
2659 * Camera 68001400 - 680015ff
2660 * VLYNQ (firewall) 68001800 - 68001bff
2661 * VLYNQ 68001e00 - 68001fff
2662 * SSI 68002000 - 680021ff
2663 * L4 68002400 - 680025ff
2664 * DSP (firewall) 68002800 - 68002bff
2665 * DSP subsystem 68002e00 - 68002fff
2666 * IVA (firewall) 68003000 - 680033ff
2667 * IVA 68003600 - 680037ff
2668 * GFX 68003a00 - 68003bff
2669 * CMDWR emulation 68003c00 - 68003dff
2670 * SMS 68004000 - 680041ff
2671 * OCM 68004200 - 680043ff
2672 * GPMC 68004400 - 680045ff
2673 * RAM (firewall) 68005000 - 680053ff
2674 * RAM (err login) 68005400 - 680057ff
2675 * ROM (firewall) 68005800 - 68005bff
2676 * ROM (err login) 68005c00 - 68005fff
2677 * GPMC (firewall) 68006000 - 680063ff
2678 * GPMC (err login) 68006400 - 680067ff
2679 * SMS (err login) 68006c00 - 68006fff
2680 * SMS registers 68008000 - 68008fff
2681 * SDRC registers 68009000 - 68009fff
2682 * GPMC registers 6800a000 6800afff
2683 */
2684
2685 qemu_register_reset(omap2_mpu_reset, s);
2686
2687 return s;
2688 }
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