hw/arm/pxa2xx_gpio.c

   1 /*
   2  * Intel XScale PXA255/270 GPIO controller emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "cpu.h"
  12 #include "hw/hw.h"
  13 #include "hw/sysbus.h"
  14 #include "hw/arm/pxa.h"
  15
  16 #define PXA2XX_GPIO_BANKS       4
  17
  18 #define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
  19 #define PXA2XX_GPIO(obj) \
  20     OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)
  21
  22 typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
  23 struct PXA2xxGPIOInfo {
  24     /*< private >*/
  25     SysBusDevice parent_obj;
  26     /*< public >*/
  27
  28     MemoryRegion iomem;
  29     qemu_irq irq0, irq1, irqX;
  30     int lines;
  31     int ncpu;
  32     ARMCPU *cpu;
  33
  34     /* XXX: GNU C vectors are more suitable */
  35     uint32_t ilevel[PXA2XX_GPIO_BANKS];
  36     uint32_t olevel[PXA2XX_GPIO_BANKS];
  37     uint32_t dir[PXA2XX_GPIO_BANKS];
  38     uint32_t rising[PXA2XX_GPIO_BANKS];
  39     uint32_t falling[PXA2XX_GPIO_BANKS];
  40     uint32_t status[PXA2XX_GPIO_BANKS];
  41     uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
  42
  43     uint32_t prev_level[PXA2XX_GPIO_BANKS];
  44     qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
  45     qemu_irq read_notify;
  46 };
  47
  48 static struct {
  49     enum {
  50         GPIO_NONE,
  51         GPLR,
  52         GPSR,
  53         GPCR,
  54         GPDR,
  55         GRER,
  56         GFER,
  57         GEDR,
  58         GAFR_L,
  59         GAFR_U,
  60     } reg;
  61     int bank;
  62 } pxa2xx_gpio_regs[0x200] = {
  63     [0 ... 0x1ff] = { GPIO_NONE, 0 },
  64 #define PXA2XX_REG(reg, a0, a1, a2, a3) \
  65     [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
  66
  67     PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
  68     PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
  69     PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
  70     PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
  71     PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
  72     PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
  73     PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
  74     PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
  75     PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
  76 };
  77
  78 static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
  79 {
  80     if (s->status[0] & (1 << 0))
  81         qemu_irq_raise(s->irq0);
  82     else
  83         qemu_irq_lower(s->irq0);
  84
  85     if (s->status[0] & (1 << 1))
  86         qemu_irq_raise(s->irq1);
  87     else
  88         qemu_irq_lower(s->irq1);
  89
  90     if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
  91         qemu_irq_raise(s->irqX);
  92     else
  93         qemu_irq_lower(s->irqX);
  94 }
  95
  96 /* Bitmap of pins used as standby and sleep wake-up sources.  */
  97 static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
  98     0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
  99 };
 100
 101 static void pxa2xx_gpio_set(void *opaque, int line, int level)
 102 {
 103     PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
 104     CPUState *cpu = CPU(s->cpu);
 105     int bank;
 106     uint32_t mask;
 107
 108     if (line >= s->lines) {
 109         printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
 110         return;
 111     }
 112
 113     bank = line >> 5;
 114     mask = 1U << (line & 31);
 115
 116     if (level) {
 117         s->status[bank] |= s->rising[bank] & mask &
 118                 ~s->ilevel[bank] & ~s->dir[bank];
 119         s->ilevel[bank] |= mask;
 120     } else {
 121         s->status[bank] |= s->falling[bank] & mask &
 122                 s->ilevel[bank] & ~s->dir[bank];
 123         s->ilevel[bank] &= ~mask;
 124     }
 125
 126     if (s->status[bank] & mask)
 127         pxa2xx_gpio_irq_update(s);
 128
 129     /* Wake-up GPIOs */
 130     if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
 131         cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
 132     }
 133 }
 134
 135 static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
 136     uint32_t level, diff;
 137     int i, bit, line;
 138     for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
 139         level = s->olevel[i] & s->dir[i];
 140
 141         for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
 142             bit = ctz32(diff);
 143             line = bit + 32 * i;
 144             qemu_set_irq(s->handler[line], (level >> bit) & 1);
 145         }
 146
 147         s->prev_level[i] = level;
 148     }
 149 }
 150
 151 static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
 152                                  unsigned size)
 153 {
 154     PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
 155     uint32_t ret;
 156     int bank;
 157     if (offset >= 0x200)
 158         return 0;
 159
 160     bank = pxa2xx_gpio_regs[offset].bank;
 161     switch (pxa2xx_gpio_regs[offset].reg) {
 162     case GPDR:          /* GPIO Pin-Direction registers */
 163         return s->dir[bank];
 164
 165     case GPSR:          /* GPIO Pin-Output Set registers */
 166         qemu_log_mask(LOG_GUEST_ERROR,
 167                       "pxa2xx GPIO: read from write only register GPSR\n");
 168         return 0;
 169
 170     case GPCR:          /* GPIO Pin-Output Clear registers */
 171         qemu_log_mask(LOG_GUEST_ERROR,
 172                       "pxa2xx GPIO: read from write only register GPCR\n");
 173         return 0;
 174
 175     case GRER:          /* GPIO Rising-Edge Detect Enable registers */
 176         return s->rising[bank];
 177
 178     case GFER:          /* GPIO Falling-Edge Detect Enable registers */
 179         return s->falling[bank];
 180
 181     case GAFR_L:        /* GPIO Alternate Function registers */
 182         return s->gafr[bank * 2];
 183
 184     case GAFR_U:        /* GPIO Alternate Function registers */
 185         return s->gafr[bank * 2 + 1];
 186
 187     case GPLR:          /* GPIO Pin-Level registers */
 188         ret = (s->olevel[bank] & s->dir[bank]) |
 189                 (s->ilevel[bank] & ~s->dir[bank]);
 190         qemu_irq_raise(s->read_notify);
 191         return ret;
 192
 193     case GEDR:          /* GPIO Edge Detect Status registers */
 194         return s->status[bank];
 195
 196     default:
 197         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 198     }
 199
 200     return 0;
 201 }
 202
 203 static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
 204                               uint64_t value, unsigned size)
 205 {
 206     PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
 207     int bank;
 208     if (offset >= 0x200)
 209         return;
 210
 211     bank = pxa2xx_gpio_regs[offset].bank;
 212     switch (pxa2xx_gpio_regs[offset].reg) {
 213     case GPDR:          /* GPIO Pin-Direction registers */
 214         s->dir[bank] = value;
 215         pxa2xx_gpio_handler_update(s);
 216         break;
 217
 218     case GPSR:          /* GPIO Pin-Output Set registers */
 219         s->olevel[bank] |= value;
 220         pxa2xx_gpio_handler_update(s);
 221         break;
 222
 223     case GPCR:          /* GPIO Pin-Output Clear registers */
 224         s->olevel[bank] &= ~value;
 225         pxa2xx_gpio_handler_update(s);
 226         break;
 227
 228     case GRER:          /* GPIO Rising-Edge Detect Enable registers */
 229         s->rising[bank] = value;
 230         break;
 231
 232     case GFER:          /* GPIO Falling-Edge Detect Enable registers */
 233         s->falling[bank] = value;
 234         break;
 235
 236     case GAFR_L:        /* GPIO Alternate Function registers */
 237         s->gafr[bank * 2] = value;
 238         break;
 239
 240     case GAFR_U:        /* GPIO Alternate Function registers */
 241         s->gafr[bank * 2 + 1] = value;
 242         break;
 243
 244     case GEDR:          /* GPIO Edge Detect Status registers */
 245         s->status[bank] &= ~value;
 246         pxa2xx_gpio_irq_update(s);
 247         break;
 248
 249     default:
 250         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 251     }
 252 }
 253
 254 static const MemoryRegionOps pxa_gpio_ops = {
 255     .read = pxa2xx_gpio_read,
 256     .write = pxa2xx_gpio_write,
 257     .endianness = DEVICE_NATIVE_ENDIAN,
 258 };
 259
 260 DeviceState *pxa2xx_gpio_init(hwaddr base,
 261                               ARMCPU *cpu, DeviceState *pic, int lines)
 262 {
 263     CPUState *cs = CPU(cpu);
 264     DeviceState *dev;
 265
 266     dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
 267     qdev_prop_set_int32(dev, "lines", lines);
 268     qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
 269     qdev_init_nofail(dev);
 270
 271     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 272     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
 273                     qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
 274     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
 275                     qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
 276     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
 277                     qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
 278
 279     return dev;
 280 }
 281
 282 static int pxa2xx_gpio_initfn(SysBusDevice *sbd)
 283 {
 284     DeviceState *dev = DEVICE(sbd);
 285     PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
 286
 287     s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
 288
 289     qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
 290     qdev_init_gpio_out(dev, s->handler, s->lines);
 291
 292     memory_region_init_io(&s->iomem, OBJECT(s), &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
 293     sysbus_init_mmio(sbd, &s->iomem);
 294     sysbus_init_irq(sbd, &s->irq0);
 295     sysbus_init_irq(sbd, &s->irq1);
 296     sysbus_init_irq(sbd, &s->irqX);
 297
 298     return 0;
 299 }
 300
 301 /*
 302  * Registers a callback to notify on GPLR reads.  This normally
 303  * shouldn't be needed but it is used for the hack on Spitz machines.
 304  */
 305 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
 306 {
 307     PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
 308
 309     s->read_notify = handler;
 310 }
 311
 312 static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
 313     .name = "pxa2xx-gpio",
 314     .version_id = 1,
 315     .minimum_version_id = 1,
 316     .fields = (VMStateField[]) {
 317         VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 318         VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 319         VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 320         VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 321         VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 322         VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 323         VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
 324         VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 325         VMSTATE_END_OF_LIST(),
 326     },
 327 };
 328
 329 static Property pxa2xx_gpio_properties[] = {
 330     DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
 331     DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
 332     DEFINE_PROP_END_OF_LIST(),
 333 };
 334
 335 static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
 336 {
 337     DeviceClass *dc = DEVICE_CLASS(klass);
 338     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 339
 340     k->init = pxa2xx_gpio_initfn;
 341     dc->desc = "PXA2xx GPIO controller";
 342     dc->props = pxa2xx_gpio_properties;
 343     dc->vmsd = &vmstate_pxa2xx_gpio_regs;
 344 }
 345
 346 static const TypeInfo pxa2xx_gpio_info = {
 347     .name          = TYPE_PXA2XX_GPIO,
 348     .parent        = TYPE_SYS_BUS_DEVICE,
 349     .instance_size = sizeof(PXA2xxGPIOInfo),
 350     .class_init    = pxa2xx_gpio_class_init,
 351 };
 352
 353 static void pxa2xx_gpio_register_types(void)
 354 {
 355     type_register_static(&pxa2xx_gpio_info);
 356 }
 357
 358 type_init(pxa2xx_gpio_register_types)