hw/arm/pxa2xx_pic.c

   1 /*
   2  * Intel XScale PXA Programmable Interrupt Controller.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Copyright (c) 2006 Thorsten Zitterell
   6  * Written by Andrzej Zaborowski <balrog@zabor.org>
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "hw/hw.h"
  12 #include "hw/pxa.h"
  13 #include "hw/sysbus.h"
  14
  15 #define ICIP    0x00    /* Interrupt Controller IRQ Pending register */
  16 #define ICMR    0x04    /* Interrupt Controller Mask register */
  17 #define ICLR    0x08    /* Interrupt Controller Level register */
  18 #define ICFP    0x0c    /* Interrupt Controller FIQ Pending register */
  19 #define ICPR    0x10    /* Interrupt Controller Pending register */
  20 #define ICCR    0x14    /* Interrupt Controller Control register */
  21 #define ICHP    0x18    /* Interrupt Controller Highest Priority register */
  22 #define IPR0    0x1c    /* Interrupt Controller Priority register 0 */
  23 #define IPR31   0x98    /* Interrupt Controller Priority register 31 */
  24 #define ICIP2   0x9c    /* Interrupt Controller IRQ Pending register 2 */
  25 #define ICMR2   0xa0    /* Interrupt Controller Mask register 2 */
  26 #define ICLR2   0xa4    /* Interrupt Controller Level register 2 */
  27 #define ICFP2   0xa8    /* Interrupt Controller FIQ Pending register 2 */
  28 #define ICPR2   0xac    /* Interrupt Controller Pending register 2 */
  29 #define IPR32   0xb0    /* Interrupt Controller Priority register 32 */
  30 #define IPR39   0xcc    /* Interrupt Controller Priority register 39 */
  31
  32 #define PXA2XX_PIC_SRCS 40
  33
  34 typedef struct {
  35     SysBusDevice busdev;
  36     MemoryRegion iomem;
  37     ARMCPU *cpu;
  38     uint32_t int_enabled[2];
  39     uint32_t int_pending[2];
  40     uint32_t is_fiq[2];
  41     uint32_t int_idle;
  42     uint32_t priority[PXA2XX_PIC_SRCS];
  43 } PXA2xxPICState;
  44
  45 static void pxa2xx_pic_update(void *opaque)
  46 {
  47     uint32_t mask[2];
  48     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
  49     CPUState *cpu = CPU(s->cpu);
  50
  51     if (cpu->halted) {
  52         mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
  53         mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
  54         if (mask[0] || mask[1]) {
  55             cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
  56         }
  57     }
  58
  59     mask[0] = s->int_pending[0] & s->int_enabled[0];
  60     mask[1] = s->int_pending[1] & s->int_enabled[1];
  61
  62     if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
  63         cpu_interrupt(cpu, CPU_INTERRUPT_FIQ);
  64     } else {
  65         cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
  66     }
  67
  68     if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
  69         cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
  70     } else {
  71         cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
  72     }
  73 }
  74
  75 /* Note: Here level means state of the signal on a pin, not
  76  * IRQ/FIQ distinction as in PXA Developer Manual.  */
  77 static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
  78 {
  79     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
  80     int int_set = (irq >= 32);
  81     irq &= 31;
  82
  83     if (level)
  84         s->int_pending[int_set] |= 1 << irq;
  85     else
  86         s->int_pending[int_set] &= ~(1 << irq);
  87
  88     pxa2xx_pic_update(opaque);
  89 }
  90
  91 static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
  92     int i, int_set, irq;
  93     uint32_t bit, mask[2];
  94     uint32_t ichp = 0x003f003f; /* Both IDs invalid */
  95
  96     mask[0] = s->int_pending[0] & s->int_enabled[0];
  97     mask[1] = s->int_pending[1] & s->int_enabled[1];
  98
  99     for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
 100         irq = s->priority[i] & 0x3f;
 101         if ((s->priority[i] & (1 << 31)) && irq < PXA2XX_PIC_SRCS) {
 102             /* Source peripheral ID is valid.  */
 103             bit = 1 << (irq & 31);
 104             int_set = (irq >= 32);
 105
 106             if (mask[int_set] & bit & s->is_fiq[int_set]) {
 107                 /* FIQ asserted */
 108                 ichp &= 0xffff0000;
 109                 ichp |= (1 << 15) | irq;
 110             }
 111
 112             if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
 113                 /* IRQ asserted */
 114                 ichp &= 0x0000ffff;
 115                 ichp |= (1 << 31) | (irq << 16);
 116             }
 117         }
 118     }
 119
 120     return ichp;
 121 }
 122
 123 static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
 124                                     unsigned size)
 125 {
 126     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
 127
 128     switch (offset) {
 129     case ICIP:  /* IRQ Pending register */
 130         return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
 131     case ICIP2: /* IRQ Pending register 2 */
 132         return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
 133     case ICMR:  /* Mask register */
 134         return s->int_enabled[0];
 135     case ICMR2: /* Mask register 2 */
 136         return s->int_enabled[1];
 137     case ICLR:  /* Level register */
 138         return s->is_fiq[0];
 139     case ICLR2: /* Level register 2 */
 140         return s->is_fiq[1];
 141     case ICCR:  /* Idle mask */
 142         return (s->int_idle == 0);
 143     case ICFP:  /* FIQ Pending register */
 144         return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
 145     case ICFP2: /* FIQ Pending register 2 */
 146         return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
 147     case ICPR:  /* Pending register */
 148         return s->int_pending[0];
 149     case ICPR2: /* Pending register 2 */
 150         return s->int_pending[1];
 151     case IPR0  ... IPR31:
 152         return s->priority[0  + ((offset - IPR0 ) >> 2)];
 153     case IPR32 ... IPR39:
 154         return s->priority[32 + ((offset - IPR32) >> 2)];
 155     case ICHP:  /* Highest Priority register */
 156         return pxa2xx_pic_highest(s);
 157     default:
 158         printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
 159         return 0;
 160     }
 161 }
 162
 163 static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
 164                                  uint64_t value, unsigned size)
 165 {
 166     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
 167
 168     switch (offset) {
 169     case ICMR:  /* Mask register */
 170         s->int_enabled[0] = value;
 171         break;
 172     case ICMR2: /* Mask register 2 */
 173         s->int_enabled[1] = value;
 174         break;
 175     case ICLR:  /* Level register */
 176         s->is_fiq[0] = value;
 177         break;
 178     case ICLR2: /* Level register 2 */
 179         s->is_fiq[1] = value;
 180         break;
 181     case ICCR:  /* Idle mask */
 182         s->int_idle = (value & 1) ? 0 : ~0;
 183         break;
 184     case IPR0  ... IPR31:
 185         s->priority[0  + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
 186         break;
 187     case IPR32 ... IPR39:
 188         s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
 189         break;
 190     default:
 191         printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
 192         return;
 193     }
 194     pxa2xx_pic_update(opaque);
 195 }
 196
 197 /* Interrupt Controller Coprocessor Space Register Mapping */
 198 static const int pxa2xx_cp_reg_map[0x10] = {
 199     [0x0 ... 0xf] = -1,
 200     [0x0] = ICIP,
 201     [0x1] = ICMR,
 202     [0x2] = ICLR,
 203     [0x3] = ICFP,
 204     [0x4] = ICPR,
 205     [0x5] = ICHP,
 206     [0x6] = ICIP2,
 207     [0x7] = ICMR2,
 208     [0x8] = ICLR2,
 209     [0x9] = ICFP2,
 210     [0xa] = ICPR2,
 211 };
 212
 213 static int pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri,
 214                               uint64_t *value)
 215 {
 216     int offset = pxa2xx_cp_reg_map[ri->crn];
 217     *value = pxa2xx_pic_mem_read(ri->opaque, offset, 4);
 218     return 0;
 219 }
 220
 221 static int pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
 222                                uint64_t value)
 223 {
 224     int offset = pxa2xx_cp_reg_map[ri->crn];
 225     pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
 226     return 0;
 227 }
 228
 229 #define REGINFO_FOR_PIC_CP(NAME, CRN) \
 230     { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
 231       .access = PL1_RW, \
 232       .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
 233
 234 static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
 235     REGINFO_FOR_PIC_CP("ICIP", 0),
 236     REGINFO_FOR_PIC_CP("ICMR", 1),
 237     REGINFO_FOR_PIC_CP("ICLR", 2),
 238     REGINFO_FOR_PIC_CP("ICFP", 3),
 239     REGINFO_FOR_PIC_CP("ICPR", 4),
 240     REGINFO_FOR_PIC_CP("ICHP", 5),
 241     REGINFO_FOR_PIC_CP("ICIP2", 6),
 242     REGINFO_FOR_PIC_CP("ICMR2", 7),
 243     REGINFO_FOR_PIC_CP("ICLR2", 8),
 244     REGINFO_FOR_PIC_CP("ICFP2", 9),
 245     REGINFO_FOR_PIC_CP("ICPR2", 0xa),
 246     REGINFO_SENTINEL
 247 };
 248
 249 static const MemoryRegionOps pxa2xx_pic_ops = {
 250     .read = pxa2xx_pic_mem_read,
 251     .write = pxa2xx_pic_mem_write,
 252     .endianness = DEVICE_NATIVE_ENDIAN,
 253 };
 254
 255 static int pxa2xx_pic_post_load(void *opaque, int version_id)
 256 {
 257     pxa2xx_pic_update(opaque);
 258     return 0;
 259 }
 260
 261 DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
 262 {
 263     CPUARMState *env = &cpu->env;
 264     DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
 265     PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, SYS_BUS_DEVICE(dev));
 266
 267     s->cpu = cpu;
 268
 269     s->int_pending[0] = 0;
 270     s->int_pending[1] = 0;
 271     s->int_enabled[0] = 0;
 272     s->int_enabled[1] = 0;
 273     s->is_fiq[0] = 0;
 274     s->is_fiq[1] = 0;
 275
 276     qdev_init_nofail(dev);
 277
 278     qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
 279
 280     /* Enable IC memory-mapped registers access.  */
 281     memory_region_init_io(&s->iomem, &pxa2xx_pic_ops, s,
 282                           "pxa2xx-pic", 0x00100000);
 283     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 284     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 285
 286     /* Enable IC coprocessor access.  */
 287     define_arm_cp_regs_with_opaque(arm_env_get_cpu(env), pxa_pic_cp_reginfo, s);
 288
 289     return dev;
 290 }
 291
 292 static VMStateDescription vmstate_pxa2xx_pic_regs = {
 293     .name = "pxa2xx_pic",
 294     .version_id = 0,
 295     .minimum_version_id = 0,
 296     .minimum_version_id_old = 0,
 297     .post_load = pxa2xx_pic_post_load,
 298     .fields = (VMStateField[]) {
 299         VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
 300         VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
 301         VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
 302         VMSTATE_UINT32(int_idle, PXA2xxPICState),
 303         VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
 304         VMSTATE_END_OF_LIST(),
 305     },
 306 };
 307
 308 static int pxa2xx_pic_initfn(SysBusDevice *dev)
 309 {
 310     return 0;
 311 }
 312
 313 static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
 314 {
 315     DeviceClass *dc = DEVICE_CLASS(klass);
 316     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 317
 318     k->init = pxa2xx_pic_initfn;
 319     dc->desc = "PXA2xx PIC";
 320     dc->vmsd = &vmstate_pxa2xx_pic_regs;
 321 }
 322
 323 static const TypeInfo pxa2xx_pic_info = {
 324     .name          = "pxa2xx_pic",
 325     .parent        = TYPE_SYS_BUS_DEVICE,
 326     .instance_size = sizeof(PXA2xxPICState),
 327     .class_init    = pxa2xx_pic_class_init,
 328 };
 329
 330 static void pxa2xx_pic_register_types(void)
 331 {
 332     type_register_static(&pxa2xx_pic_info);
 333 }
 334
 335 type_init(pxa2xx_pic_register_types)