hw/arm/realview.c

   1 /*
   2  * ARM RealView Baseboard System emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "cpu.h"
  13 #include "hw/sysbus.h"
  14 #include "hw/arm/boot.h"
  15 #include "hw/arm/primecell.h"
  16 #include "hw/core/split-irq.h"
  17 #include "hw/net/lan9118.h"
  18 #include "hw/net/smc91c111.h"
  19 #include "hw/pci/pci.h"
  20 #include "hw/qdev-core.h"
  21 #include "net/net.h"
  22 #include "sysemu/sysemu.h"
  23 #include "hw/boards.h"
  24 #include "hw/i2c/i2c.h"
  25 #include "qemu/error-report.h"
  26 #include "hw/char/pl011.h"
  27 #include "hw/cpu/a9mpcore.h"
  28 #include "hw/intc/realview_gic.h"
  29 #include "hw/irq.h"
  30 #include "hw/i2c/arm_sbcon_i2c.h"
  31 #include "hw/sd/sd.h"
  32
  33 #define SMP_BOOT_ADDR 0xe0000000
  34 #define SMP_BOOTREG_ADDR 0x10000030
  35
  36 /* Board init.  */
  37
  38 static struct arm_boot_info realview_binfo = {
  39     .smp_loader_start = SMP_BOOT_ADDR,
  40     .smp_bootreg_addr = SMP_BOOTREG_ADDR,
  41 };
  42
  43 /* The following two lists must be consistent.  */
  44 enum realview_board_type {
  45     BOARD_EB,
  46     BOARD_EB_MPCORE,
  47     BOARD_PB_A8,
  48     BOARD_PBX_A9,
  49 };
  50
  51 static const int realview_board_id[] = {
  52     0x33b,
  53     0x33b,
  54     0x769,
  55     0x76d
  56 };
  57
  58 static void split_irq_from_named(DeviceState *src, const char* outname,
  59                                  qemu_irq out1, qemu_irq out2) {
  60     DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
  61
  62     qdev_prop_set_uint32(splitter, "num-lines", 2);
  63
  64     qdev_realize_and_unref(splitter, NULL, &error_fatal);
  65
  66     qdev_connect_gpio_out(splitter, 0, out1);
  67     qdev_connect_gpio_out(splitter, 1, out2);
  68     qdev_connect_gpio_out_named(src, outname, 0,
  69                                 qdev_get_gpio_in(splitter, 0));
  70 }
  71
  72 static void realview_init(MachineState *machine,
  73                           enum realview_board_type board_type)
  74 {
  75     ARMCPU *cpu = NULL;
  76     CPUARMState *env;
  77     MemoryRegion *sysmem = get_system_memory();
  78     MemoryRegion *ram_lo;
  79     MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
  80     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
  81     MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
  82     DeviceState *dev, *sysctl, *gpio2, *pl041;
  83     SysBusDevice *busdev;
  84     qemu_irq pic[64];
  85     PCIBus *pci_bus = NULL;
  86     NICInfo *nd;
  87     DriveInfo *dinfo;
  88     I2CBus *i2c;
  89     int n;
  90     unsigned int smp_cpus = machine->smp.cpus;
  91     int done_nic = 0;
  92     qemu_irq cpu_irq[4];
  93     int is_mpcore = 0;
  94     int is_pb = 0;
  95     uint32_t proc_id = 0;
  96     uint32_t sys_id;
  97     ram_addr_t low_ram_size;
  98     ram_addr_t ram_size = machine->ram_size;
  99     hwaddr periphbase = 0;
 100
 101     switch (board_type) {
 102     case BOARD_EB:
 103         break;
 104     case BOARD_EB_MPCORE:
 105         is_mpcore = 1;
 106         periphbase = 0x10100000;
 107         break;
 108     case BOARD_PB_A8:
 109         is_pb = 1;
 110         break;
 111     case BOARD_PBX_A9:
 112         is_mpcore = 1;
 113         is_pb = 1;
 114         periphbase = 0x1f000000;
 115         break;
 116     }
 117
 118     for (n = 0; n < smp_cpus; n++) {
 119         Object *cpuobj = object_new(machine->cpu_type);
 120
 121         /* By default A9,A15 and ARM1176 CPUs have EL3 enabled.  This board
 122          * does not currently support EL3 so the CPU EL3 property is disabled
 123          * before realization.
 124          */
 125         if (object_property_find(cpuobj, "has_el3")) {
 126             object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
 127         }
 128
 129         if (is_pb && is_mpcore) {
 130             object_property_set_int(cpuobj, "reset-cbar", periphbase,
 131                                     &error_fatal);
 132         }
 133
 134         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 135
 136         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
 137     }
 138     cpu = ARM_CPU(first_cpu);
 139     env = &cpu->env;
 140     if (arm_feature(env, ARM_FEATURE_V7)) {
 141         if (is_mpcore) {
 142             proc_id = 0x0c000000;
 143         } else {
 144             proc_id = 0x0e000000;
 145         }
 146     } else if (arm_feature(env, ARM_FEATURE_V6K)) {
 147         proc_id = 0x06000000;
 148     } else if (arm_feature(env, ARM_FEATURE_V6)) {
 149         proc_id = 0x04000000;
 150     } else {
 151         proc_id = 0x02000000;
 152     }
 153
 154     if (is_pb && ram_size > 0x20000000) {
 155         /* Core tile RAM.  */
 156         ram_lo = g_new(MemoryRegion, 1);
 157         low_ram_size = ram_size - 0x20000000;
 158         ram_size = 0x20000000;
 159         memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size,
 160                                &error_fatal);
 161         memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
 162     }
 163
 164     memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size,
 165                            &error_fatal);
 166     low_ram_size = ram_size;
 167     if (low_ram_size > 0x10000000)
 168       low_ram_size = 0x10000000;
 169     /* SDRAM at address zero.  */
 170     memory_region_init_alias(ram_alias, NULL, "realview.alias",
 171                              ram_hi, 0, low_ram_size);
 172     memory_region_add_subregion(sysmem, 0, ram_alias);
 173     if (is_pb) {
 174         /* And again at a high address.  */
 175         memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
 176     } else {
 177         ram_size = low_ram_size;
 178     }
 179
 180     sys_id = is_pb ? 0x01780500 : 0xc1400400;
 181     sysctl = qdev_new("realview_sysctl");
 182     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 183     qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
 184     sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
 185     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
 186
 187     if (is_mpcore) {
 188         dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
 189         qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 190         busdev = SYS_BUS_DEVICE(dev);
 191         sysbus_realize_and_unref(busdev, &error_fatal);
 192         sysbus_mmio_map(busdev, 0, periphbase);
 193         for (n = 0; n < smp_cpus; n++) {
 194             sysbus_connect_irq(busdev, n, cpu_irq[n]);
 195         }
 196         sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL);
 197         /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */
 198         realview_binfo.gic_cpu_if_addr = periphbase + 0x100;
 199     } else {
 200         uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
 201         /* For now just create the nIRQ GIC, and ignore the others.  */
 202         dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]);
 203     }
 204     for (n = 0; n < 64; n++) {
 205         pic[n] = qdev_get_gpio_in(dev, n);
 206     }
 207
 208     pl041 = qdev_new("pl041");
 209     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 210     sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
 211     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
 212     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]);
 213
 214     sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
 215     sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
 216
 217     pl011_create(0x10009000, pic[12], serial_hd(0));
 218     pl011_create(0x1000a000, pic[13], serial_hd(1));
 219     pl011_create(0x1000b000, pic[14], serial_hd(2));
 220     pl011_create(0x1000c000, pic[15], serial_hd(3));
 221
 222     /* DMA controller is optional, apparently.  */
 223     dev = qdev_new("pl081");
 224     object_property_set_link(OBJECT(dev), "downstream", OBJECT(sysmem),
 225                              &error_fatal);
 226     busdev = SYS_BUS_DEVICE(dev);
 227     sysbus_realize_and_unref(busdev, &error_fatal);
 228     sysbus_mmio_map(busdev, 0, 0x10030000);
 229     sysbus_connect_irq(busdev, 0, pic[24]);
 230
 231     sysbus_create_simple("sp804", 0x10011000, pic[4]);
 232     sysbus_create_simple("sp804", 0x10012000, pic[5]);
 233
 234     sysbus_create_simple("pl061", 0x10013000, pic[6]);
 235     sysbus_create_simple("pl061", 0x10014000, pic[7]);
 236     gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);
 237
 238     sysbus_create_simple("pl111", 0x10020000, pic[23]);
 239
 240     dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
 241     /* Wire up MMC card detect and read-only signals. These have
 242      * to go to both the PL061 GPIO and the sysctl register.
 243      * Note that the PL181 orders these lines (readonly,inserted)
 244      * and the PL061 has them the other way about. Also the card
 245      * detect line is inverted.
 246      */
 247     split_irq_from_named(dev, "card-read-only",
 248                    qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
 249                    qdev_get_gpio_in(gpio2, 1));
 250
 251     split_irq_from_named(dev, "card-inserted",
 252                    qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
 253                    qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
 254
 255     dinfo = drive_get(IF_SD, 0, 0);
 256     if (dinfo) {
 257         DeviceState *card;
 258
 259         card = qdev_new(TYPE_SD_CARD);
 260         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 261                                 &error_fatal);
 262         qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
 263                                &error_fatal);
 264     }
 265
 266     sysbus_create_simple("pl031", 0x10017000, pic[10]);
 267
 268     if (!is_pb) {
 269         dev = qdev_new("realview_pci");
 270         busdev = SYS_BUS_DEVICE(dev);
 271         sysbus_realize_and_unref(busdev, &error_fatal);
 272         sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */
 273         sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */
 274         sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */
 275         sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */
 276         sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */
 277         sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */
 278         sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */
 279         sysbus_connect_irq(busdev, 0, pic[48]);
 280         sysbus_connect_irq(busdev, 1, pic[49]);
 281         sysbus_connect_irq(busdev, 2, pic[50]);
 282         sysbus_connect_irq(busdev, 3, pic[51]);
 283         pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 284         if (machine_usb(machine)) {
 285             pci_create_simple(pci_bus, -1, "pci-ohci");
 286         }
 287         n = drive_get_max_bus(IF_SCSI);
 288         while (n >= 0) {
 289             dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a"));
 290             lsi53c8xx_handle_legacy_cmdline(dev);
 291             n--;
 292         }
 293     }
 294     for(n = 0; n < nb_nics; n++) {
 295         nd = &nd_table[n];
 296
 297         if (!done_nic && (!nd->model ||
 298                     strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
 299             if (is_pb) {
 300                 lan9118_init(nd, 0x4e000000, pic[28]);
 301             } else {
 302                 smc91c111_init(nd, 0x4e000000, pic[28]);
 303             }
 304             done_nic = 1;
 305         } else {
 306             if (pci_bus) {
 307                 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
 308             }
 309         }
 310     }
 311
 312     dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL);
 313     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 314     i2c_slave_create_simple(i2c, "ds1338", 0x68);
 315
 316     /* Memory map for RealView Emulation Baseboard:  */
 317     /* 0x10000000 System registers.  */
 318     /*  0x10001000 System controller.  */
 319     /* 0x10002000 Two-Wire Serial Bus.  */
 320     /* 0x10003000 Reserved.  */
 321     /*  0x10004000 AACI.  */
 322     /*  0x10005000 MCI.  */
 323     /* 0x10006000 KMI0.  */
 324     /* 0x10007000 KMI1.  */
 325     /*  0x10008000 Character LCD. (EB) */
 326     /* 0x10009000 UART0.  */
 327     /* 0x1000a000 UART1.  */
 328     /* 0x1000b000 UART2.  */
 329     /* 0x1000c000 UART3.  */
 330     /*  0x1000d000 SSPI.  */
 331     /*  0x1000e000 SCI.  */
 332     /* 0x1000f000 Reserved.  */
 333     /*  0x10010000 Watchdog.  */
 334     /* 0x10011000 Timer 0+1.  */
 335     /* 0x10012000 Timer 2+3.  */
 336     /*  0x10013000 GPIO 0.  */
 337     /*  0x10014000 GPIO 1.  */
 338     /*  0x10015000 GPIO 2.  */
 339     /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
 340     /* 0x10017000 RTC.  */
 341     /*  0x10018000 DMC.  */
 342     /*  0x10019000 PCI controller config.  */
 343     /*  0x10020000 CLCD.  */
 344     /* 0x10030000 DMA Controller.  */
 345     /* 0x10040000 GIC1. (EB) */
 346     /*  0x10050000 GIC2. (EB) */
 347     /*  0x10060000 GIC3. (EB) */
 348     /*  0x10070000 GIC4. (EB) */
 349     /*  0x10080000 SMC.  */
 350     /* 0x1e000000 GIC1. (PB) */
 351     /*  0x1e001000 GIC2. (PB) */
 352     /*  0x1e002000 GIC3. (PB) */
 353     /*  0x1e003000 GIC4. (PB) */
 354     /*  0x40000000 NOR flash.  */
 355     /*  0x44000000 DoC flash.  */
 356     /*  0x48000000 SRAM.  */
 357     /*  0x4c000000 Configuration flash.  */
 358     /* 0x4e000000 Ethernet.  */
 359     /*  0x4f000000 USB.  */
 360     /*  0x50000000 PISMO.  */
 361     /*  0x54000000 PISMO.  */
 362     /*  0x58000000 PISMO.  */
 363     /*  0x5c000000 PISMO.  */
 364     /* 0x60000000 PCI.  */
 365     /* 0x60000000 PCI Self Config.  */
 366     /* 0x61000000 PCI Config.  */
 367     /* 0x62000000 PCI IO.  */
 368     /* 0x63000000 PCI mem 0.  */
 369     /* 0x64000000 PCI mem 1.  */
 370     /* 0x68000000 PCI mem 2.  */
 371
 372     /* ??? Hack to map an additional page of ram for the secondary CPU
 373        startup code.  I guess this works on real hardware because the
 374        BootROM happens to be in ROM/flash or in memory that isn't clobbered
 375        until after Linux boots the secondary CPUs.  */
 376     memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000,
 377                            &error_fatal);
 378     memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
 379
 380     realview_binfo.ram_size = ram_size;
 381     realview_binfo.board_id = realview_board_id[board_type];
 382     realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
 383     arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo);
 384 }
 385
 386 static void realview_eb_init(MachineState *machine)
 387 {
 388     realview_init(machine, BOARD_EB);
 389 }
 390
 391 static void realview_eb_mpcore_init(MachineState *machine)
 392 {
 393     realview_init(machine, BOARD_EB_MPCORE);
 394 }
 395
 396 static void realview_pb_a8_init(MachineState *machine)
 397 {
 398     realview_init(machine, BOARD_PB_A8);
 399 }
 400
 401 static void realview_pbx_a9_init(MachineState *machine)
 402 {
 403     realview_init(machine, BOARD_PBX_A9);
 404 }
 405
 406 static void realview_eb_class_init(ObjectClass *oc, void *data)
 407 {
 408     MachineClass *mc = MACHINE_CLASS(oc);
 409
 410     mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)";
 411     mc->init = realview_eb_init;
 412     mc->block_default_type = IF_SCSI;
 413     mc->ignore_memory_transaction_failures = true;
 414     mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
 415 }
 416
 417 static const TypeInfo realview_eb_type = {
 418     .name = MACHINE_TYPE_NAME("realview-eb"),
 419     .parent = TYPE_MACHINE,
 420     .class_init = realview_eb_class_init,
 421 };
 422
 423 static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)
 424 {
 425     MachineClass *mc = MACHINE_CLASS(oc);
 426
 427     mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)";
 428     mc->init = realview_eb_mpcore_init;
 429     mc->block_default_type = IF_SCSI;
 430     mc->max_cpus = 4;
 431     mc->ignore_memory_transaction_failures = true;
 432     mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore");
 433 }
 434
 435 static const TypeInfo realview_eb_mpcore_type = {
 436     .name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
 437     .parent = TYPE_MACHINE,
 438     .class_init = realview_eb_mpcore_class_init,
 439 };
 440
 441 static void realview_pb_a8_class_init(ObjectClass *oc, void *data)
 442 {
 443     MachineClass *mc = MACHINE_CLASS(oc);
 444
 445     mc->desc = "ARM RealView Platform Baseboard for Cortex-A8";
 446     mc->init = realview_pb_a8_init;
 447     mc->ignore_memory_transaction_failures = true;
 448     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8");
 449 }
 450
 451 static const TypeInfo realview_pb_a8_type = {
 452     .name = MACHINE_TYPE_NAME("realview-pb-a8"),
 453     .parent = TYPE_MACHINE,
 454     .class_init = realview_pb_a8_class_init,
 455 };
 456
 457 static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)
 458 {
 459     MachineClass *mc = MACHINE_CLASS(oc);
 460
 461     mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9";
 462     mc->init = realview_pbx_a9_init;
 463     mc->max_cpus = 4;
 464     mc->ignore_memory_transaction_failures = true;
 465     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 466 }
 467
 468 static const TypeInfo realview_pbx_a9_type = {
 469     .name = MACHINE_TYPE_NAME("realview-pbx-a9"),
 470     .parent = TYPE_MACHINE,
 471     .class_init = realview_pbx_a9_class_init,
 472 };
 473
 474 static void realview_machine_init(void)
 475 {
 476     type_register_static(&realview_eb_type);
 477     type_register_static(&realview_eb_mpcore_type);
 478     type_register_static(&realview_pb_a8_type);
 479     type_register_static(&realview_pbx_a9_type);
 480 }
 481
 482 type_init(realview_machine_init)