hw/arm/sbsa-ref.c

   1 /*
   2  * ARM SBSA Reference Platform emulation
   3  *
   4  * Copyright (c) 2018 Linaro Limited
   5  * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/datadir.h"
  22 #include "qapi/error.h"
  23 #include "qemu/error-report.h"
  24 #include "qemu/units.h"
  25 #include "sysemu/device_tree.h"
  26 #include "sysemu/numa.h"
  27 #include "sysemu/runstate.h"
  28 #include "sysemu/sysemu.h"
  29 #include "exec/hwaddr.h"
  30 #include "kvm_arm.h"
  31 #include "hw/arm/boot.h"
  32 #include "hw/block/flash.h"
  33 #include "hw/boards.h"
  34 #include "hw/ide/internal.h"
  35 #include "hw/ide/ahci_internal.h"
  36 #include "hw/intc/arm_gicv3_common.h"
  37 #include "hw/loader.h"
  38 #include "hw/pci-host/gpex.h"
  39 #include "hw/qdev-properties.h"
  40 #include "hw/usb.h"
  41 #include "hw/char/pl011.h"
  42 #include "hw/watchdog/sbsa_gwdt.h"
  43 #include "net/net.h"
  44 #include "qom/object.h"
  45
  46 #define RAMLIMIT_GB 8192
  47 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
  48
  49 #define NUM_IRQS        256
  50 #define NUM_SMMU_IRQS   4
  51 #define NUM_SATA_PORTS  6
  52
  53 #define VIRTUAL_PMU_IRQ        7
  54 #define ARCH_GIC_MAINT_IRQ     9
  55 #define ARCH_TIMER_VIRT_IRQ    11
  56 #define ARCH_TIMER_S_EL1_IRQ   13
  57 #define ARCH_TIMER_NS_EL1_IRQ  14
  58 #define ARCH_TIMER_NS_EL2_IRQ  10
  59
  60 enum {
  61     SBSA_FLASH,
  62     SBSA_MEM,
  63     SBSA_CPUPERIPHS,
  64     SBSA_GIC_DIST,
  65     SBSA_GIC_REDIST,
  66     SBSA_SECURE_EC,
  67     SBSA_GWDT_WS0,
  68     SBSA_GWDT_REFRESH,
  69     SBSA_GWDT_CONTROL,
  70     SBSA_SMMU,
  71     SBSA_UART,
  72     SBSA_RTC,
  73     SBSA_PCIE,
  74     SBSA_PCIE_MMIO,
  75     SBSA_PCIE_MMIO_HIGH,
  76     SBSA_PCIE_PIO,
  77     SBSA_PCIE_ECAM,
  78     SBSA_GPIO,
  79     SBSA_SECURE_UART,
  80     SBSA_SECURE_UART_MM,
  81     SBSA_SECURE_MEM,
  82     SBSA_AHCI,
  83     SBSA_EHCI,
  84 };
  85
  86 struct SBSAMachineState {
  87     MachineState parent;
  88     struct arm_boot_info bootinfo;
  89     int smp_cpus;
  90     void *fdt;
  91     int fdt_size;
  92     int psci_conduit;
  93     DeviceState *gic;
  94     PFlashCFI01 *flash[2];
  95 };
  96
  97 #define TYPE_SBSA_MACHINE   MACHINE_TYPE_NAME("sbsa-ref")
  98 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE)
  99
 100 static const MemMapEntry sbsa_ref_memmap[] = {
 101     /* 512M boot ROM */
 102     [SBSA_FLASH] =              {          0, 0x20000000 },
 103     /* 512M secure memory */
 104     [SBSA_SECURE_MEM] =         { 0x20000000, 0x20000000 },
 105     /* Space reserved for CPU peripheral devices */
 106     [SBSA_CPUPERIPHS] =         { 0x40000000, 0x00040000 },
 107     [SBSA_GIC_DIST] =           { 0x40060000, 0x00010000 },
 108     [SBSA_GIC_REDIST] =         { 0x40080000, 0x04000000 },
 109     [SBSA_SECURE_EC] =          { 0x50000000, 0x00001000 },
 110     [SBSA_GWDT_REFRESH] =       { 0x50010000, 0x00001000 },
 111     [SBSA_GWDT_CONTROL] =       { 0x50011000, 0x00001000 },
 112     [SBSA_UART] =               { 0x60000000, 0x00001000 },
 113     [SBSA_RTC] =                { 0x60010000, 0x00001000 },
 114     [SBSA_GPIO] =               { 0x60020000, 0x00001000 },
 115     [SBSA_SECURE_UART] =        { 0x60030000, 0x00001000 },
 116     [SBSA_SECURE_UART_MM] =     { 0x60040000, 0x00001000 },
 117     [SBSA_SMMU] =               { 0x60050000, 0x00020000 },
 118     /* Space here reserved for more SMMUs */
 119     [SBSA_AHCI] =               { 0x60100000, 0x00010000 },
 120     [SBSA_EHCI] =               { 0x60110000, 0x00010000 },
 121     /* Space here reserved for other devices */
 122     [SBSA_PCIE_PIO] =           { 0x7fff0000, 0x00010000 },
 123     /* 32-bit address PCIE MMIO space */
 124     [SBSA_PCIE_MMIO] =          { 0x80000000, 0x70000000 },
 125     /* 256M PCIE ECAM space */
 126     [SBSA_PCIE_ECAM] =          { 0xf0000000, 0x10000000 },
 127     /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
 128     [SBSA_PCIE_MMIO_HIGH] =     { 0x100000000ULL, 0xFF00000000ULL },
 129     [SBSA_MEM] =                { 0x10000000000ULL, RAMLIMIT_BYTES },
 130 };
 131
 132 static const int sbsa_ref_irqmap[] = {
 133     [SBSA_UART] = 1,
 134     [SBSA_RTC] = 2,
 135     [SBSA_PCIE] = 3, /* ... to 6 */
 136     [SBSA_GPIO] = 7,
 137     [SBSA_SECURE_UART] = 8,
 138     [SBSA_SECURE_UART_MM] = 9,
 139     [SBSA_AHCI] = 10,
 140     [SBSA_EHCI] = 11,
 141     [SBSA_SMMU] = 12, /* ... to 15 */
 142     [SBSA_GWDT_WS0] = 16,
 143 };
 144
 145 static const char * const valid_cpus[] = {
 146     ARM_CPU_TYPE_NAME("cortex-a57"),
 147     ARM_CPU_TYPE_NAME("cortex-a72"),
 148     ARM_CPU_TYPE_NAME("cortex-a76"),
 149     ARM_CPU_TYPE_NAME("neoverse-n1"),
 150     ARM_CPU_TYPE_NAME("max"),
 151 };
 152
 153 static bool cpu_type_valid(const char *cpu)
 154 {
 155     int i;
 156
 157     for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
 158         if (strcmp(cpu, valid_cpus[i]) == 0) {
 159             return true;
 160         }
 161     }
 162     return false;
 163 }
 164
 165 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
 166 {
 167     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
 168     return arm_cpu_mp_affinity(idx, clustersz);
 169 }
 170
 171 /*
 172  * Firmware on this machine only uses ACPI table to load OS, these limited
 173  * device tree nodes are just to let firmware know the info which varies from
 174  * command line parameters, so it is not necessary to be fully compatible
 175  * with the kernel CPU and NUMA binding rules.
 176  */
 177 static void create_fdt(SBSAMachineState *sms)
 178 {
 179     void *fdt = create_device_tree(&sms->fdt_size);
 180     const MachineState *ms = MACHINE(sms);
 181     int nb_numa_nodes = ms->numa_state->num_nodes;
 182     int cpu;
 183
 184     if (!fdt) {
 185         error_report("create_device_tree() failed");
 186         exit(1);
 187     }
 188
 189     sms->fdt = fdt;
 190
 191     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref");
 192     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 193     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 194
 195     /*
 196      * This versioning scheme is for informing platform fw only. It is neither:
 197      * - A QEMU versioned machine type; a given version of QEMU will emulate
 198      *   a given version of the platform.
 199      * - A reflection of level of SBSA (now SystemReady SR) support provided.
 200      *
 201      * machine-version-major: updated when changes breaking fw compatibility
 202      *                        are introduced.
 203      * machine-version-minor: updated when features are added that don't break
 204      *                        fw compatibility.
 205      */
 206     qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
 207     qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
 208
 209     if (ms->numa_state->have_numa_distance) {
 210         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
 211         uint32_t *matrix = g_malloc0(size);
 212         int idx, i, j;
 213
 214         for (i = 0; i < nb_numa_nodes; i++) {
 215             for (j = 0; j < nb_numa_nodes; j++) {
 216                 idx = (i * nb_numa_nodes + j) * 3;
 217                 matrix[idx + 0] = cpu_to_be32(i);
 218                 matrix[idx + 1] = cpu_to_be32(j);
 219                 matrix[idx + 2] =
 220                     cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
 221             }
 222         }
 223
 224         qemu_fdt_add_subnode(fdt, "/distance-map");
 225         qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
 226                          matrix, size);
 227         g_free(matrix);
 228     }
 229
 230     /*
 231      * From Documentation/devicetree/bindings/arm/cpus.yaml
 232      *  On ARM v8 64-bit systems this property is required
 233      *    and matches the MPIDR_EL1 register affinity bits.
 234      *
 235      *    * If cpus node's #address-cells property is set to 2
 236      *
 237      *      The first reg cell bits [7:0] must be set to
 238      *      bits [39:32] of MPIDR_EL1.
 239      *
 240      *      The second reg cell bits [23:0] must be set to
 241      *      bits [23:0] of MPIDR_EL1.
 242      */
 243     qemu_fdt_add_subnode(sms->fdt, "/cpus");
 244     qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2);
 245     qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0);
 246
 247     for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
 248         char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 249         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
 250         CPUState *cs = CPU(armcpu);
 251         uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu);
 252
 253         qemu_fdt_add_subnode(sms->fdt, nodename);
 254         qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr);
 255
 256         if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
 257             qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id",
 258                 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
 259         }
 260
 261         g_free(nodename);
 262     }
 263 }
 264
 265 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
 266
 267 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms,
 268                                         const char *name,
 269                                         const char *alias_prop_name)
 270 {
 271     /*
 272      * Create a single flash device.  We use the same parameters as
 273      * the flash devices on the Versatile Express board.
 274      */
 275     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
 276
 277     qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE);
 278     qdev_prop_set_uint8(dev, "width", 4);
 279     qdev_prop_set_uint8(dev, "device-width", 2);
 280     qdev_prop_set_bit(dev, "big-endian", false);
 281     qdev_prop_set_uint16(dev, "id0", 0x89);
 282     qdev_prop_set_uint16(dev, "id1", 0x18);
 283     qdev_prop_set_uint16(dev, "id2", 0x00);
 284     qdev_prop_set_uint16(dev, "id3", 0x00);
 285     qdev_prop_set_string(dev, "name", name);
 286     object_property_add_child(OBJECT(sms), name, OBJECT(dev));
 287     object_property_add_alias(OBJECT(sms), alias_prop_name,
 288                               OBJECT(dev), "drive");
 289     return PFLASH_CFI01(dev);
 290 }
 291
 292 static void sbsa_flash_create(SBSAMachineState *sms)
 293 {
 294     sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0");
 295     sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1");
 296 }
 297
 298 static void sbsa_flash_map1(PFlashCFI01 *flash,
 299                             hwaddr base, hwaddr size,
 300                             MemoryRegion *sysmem)
 301 {
 302     DeviceState *dev = DEVICE(flash);
 303
 304     assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE));
 305     assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
 306     qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
 307     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 308
 309     memory_region_add_subregion(sysmem, base,
 310                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
 311                                                        0));
 312 }
 313
 314 static void sbsa_flash_map(SBSAMachineState *sms,
 315                            MemoryRegion *sysmem,
 316                            MemoryRegion *secure_sysmem)
 317 {
 318     /*
 319      * Map two flash devices to fill the SBSA_FLASH space in the memmap.
 320      * sysmem is the system memory space. secure_sysmem is the secure view
 321      * of the system, and the first flash device should be made visible only
 322      * there. The second flash device is visible to both secure and nonsecure.
 323      */
 324     hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2;
 325     hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base;
 326
 327     sbsa_flash_map1(sms->flash[0], flashbase, flashsize,
 328                     secure_sysmem);
 329     sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize,
 330                     sysmem);
 331 }
 332
 333 static bool sbsa_firmware_init(SBSAMachineState *sms,
 334                                MemoryRegion *sysmem,
 335                                MemoryRegion *secure_sysmem)
 336 {
 337     const char *bios_name;
 338     int i;
 339     BlockBackend *pflash_blk0;
 340
 341     /* Map legacy -drive if=pflash to machine properties */
 342     for (i = 0; i < ARRAY_SIZE(sms->flash); i++) {
 343         pflash_cfi01_legacy_drive(sms->flash[i],
 344                                   drive_get(IF_PFLASH, 0, i));
 345     }
 346
 347     sbsa_flash_map(sms, sysmem, secure_sysmem);
 348
 349     pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]);
 350
 351     bios_name = MACHINE(sms)->firmware;
 352     if (bios_name) {
 353         char *fname;
 354         MemoryRegion *mr;
 355         int image_size;
 356
 357         if (pflash_blk0) {
 358             error_report("The contents of the first flash device may be "
 359                          "specified with -bios or with -drive if=pflash... "
 360                          "but you cannot use both options at once");
 361             exit(1);
 362         }
 363
 364         /* Fall back to -bios */
 365
 366         fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 367         if (!fname) {
 368             error_report("Could not find ROM image '%s'", bios_name);
 369             exit(1);
 370         }
 371         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0);
 372         image_size = load_image_mr(fname, mr);
 373         g_free(fname);
 374         if (image_size < 0) {
 375             error_report("Could not load ROM image '%s'", bios_name);
 376             exit(1);
 377         }
 378     }
 379
 380     return pflash_blk0 || bios_name;
 381 }
 382
 383 static void create_secure_ram(SBSAMachineState *sms,
 384                               MemoryRegion *secure_sysmem)
 385 {
 386     MemoryRegion *secram = g_new(MemoryRegion, 1);
 387     hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base;
 388     hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size;
 389
 390     memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size,
 391                            &error_fatal);
 392     memory_region_add_subregion(secure_sysmem, base, secram);
 393 }
 394
 395 static void create_gic(SBSAMachineState *sms)
 396 {
 397     unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
 398     SysBusDevice *gicbusdev;
 399     const char *gictype;
 400     uint32_t redist0_capacity, redist0_count;
 401     int i;
 402
 403     gictype = gicv3_class_name();
 404
 405     sms->gic = qdev_new(gictype);
 406     qdev_prop_set_uint32(sms->gic, "revision", 3);
 407     qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus);
 408     /*
 409      * Note that the num-irq property counts both internal and external
 410      * interrupts; there are always 32 of the former (mandated by GIC spec).
 411      */
 412     qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32);
 413     qdev_prop_set_bit(sms->gic, "has-security-extensions", true);
 414
 415     redist0_capacity =
 416                 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
 417     redist0_count = MIN(smp_cpus, redist0_capacity);
 418
 419     qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
 420     qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
 421
 422     gicbusdev = SYS_BUS_DEVICE(sms->gic);
 423     sysbus_realize_and_unref(gicbusdev, &error_fatal);
 424     sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
 425     sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
 426
 427     /*
 428      * Wire the outputs from each CPU's generic timer and the GICv3
 429      * maintenance interrupt signal to the appropriate GIC PPI inputs,
 430      * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
 431      */
 432     for (i = 0; i < smp_cpus; i++) {
 433         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
 434         int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
 435         int irq;
 436         /*
 437          * Mapping from the output timer irq lines from the CPU to the
 438          * GIC PPI inputs used for this board.
 439          */
 440         const int timer_irq[] = {
 441             [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
 442             [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
 443             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
 444             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
 445         };
 446
 447         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
 448             qdev_connect_gpio_out(cpudev, irq,
 449                                   qdev_get_gpio_in(sms->gic,
 450                                                    ppibase + timer_irq[irq]));
 451         }
 452
 453         qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
 454                                     qdev_get_gpio_in(sms->gic, ppibase
 455                                                      + ARCH_GIC_MAINT_IRQ));
 456         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
 457                                     qdev_get_gpio_in(sms->gic, ppibase
 458                                                      + VIRTUAL_PMU_IRQ));
 459
 460         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 461         sysbus_connect_irq(gicbusdev, i + smp_cpus,
 462                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 463         sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
 464                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
 465         sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
 466                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
 467     }
 468 }
 469
 470 static void create_uart(const SBSAMachineState *sms, int uart,
 471                         MemoryRegion *mem, Chardev *chr)
 472 {
 473     hwaddr base = sbsa_ref_memmap[uart].base;
 474     int irq = sbsa_ref_irqmap[uart];
 475     DeviceState *dev = qdev_new(TYPE_PL011);
 476     SysBusDevice *s = SYS_BUS_DEVICE(dev);
 477
 478     qdev_prop_set_chr(dev, "chardev", chr);
 479     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 480     memory_region_add_subregion(mem, base,
 481                                 sysbus_mmio_get_region(s, 0));
 482     sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
 483 }
 484
 485 static void create_rtc(const SBSAMachineState *sms)
 486 {
 487     hwaddr base = sbsa_ref_memmap[SBSA_RTC].base;
 488     int irq = sbsa_ref_irqmap[SBSA_RTC];
 489
 490     sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
 491 }
 492
 493 static void create_wdt(const SBSAMachineState *sms)
 494 {
 495     hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base;
 496     hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base;
 497     DeviceState *dev = qdev_new(TYPE_WDT_SBSA);
 498     SysBusDevice *s = SYS_BUS_DEVICE(dev);
 499     int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0];
 500
 501     sysbus_realize_and_unref(s, &error_fatal);
 502     sysbus_mmio_map(s, 0, rbase);
 503     sysbus_mmio_map(s, 1, cbase);
 504     sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
 505 }
 506
 507 static DeviceState *gpio_key_dev;
 508 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
 509 {
 510     /* use gpio Pin 3 for power button event */
 511     qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
 512 }
 513
 514 static Notifier sbsa_ref_powerdown_notifier = {
 515     .notify = sbsa_ref_powerdown_req
 516 };
 517
 518 static void create_gpio(const SBSAMachineState *sms)
 519 {
 520     DeviceState *pl061_dev;
 521     hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base;
 522     int irq = sbsa_ref_irqmap[SBSA_GPIO];
 523
 524     pl061_dev = sysbus_create_simple("pl061", base,
 525                                      qdev_get_gpio_in(sms->gic, irq));
 526
 527     gpio_key_dev = sysbus_create_simple("gpio-key", -1,
 528                                         qdev_get_gpio_in(pl061_dev, 3));
 529
 530     /* connect powerdown request */
 531     qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier);
 532 }
 533
 534 static void create_ahci(const SBSAMachineState *sms)
 535 {
 536     hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
 537     int irq = sbsa_ref_irqmap[SBSA_AHCI];
 538     DeviceState *dev;
 539     DriveInfo *hd[NUM_SATA_PORTS];
 540     SysbusAHCIState *sysahci;
 541     AHCIState *ahci;
 542     int i;
 543
 544     dev = qdev_new("sysbus-ahci");
 545     qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
 546     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 547     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 548     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
 549
 550     sysahci = SYSBUS_AHCI(dev);
 551     ahci = &sysahci->ahci;
 552     ide_drive_get(hd, ARRAY_SIZE(hd));
 553     for (i = 0; i < ahci->ports; i++) {
 554         if (hd[i] == NULL) {
 555             continue;
 556         }
 557         ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
 558     }
 559 }
 560
 561 static void create_ehci(const SBSAMachineState *sms)
 562 {
 563     hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
 564     int irq = sbsa_ref_irqmap[SBSA_EHCI];
 565
 566     sysbus_create_simple("platform-ehci-usb", base,
 567                          qdev_get_gpio_in(sms->gic, irq));
 568 }
 569
 570 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
 571 {
 572     hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
 573     int irq =  sbsa_ref_irqmap[SBSA_SMMU];
 574     DeviceState *dev;
 575     int i;
 576
 577     dev = qdev_new("arm-smmuv3");
 578
 579     object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
 580                              &error_abort);
 581     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 582     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 583     for (i = 0; i < NUM_SMMU_IRQS; i++) {
 584         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 585                            qdev_get_gpio_in(sms->gic, irq + i));
 586     }
 587 }
 588
 589 static void create_pcie(SBSAMachineState *sms)
 590 {
 591     hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
 592     hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
 593     hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base;
 594     hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size;
 595     hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base;
 596     hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size;
 597     hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base;
 598     int irq = sbsa_ref_irqmap[SBSA_PCIE];
 599     MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
 600     MemoryRegion *ecam_alias, *ecam_reg;
 601     DeviceState *dev;
 602     PCIHostState *pci;
 603     int i;
 604
 605     dev = qdev_new(TYPE_GPEX_HOST);
 606     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 607
 608     /* Map ECAM space */
 609     ecam_alias = g_new0(MemoryRegion, 1);
 610     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 611     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
 612                              ecam_reg, 0, size_ecam);
 613     memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
 614
 615     /* Map the MMIO space */
 616     mmio_alias = g_new0(MemoryRegion, 1);
 617     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
 618     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
 619                              mmio_reg, base_mmio, size_mmio);
 620     memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
 621
 622     /* Map the MMIO_HIGH space */
 623     mmio_alias_high = g_new0(MemoryRegion, 1);
 624     memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high",
 625                              mmio_reg, base_mmio_high, size_mmio_high);
 626     memory_region_add_subregion(get_system_memory(), base_mmio_high,
 627                                 mmio_alias_high);
 628
 629     /* Map IO port space */
 630     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
 631
 632     for (i = 0; i < GPEX_NUM_IRQS; i++) {
 633         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 634                            qdev_get_gpio_in(sms->gic, irq + i));
 635         gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
 636     }
 637
 638     pci = PCI_HOST_BRIDGE(dev);
 639     if (pci->bus) {
 640         for (i = 0; i < nb_nics; i++) {
 641             NICInfo *nd = &nd_table[i];
 642
 643             if (!nd->model) {
 644                 nd->model = g_strdup("e1000e");
 645             }
 646
 647             pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
 648         }
 649     }
 650
 651     pci_create_simple(pci->bus, -1, "VGA");
 652
 653     create_smmu(sms, pci->bus);
 654 }
 655
 656 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
 657 {
 658     const SBSAMachineState *board = container_of(binfo, SBSAMachineState,
 659                                                  bootinfo);
 660
 661     *fdt_size = board->fdt_size;
 662     return board->fdt;
 663 }
 664
 665 static void create_secure_ec(MemoryRegion *mem)
 666 {
 667     hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base;
 668     DeviceState *dev = qdev_new("sbsa-ec");
 669     SysBusDevice *s = SYS_BUS_DEVICE(dev);
 670
 671     memory_region_add_subregion(mem, base,
 672                                 sysbus_mmio_get_region(s, 0));
 673 }
 674
 675 static void sbsa_ref_init(MachineState *machine)
 676 {
 677     unsigned int smp_cpus = machine->smp.cpus;
 678     unsigned int max_cpus = machine->smp.max_cpus;
 679     SBSAMachineState *sms = SBSA_MACHINE(machine);
 680     MachineClass *mc = MACHINE_GET_CLASS(machine);
 681     MemoryRegion *sysmem = get_system_memory();
 682     MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1);
 683     bool firmware_loaded;
 684     const CPUArchIdList *possible_cpus;
 685     int n, sbsa_max_cpus;
 686
 687     if (!cpu_type_valid(machine->cpu_type)) {
 688         error_report("sbsa-ref: CPU type %s not supported", machine->cpu_type);
 689         exit(1);
 690     }
 691
 692     if (kvm_enabled()) {
 693         error_report("sbsa-ref: KVM is not supported for this machine");
 694         exit(1);
 695     }
 696
 697     /*
 698      * The Secure view of the world is the same as the NonSecure,
 699      * but with a few extra devices. Create it as a container region
 700      * containing the system memory at low priority; any secure-only
 701      * devices go in at higher priority and take precedence.
 702      */
 703     memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
 704                        UINT64_MAX);
 705     memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
 706
 707     firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem);
 708
 709     /*
 710      * This machine has EL3 enabled, external firmware should supply PSCI
 711      * implementation, so the QEMU's internal PSCI is disabled.
 712      */
 713     sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
 714
 715     sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
 716
 717     if (max_cpus > sbsa_max_cpus) {
 718         error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
 719                      "supported by machine 'sbsa-ref' (%d)",
 720                      max_cpus, sbsa_max_cpus);
 721         exit(1);
 722     }
 723
 724     sms->smp_cpus = smp_cpus;
 725
 726     if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
 727         error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB);
 728         exit(1);
 729     }
 730
 731     possible_cpus = mc->possible_cpu_arch_ids(machine);
 732     for (n = 0; n < possible_cpus->len; n++) {
 733         Object *cpuobj;
 734         CPUState *cs;
 735
 736         if (n >= smp_cpus) {
 737             break;
 738         }
 739
 740         cpuobj = object_new(possible_cpus->cpus[n].type);
 741         object_property_set_int(cpuobj, "mp-affinity",
 742                                 possible_cpus->cpus[n].arch_id, NULL);
 743
 744         cs = CPU(cpuobj);
 745         cs->cpu_index = n;
 746
 747         numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
 748                           &error_fatal);
 749
 750         if (object_property_find(cpuobj, "reset-cbar")) {
 751             object_property_set_int(cpuobj, "reset-cbar",
 752                                     sbsa_ref_memmap[SBSA_CPUPERIPHS].base,
 753                                     &error_abort);
 754         }
 755
 756         object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
 757                                  &error_abort);
 758
 759         object_property_set_link(cpuobj, "secure-memory",
 760                                  OBJECT(secure_sysmem), &error_abort);
 761
 762         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 763         object_unref(cpuobj);
 764     }
 765
 766     memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base,
 767                                 machine->ram);
 768
 769     create_fdt(sms);
 770
 771     create_secure_ram(sms, secure_sysmem);
 772
 773     create_gic(sms);
 774
 775     create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
 776     create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
 777     /* Second secure UART for RAS and MM from EL0 */
 778     create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
 779
 780     create_rtc(sms);
 781
 782     create_wdt(sms);
 783
 784     create_gpio(sms);
 785
 786     create_ahci(sms);
 787
 788     create_ehci(sms);
 789
 790     create_pcie(sms);
 791
 792     create_secure_ec(secure_sysmem);
 793
 794     sms->bootinfo.ram_size = machine->ram_size;
 795     sms->bootinfo.board_id = -1;
 796     sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
 797     sms->bootinfo.get_dtb = sbsa_ref_dtb;
 798     sms->bootinfo.firmware_loaded = firmware_loaded;
 799     arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo);
 800 }
 801
 802 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
 803 {
 804     unsigned int max_cpus = ms->smp.max_cpus;
 805     SBSAMachineState *sms = SBSA_MACHINE(ms);
 806     int n;
 807
 808     if (ms->possible_cpus) {
 809         assert(ms->possible_cpus->len == max_cpus);
 810         return ms->possible_cpus;
 811     }
 812
 813     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
 814                                   sizeof(CPUArchId) * max_cpus);
 815     ms->possible_cpus->len = max_cpus;
 816     for (n = 0; n < ms->possible_cpus->len; n++) {
 817         ms->possible_cpus->cpus[n].type = ms->cpu_type;
 818         ms->possible_cpus->cpus[n].arch_id =
 819             sbsa_ref_cpu_mp_affinity(sms, n);
 820         ms->possible_cpus->cpus[n].props.has_thread_id = true;
 821         ms->possible_cpus->cpus[n].props.thread_id = n;
 822     }
 823     return ms->possible_cpus;
 824 }
 825
 826 static CpuInstanceProperties
 827 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
 828 {
 829     MachineClass *mc = MACHINE_GET_CLASS(ms);
 830     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
 831
 832     assert(cpu_index < possible_cpus->len);
 833     return possible_cpus->cpus[cpu_index].props;
 834 }
 835
 836 static int64_t
 837 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
 838 {
 839     return idx % ms->numa_state->num_nodes;
 840 }
 841
 842 static void sbsa_ref_instance_init(Object *obj)
 843 {
 844     SBSAMachineState *sms = SBSA_MACHINE(obj);
 845
 846     sbsa_flash_create(sms);
 847 }
 848
 849 static void sbsa_ref_class_init(ObjectClass *oc, void *data)
 850 {
 851     MachineClass *mc = MACHINE_CLASS(oc);
 852
 853     mc->init = sbsa_ref_init;
 854     mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
 855     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57");
 856     mc->max_cpus = 512;
 857     mc->pci_allow_0_address = true;
 858     mc->minimum_page_bits = 12;
 859     mc->block_default_type = IF_IDE;
 860     mc->no_cdrom = 1;
 861     mc->default_ram_size = 1 * GiB;
 862     mc->default_ram_id = "sbsa-ref.ram";
 863     mc->default_cpus = 4;
 864     mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
 865     mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
 866     mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;
 867 }
 868
 869 static const TypeInfo sbsa_ref_info = {
 870     .name          = TYPE_SBSA_MACHINE,
 871     .parent        = TYPE_MACHINE,
 872     .instance_init = sbsa_ref_instance_init,
 873     .class_init    = sbsa_ref_class_init,
 874     .instance_size = sizeof(SBSAMachineState),
 875 };
 876
 877 static void sbsa_ref_machine_init(void)
 878 {
 879     type_register_static(&sbsa_ref_info);
 880 }
 881
 882 type_init(sbsa_ref_machine_init);