hw/arm/sbsa-ref.c

   1 /*
   2  * ARM SBSA Reference Platform emulation
   3  *
   4  * Copyright (c) 2018 Linaro Limited
   5  * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/datadir.h"
  22 #include "qapi/error.h"
  23 #include "qemu/error-report.h"
  24 #include "qemu/units.h"
  25 #include "sysemu/device_tree.h"
  26 #include "sysemu/numa.h"
  27 #include "sysemu/runstate.h"
  28 #include "sysemu/sysemu.h"
  29 #include "exec/hwaddr.h"
  30 #include "kvm_arm.h"
  31 #include "hw/arm/boot.h"
  32 #include "hw/arm/fdt.h"
  33 #include "hw/arm/smmuv3.h"
  34 #include "hw/block/flash.h"
  35 #include "hw/boards.h"
  36 #include "hw/ide/internal.h"
  37 #include "hw/ide/ahci_internal.h"
  38 #include "hw/intc/arm_gicv3_common.h"
  39 #include "hw/loader.h"
  40 #include "hw/pci-host/gpex.h"
  41 #include "hw/qdev-properties.h"
  42 #include "hw/usb.h"
  43 #include "hw/char/pl011.h"
  44 #include "hw/watchdog/sbsa_gwdt.h"
  45 #include "net/net.h"
  46 #include "qom/object.h"
  47
  48 #define RAMLIMIT_GB 8192
  49 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
  50
  51 #define NUM_IRQS        256
  52 #define NUM_SMMU_IRQS   4
  53 #define NUM_SATA_PORTS  6
  54
  55 #define VIRTUAL_PMU_IRQ        7
  56 #define ARCH_GIC_MAINT_IRQ     9
  57 #define ARCH_TIMER_VIRT_IRQ    11
  58 #define ARCH_TIMER_S_EL1_IRQ   13
  59 #define ARCH_TIMER_NS_EL1_IRQ  14
  60 #define ARCH_TIMER_NS_EL2_IRQ  10
  61
  62 enum {
  63     SBSA_FLASH,
  64     SBSA_MEM,
  65     SBSA_CPUPERIPHS,
  66     SBSA_GIC_DIST,
  67     SBSA_GIC_REDIST,
  68     SBSA_SECURE_EC,
  69     SBSA_GWDT_WS0,
  70     SBSA_GWDT_REFRESH,
  71     SBSA_GWDT_CONTROL,
  72     SBSA_SMMU,
  73     SBSA_UART,
  74     SBSA_RTC,
  75     SBSA_PCIE,
  76     SBSA_PCIE_MMIO,
  77     SBSA_PCIE_MMIO_HIGH,
  78     SBSA_PCIE_PIO,
  79     SBSA_PCIE_ECAM,
  80     SBSA_GPIO,
  81     SBSA_SECURE_UART,
  82     SBSA_SECURE_UART_MM,
  83     SBSA_SECURE_MEM,
  84     SBSA_AHCI,
  85     SBSA_EHCI,
  86 };
  87
  88 struct SBSAMachineState {
  89     MachineState parent;
  90     struct arm_boot_info bootinfo;
  91     int smp_cpus;
  92     void *fdt;
  93     int fdt_size;
  94     int psci_conduit;
  95     DeviceState *gic;
  96     PFlashCFI01 *flash[2];
  97 };
  98
  99 #define TYPE_SBSA_MACHINE   MACHINE_TYPE_NAME("sbsa-ref")
 100 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE)
 101
 102 static const MemMapEntry sbsa_ref_memmap[] = {
 103     /* 512M boot ROM */
 104     [SBSA_FLASH] =              {          0, 0x20000000 },
 105     /* 512M secure memory */
 106     [SBSA_SECURE_MEM] =         { 0x20000000, 0x20000000 },
 107     /* Space reserved for CPU peripheral devices */
 108     [SBSA_CPUPERIPHS] =         { 0x40000000, 0x00040000 },
 109     [SBSA_GIC_DIST] =           { 0x40060000, 0x00010000 },
 110     [SBSA_GIC_REDIST] =         { 0x40080000, 0x04000000 },
 111     [SBSA_SECURE_EC] =          { 0x50000000, 0x00001000 },
 112     [SBSA_GWDT_REFRESH] =       { 0x50010000, 0x00001000 },
 113     [SBSA_GWDT_CONTROL] =       { 0x50011000, 0x00001000 },
 114     [SBSA_UART] =               { 0x60000000, 0x00001000 },
 115     [SBSA_RTC] =                { 0x60010000, 0x00001000 },
 116     [SBSA_GPIO] =               { 0x60020000, 0x00001000 },
 117     [SBSA_SECURE_UART] =        { 0x60030000, 0x00001000 },
 118     [SBSA_SECURE_UART_MM] =     { 0x60040000, 0x00001000 },
 119     [SBSA_SMMU] =               { 0x60050000, 0x00020000 },
 120     /* Space here reserved for more SMMUs */
 121     [SBSA_AHCI] =               { 0x60100000, 0x00010000 },
 122     [SBSA_EHCI] =               { 0x60110000, 0x00010000 },
 123     /* Space here reserved for other devices */
 124     [SBSA_PCIE_PIO] =           { 0x7fff0000, 0x00010000 },
 125     /* 32-bit address PCIE MMIO space */
 126     [SBSA_PCIE_MMIO] =          { 0x80000000, 0x70000000 },
 127     /* 256M PCIE ECAM space */
 128     [SBSA_PCIE_ECAM] =          { 0xf0000000, 0x10000000 },
 129     /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
 130     [SBSA_PCIE_MMIO_HIGH] =     { 0x100000000ULL, 0xFF00000000ULL },
 131     [SBSA_MEM] =                { 0x10000000000ULL, RAMLIMIT_BYTES },
 132 };
 133
 134 static const int sbsa_ref_irqmap[] = {
 135     [SBSA_UART] = 1,
 136     [SBSA_RTC] = 2,
 137     [SBSA_PCIE] = 3, /* ... to 6 */
 138     [SBSA_GPIO] = 7,
 139     [SBSA_SECURE_UART] = 8,
 140     [SBSA_SECURE_UART_MM] = 9,
 141     [SBSA_AHCI] = 10,
 142     [SBSA_EHCI] = 11,
 143     [SBSA_SMMU] = 12, /* ... to 15 */
 144     [SBSA_GWDT_WS0] = 16,
 145 };
 146
 147 static const char * const valid_cpus[] = {
 148     ARM_CPU_TYPE_NAME("cortex-a57"),
 149     ARM_CPU_TYPE_NAME("cortex-a72"),
 150     ARM_CPU_TYPE_NAME("neoverse-n1"),
 151     ARM_CPU_TYPE_NAME("max"),
 152 };
 153
 154 static bool cpu_type_valid(const char *cpu)
 155 {
 156     int i;
 157
 158     for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
 159         if (strcmp(cpu, valid_cpus[i]) == 0) {
 160             return true;
 161         }
 162     }
 163     return false;
 164 }
 165
 166 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
 167 {
 168     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
 169     return arm_cpu_mp_affinity(idx, clustersz);
 170 }
 171
 172 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)
 173 {
 174     char *nodename;
 175
 176     nodename = g_strdup_printf("/intc");
 177     qemu_fdt_add_subnode(sms->fdt, nodename);
 178     qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
 179                                  2, sbsa_ref_memmap[SBSA_GIC_DIST].base,
 180                                  2, sbsa_ref_memmap[SBSA_GIC_DIST].size,
 181                                  2, sbsa_ref_memmap[SBSA_GIC_REDIST].base,
 182                                  2, sbsa_ref_memmap[SBSA_GIC_REDIST].size);
 183
 184     g_free(nodename);
 185 }
 186 /*
 187  * Firmware on this machine only uses ACPI table to load OS, these limited
 188  * device tree nodes are just to let firmware know the info which varies from
 189  * command line parameters, so it is not necessary to be fully compatible
 190  * with the kernel CPU and NUMA binding rules.
 191  */
 192 static void create_fdt(SBSAMachineState *sms)
 193 {
 194     void *fdt = create_device_tree(&sms->fdt_size);
 195     const MachineState *ms = MACHINE(sms);
 196     int nb_numa_nodes = ms->numa_state->num_nodes;
 197     int cpu;
 198
 199     if (!fdt) {
 200         error_report("create_device_tree() failed");
 201         exit(1);
 202     }
 203
 204     sms->fdt = fdt;
 205
 206     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref");
 207     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 208     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 209
 210     /*
 211      * This versioning scheme is for informing platform fw only. It is neither:
 212      * - A QEMU versioned machine type; a given version of QEMU will emulate
 213      *   a given version of the platform.
 214      * - A reflection of level of SBSA (now SystemReady SR) support provided.
 215      *
 216      * machine-version-major: updated when changes breaking fw compatibility
 217      *                        are introduced.
 218      * machine-version-minor: updated when features are added that don't break
 219      *                        fw compatibility.
 220      */
 221     qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
 222     qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 1);
 223
 224     if (ms->numa_state->have_numa_distance) {
 225         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
 226         uint32_t *matrix = g_malloc0(size);
 227         int idx, i, j;
 228
 229         for (i = 0; i < nb_numa_nodes; i++) {
 230             for (j = 0; j < nb_numa_nodes; j++) {
 231                 idx = (i * nb_numa_nodes + j) * 3;
 232                 matrix[idx + 0] = cpu_to_be32(i);
 233                 matrix[idx + 1] = cpu_to_be32(j);
 234                 matrix[idx + 2] =
 235                     cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
 236             }
 237         }
 238
 239         qemu_fdt_add_subnode(fdt, "/distance-map");
 240         qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
 241                          matrix, size);
 242         g_free(matrix);
 243     }
 244
 245     /*
 246      * From Documentation/devicetree/bindings/arm/cpus.yaml
 247      *  On ARM v8 64-bit systems this property is required
 248      *    and matches the MPIDR_EL1 register affinity bits.
 249      *
 250      *    * If cpus node's #address-cells property is set to 2
 251      *
 252      *      The first reg cell bits [7:0] must be set to
 253      *      bits [39:32] of MPIDR_EL1.
 254      *
 255      *      The second reg cell bits [23:0] must be set to
 256      *      bits [23:0] of MPIDR_EL1.
 257      */
 258     qemu_fdt_add_subnode(sms->fdt, "/cpus");
 259     qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2);
 260     qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0);
 261
 262     for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
 263         char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 264         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
 265         CPUState *cs = CPU(armcpu);
 266         uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu);
 267
 268         qemu_fdt_add_subnode(sms->fdt, nodename);
 269         qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr);
 270
 271         if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
 272             qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id",
 273                 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
 274         }
 275
 276         g_free(nodename);
 277     }
 278
 279     sbsa_fdt_add_gic_node(sms);
 280 }
 281
 282 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
 283
 284 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms,
 285                                         const char *name,
 286                                         const char *alias_prop_name)
 287 {
 288     /*
 289      * Create a single flash device.  We use the same parameters as
 290      * the flash devices on the Versatile Express board.
 291      */
 292     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
 293
 294     qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE);
 295     qdev_prop_set_uint8(dev, "width", 4);
 296     qdev_prop_set_uint8(dev, "device-width", 2);
 297     qdev_prop_set_bit(dev, "big-endian", false);
 298     qdev_prop_set_uint16(dev, "id0", 0x89);
 299     qdev_prop_set_uint16(dev, "id1", 0x18);
 300     qdev_prop_set_uint16(dev, "id2", 0x00);
 301     qdev_prop_set_uint16(dev, "id3", 0x00);
 302     qdev_prop_set_string(dev, "name", name);
 303     object_property_add_child(OBJECT(sms), name, OBJECT(dev));
 304     object_property_add_alias(OBJECT(sms), alias_prop_name,
 305                               OBJECT(dev), "drive");
 306     return PFLASH_CFI01(dev);
 307 }
 308
 309 static void sbsa_flash_create(SBSAMachineState *sms)
 310 {
 311     sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0");
 312     sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1");
 313 }
 314
 315 static void sbsa_flash_map1(PFlashCFI01 *flash,
 316                             hwaddr base, hwaddr size,
 317                             MemoryRegion *sysmem)
 318 {
 319     DeviceState *dev = DEVICE(flash);
 320
 321     assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE));
 322     assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
 323     qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
 324     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 325
 326     memory_region_add_subregion(sysmem, base,
 327                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
 328                                                        0));
 329 }
 330
 331 static void sbsa_flash_map(SBSAMachineState *sms,
 332                            MemoryRegion *sysmem,
 333                            MemoryRegion *secure_sysmem)
 334 {
 335     /*
 336      * Map two flash devices to fill the SBSA_FLASH space in the memmap.
 337      * sysmem is the system memory space. secure_sysmem is the secure view
 338      * of the system, and the first flash device should be made visible only
 339      * there. The second flash device is visible to both secure and nonsecure.
 340      */
 341     hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2;
 342     hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base;
 343
 344     sbsa_flash_map1(sms->flash[0], flashbase, flashsize,
 345                     secure_sysmem);
 346     sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize,
 347                     sysmem);
 348 }
 349
 350 static bool sbsa_firmware_init(SBSAMachineState *sms,
 351                                MemoryRegion *sysmem,
 352                                MemoryRegion *secure_sysmem)
 353 {
 354     const char *bios_name;
 355     int i;
 356     BlockBackend *pflash_blk0;
 357
 358     /* Map legacy -drive if=pflash to machine properties */
 359     for (i = 0; i < ARRAY_SIZE(sms->flash); i++) {
 360         pflash_cfi01_legacy_drive(sms->flash[i],
 361                                   drive_get(IF_PFLASH, 0, i));
 362     }
 363
 364     sbsa_flash_map(sms, sysmem, secure_sysmem);
 365
 366     pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]);
 367
 368     bios_name = MACHINE(sms)->firmware;
 369     if (bios_name) {
 370         char *fname;
 371         MemoryRegion *mr;
 372         int image_size;
 373
 374         if (pflash_blk0) {
 375             error_report("The contents of the first flash device may be "
 376                          "specified with -bios or with -drive if=pflash... "
 377                          "but you cannot use both options at once");
 378             exit(1);
 379         }
 380
 381         /* Fall back to -bios */
 382
 383         fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 384         if (!fname) {
 385             error_report("Could not find ROM image '%s'", bios_name);
 386             exit(1);
 387         }
 388         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0);
 389         image_size = load_image_mr(fname, mr);
 390         g_free(fname);
 391         if (image_size < 0) {
 392             error_report("Could not load ROM image '%s'", bios_name);
 393             exit(1);
 394         }
 395     }
 396
 397     return pflash_blk0 || bios_name;
 398 }
 399
 400 static void create_secure_ram(SBSAMachineState *sms,
 401                               MemoryRegion *secure_sysmem)
 402 {
 403     MemoryRegion *secram = g_new(MemoryRegion, 1);
 404     hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base;
 405     hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size;
 406
 407     memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size,
 408                            &error_fatal);
 409     memory_region_add_subregion(secure_sysmem, base, secram);
 410 }
 411
 412 static void create_gic(SBSAMachineState *sms)
 413 {
 414     unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
 415     SysBusDevice *gicbusdev;
 416     const char *gictype;
 417     uint32_t redist0_capacity, redist0_count;
 418     int i;
 419
 420     gictype = gicv3_class_name();
 421
 422     sms->gic = qdev_new(gictype);
 423     qdev_prop_set_uint32(sms->gic, "revision", 3);
 424     qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus);
 425     /*
 426      * Note that the num-irq property counts both internal and external
 427      * interrupts; there are always 32 of the former (mandated by GIC spec).
 428      */
 429     qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32);
 430     qdev_prop_set_bit(sms->gic, "has-security-extensions", true);
 431
 432     redist0_capacity =
 433                 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
 434     redist0_count = MIN(smp_cpus, redist0_capacity);
 435
 436     qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
 437     qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
 438
 439     gicbusdev = SYS_BUS_DEVICE(sms->gic);
 440     sysbus_realize_and_unref(gicbusdev, &error_fatal);
 441     sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
 442     sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
 443
 444     /*
 445      * Wire the outputs from each CPU's generic timer and the GICv3
 446      * maintenance interrupt signal to the appropriate GIC PPI inputs,
 447      * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
 448      */
 449     for (i = 0; i < smp_cpus; i++) {
 450         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
 451         int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
 452         int irq;
 453         /*
 454          * Mapping from the output timer irq lines from the CPU to the
 455          * GIC PPI inputs used for this board.
 456          */
 457         const int timer_irq[] = {
 458             [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
 459             [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
 460             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
 461             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
 462         };
 463
 464         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
 465             qdev_connect_gpio_out(cpudev, irq,
 466                                   qdev_get_gpio_in(sms->gic,
 467                                                    ppibase + timer_irq[irq]));
 468         }
 469
 470         qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
 471                                     qdev_get_gpio_in(sms->gic, ppibase
 472                                                      + ARCH_GIC_MAINT_IRQ));
 473         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
 474                                     qdev_get_gpio_in(sms->gic, ppibase
 475                                                      + VIRTUAL_PMU_IRQ));
 476
 477         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 478         sysbus_connect_irq(gicbusdev, i + smp_cpus,
 479                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 480         sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
 481                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
 482         sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
 483                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
 484     }
 485 }
 486
 487 static void create_uart(const SBSAMachineState *sms, int uart,
 488                         MemoryRegion *mem, Chardev *chr)
 489 {
 490     hwaddr base = sbsa_ref_memmap[uart].base;
 491     int irq = sbsa_ref_irqmap[uart];
 492     DeviceState *dev = qdev_new(TYPE_PL011);
 493     SysBusDevice *s = SYS_BUS_DEVICE(dev);
 494
 495     qdev_prop_set_chr(dev, "chardev", chr);
 496     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 497     memory_region_add_subregion(mem, base,
 498                                 sysbus_mmio_get_region(s, 0));
 499     sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
 500 }
 501
 502 static void create_rtc(const SBSAMachineState *sms)
 503 {
 504     hwaddr base = sbsa_ref_memmap[SBSA_RTC].base;
 505     int irq = sbsa_ref_irqmap[SBSA_RTC];
 506
 507     sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
 508 }
 509
 510 static void create_wdt(const SBSAMachineState *sms)
 511 {
 512     hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base;
 513     hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base;
 514     DeviceState *dev = qdev_new(TYPE_WDT_SBSA);
 515     SysBusDevice *s = SYS_BUS_DEVICE(dev);
 516     int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0];
 517
 518     sysbus_realize_and_unref(s, &error_fatal);
 519     sysbus_mmio_map(s, 0, rbase);
 520     sysbus_mmio_map(s, 1, cbase);
 521     sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
 522 }
 523
 524 static DeviceState *gpio_key_dev;
 525 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
 526 {
 527     /* use gpio Pin 3 for power button event */
 528     qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
 529 }
 530
 531 static Notifier sbsa_ref_powerdown_notifier = {
 532     .notify = sbsa_ref_powerdown_req
 533 };
 534
 535 static void create_gpio(const SBSAMachineState *sms)
 536 {
 537     DeviceState *pl061_dev;
 538     hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base;
 539     int irq = sbsa_ref_irqmap[SBSA_GPIO];
 540
 541     pl061_dev = sysbus_create_simple("pl061", base,
 542                                      qdev_get_gpio_in(sms->gic, irq));
 543
 544     gpio_key_dev = sysbus_create_simple("gpio-key", -1,
 545                                         qdev_get_gpio_in(pl061_dev, 3));
 546
 547     /* connect powerdown request */
 548     qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier);
 549 }
 550
 551 static void create_ahci(const SBSAMachineState *sms)
 552 {
 553     hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
 554     int irq = sbsa_ref_irqmap[SBSA_AHCI];
 555     DeviceState *dev;
 556     DriveInfo *hd[NUM_SATA_PORTS];
 557     SysbusAHCIState *sysahci;
 558     AHCIState *ahci;
 559     int i;
 560
 561     dev = qdev_new("sysbus-ahci");
 562     qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
 563     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 564     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 565     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
 566
 567     sysahci = SYSBUS_AHCI(dev);
 568     ahci = &sysahci->ahci;
 569     ide_drive_get(hd, ARRAY_SIZE(hd));
 570     for (i = 0; i < ahci->ports; i++) {
 571         if (hd[i] == NULL) {
 572             continue;
 573         }
 574         ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]);
 575     }
 576 }
 577
 578 static void create_ehci(const SBSAMachineState *sms)
 579 {
 580     hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
 581     int irq = sbsa_ref_irqmap[SBSA_EHCI];
 582
 583     sysbus_create_simple("platform-ehci-usb", base,
 584                          qdev_get_gpio_in(sms->gic, irq));
 585 }
 586
 587 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
 588 {
 589     hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
 590     int irq =  sbsa_ref_irqmap[SBSA_SMMU];
 591     DeviceState *dev;
 592     int i;
 593
 594     dev = qdev_new(TYPE_ARM_SMMUV3);
 595
 596     object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
 597                              &error_abort);
 598     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 599     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 600     for (i = 0; i < NUM_SMMU_IRQS; i++) {
 601         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 602                            qdev_get_gpio_in(sms->gic, irq + i));
 603     }
 604 }
 605
 606 static void create_pcie(SBSAMachineState *sms)
 607 {
 608     hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
 609     hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
 610     hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base;
 611     hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size;
 612     hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base;
 613     hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size;
 614     hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base;
 615     int irq = sbsa_ref_irqmap[SBSA_PCIE];
 616     MachineClass *mc = MACHINE_GET_CLASS(sms);
 617     MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
 618     MemoryRegion *ecam_alias, *ecam_reg;
 619     DeviceState *dev;
 620     PCIHostState *pci;
 621     int i;
 622
 623     dev = qdev_new(TYPE_GPEX_HOST);
 624     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 625
 626     /* Map ECAM space */
 627     ecam_alias = g_new0(MemoryRegion, 1);
 628     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 629     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
 630                              ecam_reg, 0, size_ecam);
 631     memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
 632
 633     /* Map the MMIO space */
 634     mmio_alias = g_new0(MemoryRegion, 1);
 635     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
 636     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
 637                              mmio_reg, base_mmio, size_mmio);
 638     memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
 639
 640     /* Map the MMIO_HIGH space */
 641     mmio_alias_high = g_new0(MemoryRegion, 1);
 642     memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high",
 643                              mmio_reg, base_mmio_high, size_mmio_high);
 644     memory_region_add_subregion(get_system_memory(), base_mmio_high,
 645                                 mmio_alias_high);
 646
 647     /* Map IO port space */
 648     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
 649
 650     for (i = 0; i < GPEX_NUM_IRQS; i++) {
 651         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 652                            qdev_get_gpio_in(sms->gic, irq + i));
 653         gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
 654     }
 655
 656     pci = PCI_HOST_BRIDGE(dev);
 657     if (pci->bus) {
 658         for (i = 0; i < nb_nics; i++) {
 659             NICInfo *nd = &nd_table[i];
 660
 661             if (!nd->model) {
 662                 nd->model = g_strdup(mc->default_nic);
 663             }
 664
 665             pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
 666         }
 667     }
 668
 669     pci_create_simple(pci->bus, -1, "bochs-display");
 670
 671     create_smmu(sms, pci->bus);
 672 }
 673
 674 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
 675 {
 676     const SBSAMachineState *board = container_of(binfo, SBSAMachineState,
 677                                                  bootinfo);
 678
 679     *fdt_size = board->fdt_size;
 680     return board->fdt;
 681 }
 682
 683 static void create_secure_ec(MemoryRegion *mem)
 684 {
 685     hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base;
 686     DeviceState *dev = qdev_new("sbsa-ec");
 687     SysBusDevice *s = SYS_BUS_DEVICE(dev);
 688
 689     memory_region_add_subregion(mem, base,
 690                                 sysbus_mmio_get_region(s, 0));
 691 }
 692
 693 static void sbsa_ref_init(MachineState *machine)
 694 {
 695     unsigned int smp_cpus = machine->smp.cpus;
 696     unsigned int max_cpus = machine->smp.max_cpus;
 697     SBSAMachineState *sms = SBSA_MACHINE(machine);
 698     MachineClass *mc = MACHINE_GET_CLASS(machine);
 699     MemoryRegion *sysmem = get_system_memory();
 700     MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1);
 701     bool firmware_loaded;
 702     const CPUArchIdList *possible_cpus;
 703     int n, sbsa_max_cpus;
 704
 705     if (!cpu_type_valid(machine->cpu_type)) {
 706         error_report("sbsa-ref: CPU type %s not supported", machine->cpu_type);
 707         exit(1);
 708     }
 709
 710     if (kvm_enabled()) {
 711         error_report("sbsa-ref: KVM is not supported for this machine");
 712         exit(1);
 713     }
 714
 715     /*
 716      * The Secure view of the world is the same as the NonSecure,
 717      * but with a few extra devices. Create it as a container region
 718      * containing the system memory at low priority; any secure-only
 719      * devices go in at higher priority and take precedence.
 720      */
 721     memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
 722                        UINT64_MAX);
 723     memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
 724
 725     firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem);
 726
 727     /*
 728      * This machine has EL3 enabled, external firmware should supply PSCI
 729      * implementation, so the QEMU's internal PSCI is disabled.
 730      */
 731     sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
 732
 733     sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
 734
 735     if (max_cpus > sbsa_max_cpus) {
 736         error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
 737                      "supported by machine 'sbsa-ref' (%d)",
 738                      max_cpus, sbsa_max_cpus);
 739         exit(1);
 740     }
 741
 742     sms->smp_cpus = smp_cpus;
 743
 744     if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
 745         error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB);
 746         exit(1);
 747     }
 748
 749     possible_cpus = mc->possible_cpu_arch_ids(machine);
 750     for (n = 0; n < possible_cpus->len; n++) {
 751         Object *cpuobj;
 752         CPUState *cs;
 753
 754         if (n >= smp_cpus) {
 755             break;
 756         }
 757
 758         cpuobj = object_new(possible_cpus->cpus[n].type);
 759         object_property_set_int(cpuobj, "mp-affinity",
 760                                 possible_cpus->cpus[n].arch_id, NULL);
 761
 762         cs = CPU(cpuobj);
 763         cs->cpu_index = n;
 764
 765         numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
 766                           &error_fatal);
 767
 768         if (object_property_find(cpuobj, "reset-cbar")) {
 769             object_property_set_int(cpuobj, "reset-cbar",
 770                                     sbsa_ref_memmap[SBSA_CPUPERIPHS].base,
 771                                     &error_abort);
 772         }
 773
 774         object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
 775                                  &error_abort);
 776
 777         object_property_set_link(cpuobj, "secure-memory",
 778                                  OBJECT(secure_sysmem), &error_abort);
 779
 780         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 781         object_unref(cpuobj);
 782     }
 783
 784     memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base,
 785                                 machine->ram);
 786
 787     create_fdt(sms);
 788
 789     create_secure_ram(sms, secure_sysmem);
 790
 791     create_gic(sms);
 792
 793     create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
 794     create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
 795     /* Second secure UART for RAS and MM from EL0 */
 796     create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
 797
 798     create_rtc(sms);
 799
 800     create_wdt(sms);
 801
 802     create_gpio(sms);
 803
 804     create_ahci(sms);
 805
 806     create_ehci(sms);
 807
 808     create_pcie(sms);
 809
 810     create_secure_ec(secure_sysmem);
 811
 812     sms->bootinfo.ram_size = machine->ram_size;
 813     sms->bootinfo.board_id = -1;
 814     sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
 815     sms->bootinfo.get_dtb = sbsa_ref_dtb;
 816     sms->bootinfo.firmware_loaded = firmware_loaded;
 817     arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo);
 818 }
 819
 820 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
 821 {
 822     unsigned int max_cpus = ms->smp.max_cpus;
 823     SBSAMachineState *sms = SBSA_MACHINE(ms);
 824     int n;
 825
 826     if (ms->possible_cpus) {
 827         assert(ms->possible_cpus->len == max_cpus);
 828         return ms->possible_cpus;
 829     }
 830
 831     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
 832                                   sizeof(CPUArchId) * max_cpus);
 833     ms->possible_cpus->len = max_cpus;
 834     for (n = 0; n < ms->possible_cpus->len; n++) {
 835         ms->possible_cpus->cpus[n].type = ms->cpu_type;
 836         ms->possible_cpus->cpus[n].arch_id =
 837             sbsa_ref_cpu_mp_affinity(sms, n);
 838         ms->possible_cpus->cpus[n].props.has_thread_id = true;
 839         ms->possible_cpus->cpus[n].props.thread_id = n;
 840     }
 841     return ms->possible_cpus;
 842 }
 843
 844 static CpuInstanceProperties
 845 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
 846 {
 847     MachineClass *mc = MACHINE_GET_CLASS(ms);
 848     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
 849
 850     assert(cpu_index < possible_cpus->len);
 851     return possible_cpus->cpus[cpu_index].props;
 852 }
 853
 854 static int64_t
 855 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
 856 {
 857     return idx % ms->numa_state->num_nodes;
 858 }
 859
 860 static void sbsa_ref_instance_init(Object *obj)
 861 {
 862     SBSAMachineState *sms = SBSA_MACHINE(obj);
 863
 864     sbsa_flash_create(sms);
 865 }
 866
 867 static void sbsa_ref_class_init(ObjectClass *oc, void *data)
 868 {
 869     MachineClass *mc = MACHINE_CLASS(oc);
 870
 871     mc->init = sbsa_ref_init;
 872     mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
 873     mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1");
 874     mc->max_cpus = 512;
 875     mc->pci_allow_0_address = true;
 876     mc->minimum_page_bits = 12;
 877     mc->block_default_type = IF_IDE;
 878     mc->no_cdrom = 1;
 879     mc->default_nic = "e1000e";
 880     mc->default_ram_size = 1 * GiB;
 881     mc->default_ram_id = "sbsa-ref.ram";
 882     mc->default_cpus = 4;
 883     mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
 884     mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
 885     mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;
 886 }
 887
 888 static const TypeInfo sbsa_ref_info = {
 889     .name          = TYPE_SBSA_MACHINE,
 890     .parent        = TYPE_MACHINE,
 891     .instance_init = sbsa_ref_instance_init,
 892     .class_init    = sbsa_ref_class_init,
 893     .instance_size = sizeof(SBSAMachineState),
 894 };
 895
 896 static void sbsa_ref_machine_init(void)
 897 {
 898     type_register_static(&sbsa_ref_info);
 899 }
 900
 901 type_init(sbsa_ref_machine_init);