2 * Luminary Micro Stellaris peripherals
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/core/split-irq.h"
13 #include "hw/sysbus.h"
15 #include "hw/ssi/ssi.h"
16 #include "hw/arm/boot.h"
17 #include "qemu/timer.h"
18 #include "hw/i2c/i2c.h"
20 #include "hw/boards.h"
22 #include "exec/address-spaces.h"
23 #include "sysemu/sysemu.h"
24 #include "hw/arm/armv7m.h"
25 #include "hw/char/pl011.h"
26 #include "hw/input/stellaris_gamepad.h"
28 #include "hw/watchdog/cmsdk-apb-watchdog.h"
29 #include "migration/vmstate.h"
30 #include "hw/misc/unimp.h"
31 #include "hw/timer/stellaris-gptm.h"
32 #include "hw/qdev-clock.h"
33 #include "qom/object.h"
34 #include "qapi/qmp/qlist.h"
45 #define BP_OLED_I2C 0x01
46 #define BP_OLED_SSI 0x02
47 #define BP_GAMEPAD 0x04
49 #define NUM_IRQ_LINES 64
50 #define NUM_PRIO_BITS 3
52 typedef const struct {
62 } stellaris_board_info
;
64 /* System controller. */
66 #define TYPE_STELLARIS_SYS "stellaris-sys"
67 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state
, STELLARIS_SYS
)
70 SysBusDevice parent_obj
;
87 /* Properties (all read-only registers) */
99 static void ssys_update(ssys_state
*s
)
101 qemu_set_irq(s
->irq
, (s
->int_status
& s
->int_mask
) != 0);
104 static uint32_t pllcfg_sandstorm
[16] = {
106 0x1ae0, /* 1.8432 Mhz */
108 0xd573, /* 2.4576 Mhz */
109 0x37a6, /* 3.57954 Mhz */
110 0x1ae2, /* 3.6864 Mhz */
112 0x98bc, /* 4.906 Mhz */
113 0x935b, /* 4.9152 Mhz */
115 0x4dee, /* 5.12 Mhz */
117 0x75db, /* 6.144 Mhz */
118 0x1ae6, /* 7.3728 Mhz */
120 0x585b /* 8.192 Mhz */
123 static uint32_t pllcfg_fury
[16] = {
125 0x1b20, /* 1.8432 Mhz */
127 0xf42b, /* 2.4576 Mhz */
128 0x37e3, /* 3.57954 Mhz */
129 0x1b21, /* 3.6864 Mhz */
131 0x98ee, /* 4.906 Mhz */
132 0xd5b4, /* 4.9152 Mhz */
134 0x4e27, /* 5.12 Mhz */
136 0xec1c, /* 6.144 Mhz */
137 0x1b23, /* 7.3728 Mhz */
139 0xb11c /* 8.192 Mhz */
142 #define DID0_VER_MASK 0x70000000
143 #define DID0_VER_0 0x00000000
144 #define DID0_VER_1 0x10000000
146 #define DID0_CLASS_MASK 0x00FF0000
147 #define DID0_CLASS_SANDSTORM 0x00000000
148 #define DID0_CLASS_FURY 0x00010000
150 static int ssys_board_class(const ssys_state
*s
)
152 uint32_t did0
= s
->did0
;
153 switch (did0
& DID0_VER_MASK
) {
155 return DID0_CLASS_SANDSTORM
;
157 switch (did0
& DID0_CLASS_MASK
) {
158 case DID0_CLASS_SANDSTORM
:
159 case DID0_CLASS_FURY
:
160 return did0
& DID0_CLASS_MASK
;
162 /* for unknown classes, fall through */
164 /* This can only happen if the hardwired constant did0 value
165 * in this board's stellaris_board_info struct is wrong.
167 g_assert_not_reached();
171 static uint64_t ssys_read(void *opaque
, hwaddr offset
,
174 ssys_state
*s
= (ssys_state
*)opaque
;
177 case 0x000: /* DID0 */
179 case 0x004: /* DID1 */
181 case 0x008: /* DC0 */
183 case 0x010: /* DC1 */
185 case 0x014: /* DC2 */
187 case 0x018: /* DC3 */
189 case 0x01c: /* DC4 */
191 case 0x030: /* PBORCTL */
193 case 0x034: /* LDOPCTL */
195 case 0x040: /* SRCR0 */
197 case 0x044: /* SRCR1 */
199 case 0x048: /* SRCR2 */
201 case 0x050: /* RIS */
202 return s
->int_status
;
203 case 0x054: /* IMC */
205 case 0x058: /* MISC */
206 return s
->int_status
& s
->int_mask
;
207 case 0x05c: /* RESC */
209 case 0x060: /* RCC */
211 case 0x064: /* PLLCFG */
214 xtal
= (s
->rcc
>> 6) & 0xf;
215 switch (ssys_board_class(s
)) {
216 case DID0_CLASS_FURY
:
217 return pllcfg_fury
[xtal
];
218 case DID0_CLASS_SANDSTORM
:
219 return pllcfg_sandstorm
[xtal
];
221 g_assert_not_reached();
224 case 0x070: /* RCC2 */
226 case 0x100: /* RCGC0 */
228 case 0x104: /* RCGC1 */
230 case 0x108: /* RCGC2 */
232 case 0x110: /* SCGC0 */
234 case 0x114: /* SCGC1 */
236 case 0x118: /* SCGC2 */
238 case 0x120: /* DCGC0 */
240 case 0x124: /* DCGC1 */
242 case 0x128: /* DCGC2 */
244 case 0x150: /* CLKVCLR */
246 case 0x160: /* LDOARST */
248 case 0x1e0: /* USER0 */
250 case 0x1e4: /* USER1 */
253 qemu_log_mask(LOG_GUEST_ERROR
,
254 "SSYS: read at bad offset 0x%x\n", (int)offset
);
259 static bool ssys_use_rcc2(ssys_state
*s
)
261 return (s
->rcc2
>> 31) & 0x1;
265 * Calculate the system clock period. We only want to propagate
266 * this change to the rest of the system if we're not being called
267 * from migration post-load.
269 static void ssys_calculate_system_clock(ssys_state
*s
, bool propagate_clock
)
273 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
274 * clock is 200MHz, which is a period of 5 ns. Dividing the clock
275 * frequency by X is the same as multiplying the period by X.
277 if (ssys_use_rcc2(s
)) {
278 period_ns
= 5 * (((s
->rcc2
>> 23) & 0x3f) + 1);
280 period_ns
= 5 * (((s
->rcc
>> 23) & 0xf) + 1);
282 clock_set_ns(s
->sysclk
, period_ns
);
283 if (propagate_clock
) {
284 clock_propagate(s
->sysclk
);
288 static void ssys_write(void *opaque
, hwaddr offset
,
289 uint64_t value
, unsigned size
)
291 ssys_state
*s
= (ssys_state
*)opaque
;
294 case 0x030: /* PBORCTL */
295 s
->pborctl
= value
& 0xffff;
297 case 0x034: /* LDOPCTL */
298 s
->ldopctl
= value
& 0x1f;
300 case 0x040: /* SRCR0 */
301 case 0x044: /* SRCR1 */
302 case 0x048: /* SRCR2 */
303 qemu_log_mask(LOG_UNIMP
, "Peripheral reset not implemented\n");
305 case 0x054: /* IMC */
306 s
->int_mask
= value
& 0x7f;
308 case 0x058: /* MISC */
309 s
->int_status
&= ~value
;
311 case 0x05c: /* RESC */
312 s
->resc
= value
& 0x3f;
314 case 0x060: /* RCC */
315 if ((s
->rcc
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
317 s
->int_status
|= (1 << 6);
320 ssys_calculate_system_clock(s
, true);
322 case 0x070: /* RCC2 */
323 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
327 if ((s
->rcc2
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
329 s
->int_status
|= (1 << 6);
332 ssys_calculate_system_clock(s
, true);
334 case 0x100: /* RCGC0 */
337 case 0x104: /* RCGC1 */
340 case 0x108: /* RCGC2 */
343 case 0x110: /* SCGC0 */
346 case 0x114: /* SCGC1 */
349 case 0x118: /* SCGC2 */
352 case 0x120: /* DCGC0 */
355 case 0x124: /* DCGC1 */
358 case 0x128: /* DCGC2 */
361 case 0x150: /* CLKVCLR */
364 case 0x160: /* LDOARST */
368 qemu_log_mask(LOG_GUEST_ERROR
,
369 "SSYS: write at bad offset 0x%x\n", (int)offset
);
374 static const MemoryRegionOps ssys_ops
= {
377 .endianness
= DEVICE_NATIVE_ENDIAN
,
380 static void stellaris_sys_reset_enter(Object
*obj
, ResetType type
)
382 ssys_state
*s
= STELLARIS_SYS(obj
);
387 if (ssys_board_class(s
) == DID0_CLASS_SANDSTORM
) {
390 s
->rcc2
= 0x07802810;
397 static void stellaris_sys_reset_hold(Object
*obj
, ResetType type
)
399 ssys_state
*s
= STELLARIS_SYS(obj
);
401 /* OK to propagate clocks from the hold phase */
402 ssys_calculate_system_clock(s
, true);
405 static void stellaris_sys_reset_exit(Object
*obj
, ResetType type
)
409 static int stellaris_sys_post_load(void *opaque
, int version_id
)
411 ssys_state
*s
= opaque
;
413 ssys_calculate_system_clock(s
, false);
418 static const VMStateDescription vmstate_stellaris_sys
= {
419 .name
= "stellaris_sys",
421 .minimum_version_id
= 1,
422 .post_load
= stellaris_sys_post_load
,
423 .fields
= (const VMStateField
[]) {
424 VMSTATE_UINT32(pborctl
, ssys_state
),
425 VMSTATE_UINT32(ldopctl
, ssys_state
),
426 VMSTATE_UINT32(int_mask
, ssys_state
),
427 VMSTATE_UINT32(int_status
, ssys_state
),
428 VMSTATE_UINT32(resc
, ssys_state
),
429 VMSTATE_UINT32(rcc
, ssys_state
),
430 VMSTATE_UINT32_V(rcc2
, ssys_state
, 2),
431 VMSTATE_UINT32_ARRAY(rcgc
, ssys_state
, 3),
432 VMSTATE_UINT32_ARRAY(scgc
, ssys_state
, 3),
433 VMSTATE_UINT32_ARRAY(dcgc
, ssys_state
, 3),
434 VMSTATE_UINT32(clkvclr
, ssys_state
),
435 VMSTATE_UINT32(ldoarst
, ssys_state
),
436 /* No field for sysclk -- handled in post-load instead */
437 VMSTATE_END_OF_LIST()
441 static Property stellaris_sys_properties
[] = {
442 DEFINE_PROP_UINT32("user0", ssys_state
, user0
, 0),
443 DEFINE_PROP_UINT32("user1", ssys_state
, user1
, 0),
444 DEFINE_PROP_UINT32("did0", ssys_state
, did0
, 0),
445 DEFINE_PROP_UINT32("did1", ssys_state
, did1
, 0),
446 DEFINE_PROP_UINT32("dc0", ssys_state
, dc0
, 0),
447 DEFINE_PROP_UINT32("dc1", ssys_state
, dc1
, 0),
448 DEFINE_PROP_UINT32("dc2", ssys_state
, dc2
, 0),
449 DEFINE_PROP_UINT32("dc3", ssys_state
, dc3
, 0),
450 DEFINE_PROP_UINT32("dc4", ssys_state
, dc4
, 0),
451 DEFINE_PROP_END_OF_LIST()
454 static void stellaris_sys_instance_init(Object
*obj
)
456 ssys_state
*s
= STELLARIS_SYS(obj
);
457 SysBusDevice
*sbd
= SYS_BUS_DEVICE(s
);
459 memory_region_init_io(&s
->iomem
, obj
, &ssys_ops
, s
, "ssys", 0x00001000);
460 sysbus_init_mmio(sbd
, &s
->iomem
);
461 sysbus_init_irq(sbd
, &s
->irq
);
462 s
->sysclk
= qdev_init_clock_out(DEVICE(s
), "SYSCLK");
467 * ??? For now we only implement the master interface.
470 #define TYPE_STELLARIS_I2C "stellaris-i2c"
471 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state
, STELLARIS_I2C
)
473 struct stellaris_i2c_state
{
474 SysBusDevice parent_obj
;
488 #define STELLARIS_I2C_MCS_BUSY 0x01
489 #define STELLARIS_I2C_MCS_ERROR 0x02
490 #define STELLARIS_I2C_MCS_ADRACK 0x04
491 #define STELLARIS_I2C_MCS_DATACK 0x08
492 #define STELLARIS_I2C_MCS_ARBLST 0x10
493 #define STELLARIS_I2C_MCS_IDLE 0x20
494 #define STELLARIS_I2C_MCS_BUSBSY 0x40
496 static uint64_t stellaris_i2c_read(void *opaque
, hwaddr offset
,
499 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
505 /* We don't emulate timing, so the controller is never busy. */
506 return s
->mcs
| STELLARIS_I2C_MCS_IDLE
;
509 case 0x0c: /* MTPR */
511 case 0x10: /* MIMR */
513 case 0x14: /* MRIS */
515 case 0x18: /* MMIS */
516 return s
->mris
& s
->mimr
;
520 qemu_log_mask(LOG_GUEST_ERROR
,
521 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset
);
526 static void stellaris_i2c_update(stellaris_i2c_state
*s
)
530 level
= (s
->mris
& s
->mimr
) != 0;
531 qemu_set_irq(s
->irq
, level
);
534 static void stellaris_i2c_write(void *opaque
, hwaddr offset
,
535 uint64_t value
, unsigned size
)
537 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
541 s
->msa
= value
& 0xff;
544 if ((s
->mcr
& 0x10) == 0) {
545 /* Disabled. Do nothing. */
548 /* Grab the bus if this is starting a transfer. */
549 if ((value
& 2) && (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
550 if (i2c_start_transfer(s
->bus
, s
->msa
>> 1, s
->msa
& 1)) {
551 s
->mcs
|= STELLARIS_I2C_MCS_ARBLST
;
553 s
->mcs
&= ~STELLARIS_I2C_MCS_ARBLST
;
554 s
->mcs
|= STELLARIS_I2C_MCS_BUSBSY
;
557 /* If we don't have the bus then indicate an error. */
558 if (!i2c_bus_busy(s
->bus
)
559 || (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
560 s
->mcs
|= STELLARIS_I2C_MCS_ERROR
;
563 s
->mcs
&= ~STELLARIS_I2C_MCS_ERROR
;
565 /* Transfer a byte. */
566 /* TODO: Handle errors. */
569 s
->mdr
= i2c_recv(s
->bus
);
572 i2c_send(s
->bus
, s
->mdr
);
574 /* Raise an interrupt. */
578 /* Finish transfer. */
579 i2c_end_transfer(s
->bus
);
580 s
->mcs
&= ~STELLARIS_I2C_MCS_BUSBSY
;
584 s
->mdr
= value
& 0xff;
586 case 0x0c: /* MTPR */
587 s
->mtpr
= value
& 0xff;
589 case 0x10: /* MIMR */
592 case 0x1c: /* MICR */
597 qemu_log_mask(LOG_UNIMP
,
598 "stellaris_i2c: Loopback not implemented\n");
601 qemu_log_mask(LOG_UNIMP
,
602 "stellaris_i2c: Slave mode not implemented\n");
604 s
->mcr
= value
& 0x31;
607 qemu_log_mask(LOG_GUEST_ERROR
,
608 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset
);
610 stellaris_i2c_update(s
);
613 static void stellaris_i2c_reset_enter(Object
*obj
, ResetType type
)
615 stellaris_i2c_state
*s
= STELLARIS_I2C(obj
);
617 if (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
)
618 i2c_end_transfer(s
->bus
);
621 static void stellaris_i2c_reset_hold(Object
*obj
, ResetType type
)
623 stellaris_i2c_state
*s
= STELLARIS_I2C(obj
);
634 static void stellaris_i2c_reset_exit(Object
*obj
, ResetType type
)
636 stellaris_i2c_state
*s
= STELLARIS_I2C(obj
);
638 stellaris_i2c_update(s
);
641 static const MemoryRegionOps stellaris_i2c_ops
= {
642 .read
= stellaris_i2c_read
,
643 .write
= stellaris_i2c_write
,
644 .endianness
= DEVICE_NATIVE_ENDIAN
,
647 static const VMStateDescription vmstate_stellaris_i2c
= {
648 .name
= "stellaris_i2c",
650 .minimum_version_id
= 1,
651 .fields
= (const VMStateField
[]) {
652 VMSTATE_UINT32(msa
, stellaris_i2c_state
),
653 VMSTATE_UINT32(mcs
, stellaris_i2c_state
),
654 VMSTATE_UINT32(mdr
, stellaris_i2c_state
),
655 VMSTATE_UINT32(mtpr
, stellaris_i2c_state
),
656 VMSTATE_UINT32(mimr
, stellaris_i2c_state
),
657 VMSTATE_UINT32(mris
, stellaris_i2c_state
),
658 VMSTATE_UINT32(mcr
, stellaris_i2c_state
),
659 VMSTATE_END_OF_LIST()
663 static void stellaris_i2c_init(Object
*obj
)
665 DeviceState
*dev
= DEVICE(obj
);
666 stellaris_i2c_state
*s
= STELLARIS_I2C(obj
);
667 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
670 sysbus_init_irq(sbd
, &s
->irq
);
671 bus
= i2c_init_bus(dev
, "i2c");
674 memory_region_init_io(&s
->iomem
, obj
, &stellaris_i2c_ops
, s
,
676 sysbus_init_mmio(sbd
, &s
->iomem
);
679 /* Analogue to Digital Converter. This is only partially implemented,
680 enough for applications that use a combined ADC and timer tick. */
682 #define STELLARIS_ADC_EM_CONTROLLER 0
683 #define STELLARIS_ADC_EM_COMP 1
684 #define STELLARIS_ADC_EM_EXTERNAL 4
685 #define STELLARIS_ADC_EM_TIMER 5
686 #define STELLARIS_ADC_EM_PWM0 6
687 #define STELLARIS_ADC_EM_PWM1 7
688 #define STELLARIS_ADC_EM_PWM2 8
690 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
691 #define STELLARIS_ADC_FIFO_FULL 0x1000
693 #define TYPE_STELLARIS_ADC "stellaris-adc"
694 typedef struct StellarisADCState StellarisADCState
;
695 DECLARE_INSTANCE_CHECKER(StellarisADCState
, STELLARIS_ADC
, TYPE_STELLARIS_ADC
)
697 struct StellarisADCState
{
698 SysBusDevice parent_obj
;
719 static uint32_t stellaris_adc_fifo_read(StellarisADCState
*s
, int n
)
723 tail
= s
->fifo
[n
].state
& 0xf;
724 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_EMPTY
) {
727 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf) | ((tail
+ 1) & 0xf);
728 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_FULL
;
729 if (tail
+ 1 == ((s
->fifo
[n
].state
>> 4) & 0xf))
730 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_EMPTY
;
732 return s
->fifo
[n
].data
[tail
];
735 static void stellaris_adc_fifo_write(StellarisADCState
*s
, int n
,
740 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
741 FIFO fir each sequencer. */
742 head
= (s
->fifo
[n
].state
>> 4) & 0xf;
743 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_FULL
) {
747 s
->fifo
[n
].data
[head
] = value
;
748 head
= (head
+ 1) & 0xf;
749 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_EMPTY
;
750 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf0) | (head
<< 4);
751 if ((s
->fifo
[n
].state
& 0xf) == head
)
752 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_FULL
;
755 static void stellaris_adc_update(StellarisADCState
*s
)
760 for (n
= 0; n
< 4; n
++) {
761 level
= (s
->ris
& s
->im
& (1 << n
)) != 0;
762 qemu_set_irq(s
->irq
[n
], level
);
766 static void stellaris_adc_trigger(void *opaque
, int irq
, int level
)
768 StellarisADCState
*s
= opaque
;
771 for (n
= 0; n
< 4; n
++) {
772 if ((s
->actss
& (1 << n
)) == 0) {
776 if (((s
->emux
>> (n
* 4)) & 0xff) != 5) {
780 /* Some applications use the ADC as a random number source, so introduce
781 some variation into the signal. */
782 s
->noise
= s
->noise
* 314159 + 1;
783 /* ??? actual inputs not implemented. Return an arbitrary value. */
784 stellaris_adc_fifo_write(s
, n
, 0x200 + ((s
->noise
>> 16) & 7));
786 stellaris_adc_update(s
);
790 static void stellaris_adc_reset_hold(Object
*obj
, ResetType type
)
792 StellarisADCState
*s
= STELLARIS_ADC(obj
);
795 for (n
= 0; n
< 4; n
++) {
798 s
->fifo
[n
].state
= STELLARIS_ADC_FIFO_EMPTY
;
802 static uint64_t stellaris_adc_read(void *opaque
, hwaddr offset
,
805 StellarisADCState
*s
= opaque
;
807 /* TODO: Implement this. */
808 if (offset
>= 0x40 && offset
< 0xc0) {
810 n
= (offset
- 0x40) >> 5;
811 switch (offset
& 0x1f) {
812 case 0x00: /* SSMUX */
814 case 0x04: /* SSCTL */
816 case 0x08: /* SSFIFO */
817 return stellaris_adc_fifo_read(s
, n
);
818 case 0x0c: /* SSFSTAT */
819 return s
->fifo
[n
].state
;
825 case 0x00: /* ACTSS */
832 return s
->ris
& s
->im
;
833 case 0x10: /* OSTAT */
835 case 0x14: /* EMUX */
837 case 0x18: /* USTAT */
839 case 0x20: /* SSPRI */
844 qemu_log_mask(LOG_GUEST_ERROR
,
845 "stellaris_adc: read at bad offset 0x%x\n", (int)offset
);
850 static void stellaris_adc_write(void *opaque
, hwaddr offset
,
851 uint64_t value
, unsigned size
)
853 StellarisADCState
*s
= opaque
;
855 /* TODO: Implement this. */
856 if (offset
>= 0x40 && offset
< 0xc0) {
858 n
= (offset
- 0x40) >> 5;
859 switch (offset
& 0x1f) {
860 case 0x00: /* SSMUX */
861 s
->ssmux
[n
] = value
& 0x33333333;
863 case 0x04: /* SSCTL */
865 qemu_log_mask(LOG_UNIMP
,
866 "ADC: Unimplemented sequence %" PRIx64
"\n",
876 case 0x00: /* ACTSS */
877 s
->actss
= value
& 0xf;
885 case 0x10: /* OSTAT */
888 case 0x14: /* EMUX */
891 case 0x18: /* USTAT */
894 case 0x20: /* SSPRI */
897 case 0x28: /* PSSI */
898 qemu_log_mask(LOG_UNIMP
, "ADC: sample initiate unimplemented\n");
904 qemu_log_mask(LOG_GUEST_ERROR
,
905 "stellaris_adc: write at bad offset 0x%x\n", (int)offset
);
907 stellaris_adc_update(s
);
910 static const MemoryRegionOps stellaris_adc_ops
= {
911 .read
= stellaris_adc_read
,
912 .write
= stellaris_adc_write
,
913 .endianness
= DEVICE_NATIVE_ENDIAN
,
916 static const VMStateDescription vmstate_stellaris_adc
= {
917 .name
= "stellaris_adc",
919 .minimum_version_id
= 1,
920 .fields
= (const VMStateField
[]) {
921 VMSTATE_UINT32(actss
, StellarisADCState
),
922 VMSTATE_UINT32(ris
, StellarisADCState
),
923 VMSTATE_UINT32(im
, StellarisADCState
),
924 VMSTATE_UINT32(emux
, StellarisADCState
),
925 VMSTATE_UINT32(ostat
, StellarisADCState
),
926 VMSTATE_UINT32(ustat
, StellarisADCState
),
927 VMSTATE_UINT32(sspri
, StellarisADCState
),
928 VMSTATE_UINT32(sac
, StellarisADCState
),
929 VMSTATE_UINT32(fifo
[0].state
, StellarisADCState
),
930 VMSTATE_UINT32_ARRAY(fifo
[0].data
, StellarisADCState
, 16),
931 VMSTATE_UINT32(ssmux
[0], StellarisADCState
),
932 VMSTATE_UINT32(ssctl
[0], StellarisADCState
),
933 VMSTATE_UINT32(fifo
[1].state
, StellarisADCState
),
934 VMSTATE_UINT32_ARRAY(fifo
[1].data
, StellarisADCState
, 16),
935 VMSTATE_UINT32(ssmux
[1], StellarisADCState
),
936 VMSTATE_UINT32(ssctl
[1], StellarisADCState
),
937 VMSTATE_UINT32(fifo
[2].state
, StellarisADCState
),
938 VMSTATE_UINT32_ARRAY(fifo
[2].data
, StellarisADCState
, 16),
939 VMSTATE_UINT32(ssmux
[2], StellarisADCState
),
940 VMSTATE_UINT32(ssctl
[2], StellarisADCState
),
941 VMSTATE_UINT32(fifo
[3].state
, StellarisADCState
),
942 VMSTATE_UINT32_ARRAY(fifo
[3].data
, StellarisADCState
, 16),
943 VMSTATE_UINT32(ssmux
[3], StellarisADCState
),
944 VMSTATE_UINT32(ssctl
[3], StellarisADCState
),
945 VMSTATE_UINT32(noise
, StellarisADCState
),
946 VMSTATE_END_OF_LIST()
950 static void stellaris_adc_init(Object
*obj
)
952 DeviceState
*dev
= DEVICE(obj
);
953 StellarisADCState
*s
= STELLARIS_ADC(obj
);
954 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
957 for (n
= 0; n
< 4; n
++) {
958 sysbus_init_irq(sbd
, &s
->irq
[n
]);
961 memory_region_init_io(&s
->iomem
, obj
, &stellaris_adc_ops
, s
,
963 sysbus_init_mmio(sbd
, &s
->iomem
);
964 qdev_init_gpio_in(dev
, stellaris_adc_trigger
, 1);
968 static stellaris_board_info stellaris_boards
[] = {
972 0x001f001f, /* dc0 */
982 0x00ff007f, /* dc0 */
987 BP_OLED_SSI
| BP_GAMEPAD
991 static void stellaris_init(MachineState
*ms
, stellaris_board_info
*board
)
993 static const int uart_irq
[] = {5, 6, 33, 34};
994 static const int timer_irq
[] = {19, 21, 23, 35};
995 static const uint32_t gpio_addr
[7] =
996 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
997 0x40024000, 0x40025000, 0x40026000};
998 static const int gpio_irq
[7] = {0, 1, 2, 3, 4, 30, 31};
1000 /* Memory map of SoC devices, from
1001 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1002 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1005 * 40002000 i2c (unimplemented)
1015 * 40021000 i2c (unimplemented)
1019 * 40028000 PWM (unimplemented)
1020 * 4002c000 QEI (unimplemented)
1021 * 4002d000 QEI (unimplemented)
1027 * 4003c000 analogue comparator (unimplemented)
1029 * 400fc000 hibernation module (unimplemented)
1030 * 400fd000 flash memory control (unimplemented)
1031 * 400fe000 system control
1034 Object
*soc_container
;
1035 DeviceState
*gpio_dev
[7], *nvic
;
1036 qemu_irq gpio_in
[7][8];
1037 qemu_irq gpio_out
[7][8];
1043 DeviceState
*ssys_dev
;
1049 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
1050 MemoryRegion
*flash
= g_new(MemoryRegion
, 1);
1051 MemoryRegion
*system_memory
= get_system_memory();
1053 flash_size
= (((board
->dc0
& 0xffff) + 1) << 1) * 1024;
1054 sram_size
= ((board
->dc0
>> 18) + 1) * 1024;
1056 soc_container
= object_new("container");
1057 object_property_add_child(OBJECT(ms
), "soc", soc_container
);
1059 /* Flash programming is done via the SCU, so pretend it is ROM. */
1060 memory_region_init_rom(flash
, NULL
, "stellaris.flash", flash_size
,
1062 memory_region_add_subregion(system_memory
, 0, flash
);
1064 memory_region_init_ram(sram
, NULL
, "stellaris.sram", sram_size
,
1066 memory_region_add_subregion(system_memory
, 0x20000000, sram
);
1069 * Create the system-registers object early, because we will
1070 * need its sysclk output.
1072 ssys_dev
= qdev_new(TYPE_STELLARIS_SYS
);
1073 object_property_add_child(soc_container
, "sys", OBJECT(ssys_dev
));
1076 * Most devices come preprogrammed with a MAC address in the user data.
1077 * Generate a MAC address now, if there isn't a matching -nic for it.
1079 nd
= qemu_find_nic_info("stellaris_enet", true, "stellaris");
1081 memcpy(mac
.a
, nd
->macaddr
.a
, sizeof(mac
.a
));
1083 qemu_macaddr_default_if_unset(&mac
);
1086 qdev_prop_set_uint32(ssys_dev
, "user0",
1087 mac
.a
[0] | (mac
.a
[1] << 8) | (mac
.a
[2] << 16));
1088 qdev_prop_set_uint32(ssys_dev
, "user1",
1089 mac
.a
[3] | (mac
.a
[4] << 8) | (mac
.a
[5] << 16));
1090 qdev_prop_set_uint32(ssys_dev
, "did0", board
->did0
);
1091 qdev_prop_set_uint32(ssys_dev
, "did1", board
->did1
);
1092 qdev_prop_set_uint32(ssys_dev
, "dc0", board
->dc0
);
1093 qdev_prop_set_uint32(ssys_dev
, "dc1", board
->dc1
);
1094 qdev_prop_set_uint32(ssys_dev
, "dc2", board
->dc2
);
1095 qdev_prop_set_uint32(ssys_dev
, "dc3", board
->dc3
);
1096 qdev_prop_set_uint32(ssys_dev
, "dc4", board
->dc4
);
1097 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev
), &error_fatal
);
1099 nvic
= qdev_new(TYPE_ARMV7M
);
1100 object_property_add_child(soc_container
, "v7m", OBJECT(nvic
));
1101 qdev_prop_set_uint32(nvic
, "num-irq", NUM_IRQ_LINES
);
1102 qdev_prop_set_uint8(nvic
, "num-prio-bits", NUM_PRIO_BITS
);
1103 qdev_prop_set_string(nvic
, "cpu-type", ms
->cpu_type
);
1104 qdev_prop_set_bit(nvic
, "enable-bitband", true);
1105 qdev_connect_clock_in(nvic
, "cpuclk",
1106 qdev_get_clock_out(ssys_dev
, "SYSCLK"));
1107 /* This SoC does not connect the systick reference clock */
1108 object_property_set_link(OBJECT(nvic
), "memory",
1109 OBJECT(get_system_memory()), &error_abort
);
1110 /* This will exit with an error if the user passed us a bad cpu_type */
1111 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic
), &error_fatal
);
1113 /* Now we can wire up the IRQ and MMIO of the system registers */
1114 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev
), 0, 0x400fe000);
1115 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev
), 0, qdev_get_gpio_in(nvic
, 28));
1117 if (board
->dc1
& (1 << 16)) {
1118 dev
= sysbus_create_varargs(TYPE_STELLARIS_ADC
, 0x40038000,
1119 qdev_get_gpio_in(nvic
, 14),
1120 qdev_get_gpio_in(nvic
, 15),
1121 qdev_get_gpio_in(nvic
, 16),
1122 qdev_get_gpio_in(nvic
, 17),
1124 adc
= qdev_get_gpio_in(dev
, 0);
1128 for (i
= 0; i
< 4; i
++) {
1129 if (board
->dc2
& (0x10000 << i
)) {
1132 dev
= qdev_new(TYPE_STELLARIS_GPTM
);
1133 sbd
= SYS_BUS_DEVICE(dev
);
1134 object_property_add_child(soc_container
, "gptm[*]", OBJECT(dev
));
1135 qdev_connect_clock_in(dev
, "clk",
1136 qdev_get_clock_out(ssys_dev
, "SYSCLK"));
1137 sysbus_realize_and_unref(sbd
, &error_fatal
);
1138 sysbus_mmio_map(sbd
, 0, 0x40030000 + i
* 0x1000);
1139 sysbus_connect_irq(sbd
, 0, qdev_get_gpio_in(nvic
, timer_irq
[i
]));
1140 /* TODO: This is incorrect, but we get away with it because
1141 the ADC output is only ever pulsed. */
1142 qdev_connect_gpio_out(dev
, 0, adc
);
1146 if (board
->dc1
& (1 << 3)) { /* watchdog present */
1147 dev
= qdev_new(TYPE_LUMINARY_WATCHDOG
);
1148 object_property_add_child(soc_container
, "wdg", OBJECT(dev
));
1149 qdev_connect_clock_in(dev
, "WDOGCLK",
1150 qdev_get_clock_out(ssys_dev
, "SYSCLK"));
1152 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1153 sysbus_mmio_map(SYS_BUS_DEVICE(dev
),
1156 sysbus_connect_irq(SYS_BUS_DEVICE(dev
),
1158 qdev_get_gpio_in(nvic
, 18));
1162 for (i
= 0; i
< 7; i
++) {
1163 if (board
->dc4
& (1 << i
)) {
1164 gpio_dev
[i
] = sysbus_create_simple("pl061_luminary", gpio_addr
[i
],
1165 qdev_get_gpio_in(nvic
,
1167 for (j
= 0; j
< 8; j
++) {
1168 gpio_in
[i
][j
] = qdev_get_gpio_in(gpio_dev
[i
], j
);
1169 gpio_out
[i
][j
] = NULL
;
1174 if (board
->dc2
& (1 << 12)) {
1175 dev
= sysbus_create_simple(TYPE_STELLARIS_I2C
, 0x40020000,
1176 qdev_get_gpio_in(nvic
, 8));
1177 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
1178 if (board
->peripherals
& BP_OLED_I2C
) {
1179 i2c_slave_create_simple(i2c
, "ssd0303", 0x3d);
1183 for (i
= 0; i
< 4; i
++) {
1184 if (board
->dc2
& (1 << i
)) {
1187 dev
= qdev_new("pl011_luminary");
1188 object_property_add_child(soc_container
, "uart[*]", OBJECT(dev
));
1189 sbd
= SYS_BUS_DEVICE(dev
);
1190 qdev_prop_set_chr(dev
, "chardev", serial_hd(i
));
1191 sysbus_realize_and_unref(sbd
, &error_fatal
);
1192 sysbus_mmio_map(sbd
, 0, 0x4000c000 + i
* 0x1000);
1193 sysbus_connect_irq(sbd
, 0, qdev_get_gpio_in(nvic
, uart_irq
[i
]));
1196 if (board
->dc2
& (1 << 4)) {
1197 dev
= sysbus_create_simple("pl022", 0x40008000,
1198 qdev_get_gpio_in(nvic
, 7));
1199 if (board
->peripherals
& BP_OLED_SSI
) {
1202 DeviceState
*ssddev
;
1204 DeviceState
*carddev
;
1205 DeviceState
*gpio_d_splitter
;
1209 * Some boards have both an OLED controller and SD card connected to
1210 * the same SSI port, with the SD card chip select connected to a
1211 * GPIO pin. Technically the OLED chip select is connected to the
1212 * SSI Fss pin. We do not bother emulating that as both devices
1213 * should never be selected simultaneously, and our OLED controller
1214 * ignores stray 0xff commands that occur when deselecting the SD
1217 * The h/w wiring is:
1218 * - GPIO pin D0 is wired to the active-low SD card chip select
1219 * - GPIO pin A3 is wired to the active-low OLED chip select
1220 * - The SoC wiring of the PL061 "auxiliary function" for A3 is
1221 * SSI0Fss ("frame signal"), which is an output from the SoC's
1222 * SSI controller. The SSI controller takes SSI0Fss low when it
1223 * transmits a frame, so it can work as a chip-select signal.
1224 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx
1225 * (the OLED never sends data to the CPU, so no wiring needed)
1226 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx
1227 * and the OLED display-data-in
1228 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED
1229 * serial-clock input
1230 * So a guest that wants to use the OLED can configure the PL061
1231 * to make pins A2, A3, A5 aux-function, so they are connected
1232 * directly to the SSI controller. When the SSI controller sends
1233 * data it asserts SSI0Fss which selects the OLED.
1234 * A guest that wants to use the SD card configures A2, A4 and A5
1235 * as aux-function, but leaves A3 as a software-controlled GPIO
1236 * line. It asserts the SD card chip-select by using the PL061
1237 * to control pin D0, and lets the SSI controller handle Clk, Tx
1238 * and Rx. (The SSI controller asserts Fss during tx cycles as
1239 * usual, but because A3 is not set to aux-function this is not
1240 * forwarded to the OLED, and so the OLED stays unselected.)
1242 * The QEMU implementation instead is:
1243 * - GPIO pin D0 is wired to the active-low SD card chip select,
1244 * and also to the OLED chip-select which is implemented
1246 * - SSI controller signals go to the devices regardless of
1247 * whether the guest programs A2, A4, A5 as aux-function or not
1249 * The problem with this implementation is if the guest doesn't
1250 * care about the SD card and only uses the OLED. In that case it
1251 * may choose never to do anything with D0 (leaving it in its
1252 * default floating state, which reliably leaves the card disabled
1253 * because an SD card has a pullup on CS within the card itself),
1254 * and only set up A2, A3, A5. This for us would mean the OLED
1255 * never gets the chip-select assert it needs. We work around
1256 * this with a manual raise of D0 here (despite board creation
1257 * code being the wrong place to raise IRQ lines) to put the OLED
1258 * into an initially selected state.
1260 * In theory the right way to model this would be:
1261 * - Implement aux-function support in the PL061, with an
1262 * extra set of AFIN and AFOUT GPIO lines (set up so that
1263 * if a GPIO line is in auxfn mode the main GPIO in and out
1264 * track the AFIN and AFOUT lines)
1265 * - Wire the AFOUT for D0 up to either a line from the
1266 * SSI controller that's pulled low around every transmit,
1267 * or at least to an always-0 line here on the board
1268 * - Make the ssd0323 OLED controller chipselect active-low
1270 bus
= qdev_get_child_bus(dev
, "ssi");
1271 sddev
= ssi_create_peripheral(bus
, "ssi-sd");
1273 dinfo
= drive_get(IF_SD
, 0, 0);
1274 blk
= dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
;
1275 carddev
= qdev_new(TYPE_SD_CARD_SPI
);
1276 qdev_prop_set_drive_err(carddev
, "drive", blk
, &error_fatal
);
1277 qdev_realize_and_unref(carddev
,
1278 qdev_get_child_bus(sddev
, "sd-bus"),
1281 ssddev
= qdev_new("ssd0323");
1282 object_property_add_child(OBJECT(ms
), "oled", OBJECT(ssddev
));
1283 qdev_prop_set_uint8(ssddev
, "cs", 1);
1284 qdev_realize_and_unref(ssddev
, bus
, &error_fatal
);
1286 gpio_d_splitter
= qdev_new(TYPE_SPLIT_IRQ
);
1287 object_property_add_child(OBJECT(ms
), "splitter",
1288 OBJECT(gpio_d_splitter
));
1289 qdev_prop_set_uint32(gpio_d_splitter
, "num-lines", 2);
1290 qdev_realize_and_unref(gpio_d_splitter
, NULL
, &error_fatal
);
1291 qdev_connect_gpio_out(
1293 qdev_get_gpio_in_named(sddev
, SSI_GPIO_CS
, 0));
1294 qdev_connect_gpio_out(
1296 qdev_get_gpio_in_named(ssddev
, SSI_GPIO_CS
, 0));
1297 gpio_out
[GPIO_D
][0] = qdev_get_gpio_in(gpio_d_splitter
, 0);
1299 gpio_out
[GPIO_C
][7] = qdev_get_gpio_in(ssddev
, 0);
1301 /* Make sure the select pin is high. */
1302 qemu_irq_raise(gpio_out
[GPIO_D
][0]);
1305 if (board
->dc4
& (1 << 28)) {
1308 enet
= qdev_new("stellaris_enet");
1309 object_property_add_child(soc_container
, "enet", OBJECT(enet
));
1311 qdev_set_nic_properties(enet
, nd
);
1313 qdev_prop_set_macaddr(enet
, "mac", mac
.a
);
1316 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet
), &error_fatal
);
1317 sysbus_mmio_map(SYS_BUS_DEVICE(enet
), 0, 0x40048000);
1318 sysbus_connect_irq(SYS_BUS_DEVICE(enet
), 0, qdev_get_gpio_in(nvic
, 42));
1320 if (board
->peripherals
& BP_GAMEPAD
) {
1321 QList
*gpad_keycode_list
= qlist_new();
1322 static const int gpad_keycode
[5] = {
1323 Q_KEY_CODE_UP
, Q_KEY_CODE_DOWN
, Q_KEY_CODE_LEFT
,
1324 Q_KEY_CODE_RIGHT
, Q_KEY_CODE_CTRL
,
1328 gpad
= qdev_new(TYPE_STELLARIS_GAMEPAD
);
1329 object_property_add_child(OBJECT(ms
), "gamepad", OBJECT(gpad
));
1330 for (i
= 0; i
< ARRAY_SIZE(gpad_keycode
); i
++) {
1331 qlist_append_int(gpad_keycode_list
, gpad_keycode
[i
]);
1333 qdev_prop_set_array(gpad
, "keycodes", gpad_keycode_list
);
1334 sysbus_realize_and_unref(SYS_BUS_DEVICE(gpad
), &error_fatal
);
1336 qdev_connect_gpio_out(gpad
, 0,
1337 qemu_irq_invert(gpio_in
[GPIO_E
][0])); /* up */
1338 qdev_connect_gpio_out(gpad
, 1,
1339 qemu_irq_invert(gpio_in
[GPIO_E
][1])); /* down */
1340 qdev_connect_gpio_out(gpad
, 2,
1341 qemu_irq_invert(gpio_in
[GPIO_E
][2])); /* left */
1342 qdev_connect_gpio_out(gpad
, 3,
1343 qemu_irq_invert(gpio_in
[GPIO_E
][3])); /* right */
1344 qdev_connect_gpio_out(gpad
, 4,
1345 qemu_irq_invert(gpio_in
[GPIO_F
][1])); /* select */
1347 for (i
= 0; i
< 7; i
++) {
1348 if (board
->dc4
& (1 << i
)) {
1349 for (j
= 0; j
< 8; j
++) {
1350 if (gpio_out
[i
][j
]) {
1351 qdev_connect_gpio_out(gpio_dev
[i
], j
, gpio_out
[i
][j
]);
1357 /* Add dummy regions for the devices we don't implement yet,
1358 * so guest accesses don't cause unlogged crashes.
1360 create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1361 create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1362 create_unimplemented_device("PWM", 0x40028000, 0x1000);
1363 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1364 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1365 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1366 create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1367 create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1369 armv7m_load_kernel(ARM_CPU(first_cpu
), ms
->kernel_filename
, 0, flash_size
);
1372 /* FIXME: Figure out how to generate these from stellaris_boards. */
1373 static void lm3s811evb_init(MachineState
*machine
)
1375 stellaris_init(machine
, &stellaris_boards
[0]);
1378 static void lm3s6965evb_init(MachineState
*machine
)
1380 stellaris_init(machine
, &stellaris_boards
[1]);
1383 static void lm3s811evb_class_init(ObjectClass
*oc
, void *data
)
1385 MachineClass
*mc
= MACHINE_CLASS(oc
);
1387 mc
->desc
= "Stellaris LM3S811EVB (Cortex-M3)";
1388 mc
->init
= lm3s811evb_init
;
1389 mc
->ignore_memory_transaction_failures
= true;
1390 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
1393 static const TypeInfo lm3s811evb_type
= {
1394 .name
= MACHINE_TYPE_NAME("lm3s811evb"),
1395 .parent
= TYPE_MACHINE
,
1396 .class_init
= lm3s811evb_class_init
,
1399 static void lm3s6965evb_class_init(ObjectClass
*oc
, void *data
)
1401 MachineClass
*mc
= MACHINE_CLASS(oc
);
1403 mc
->desc
= "Stellaris LM3S6965EVB (Cortex-M3)";
1404 mc
->init
= lm3s6965evb_init
;
1405 mc
->ignore_memory_transaction_failures
= true;
1406 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
1409 static const TypeInfo lm3s6965evb_type
= {
1410 .name
= MACHINE_TYPE_NAME("lm3s6965evb"),
1411 .parent
= TYPE_MACHINE
,
1412 .class_init
= lm3s6965evb_class_init
,
1415 static void stellaris_machine_init(void)
1417 type_register_static(&lm3s811evb_type
);
1418 type_register_static(&lm3s6965evb_type
);
1421 type_init(stellaris_machine_init
)
1423 static void stellaris_i2c_class_init(ObjectClass
*klass
, void *data
)
1425 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1426 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
1428 rc
->phases
.enter
= stellaris_i2c_reset_enter
;
1429 rc
->phases
.hold
= stellaris_i2c_reset_hold
;
1430 rc
->phases
.exit
= stellaris_i2c_reset_exit
;
1431 dc
->vmsd
= &vmstate_stellaris_i2c
;
1434 static const TypeInfo stellaris_i2c_info
= {
1435 .name
= TYPE_STELLARIS_I2C
,
1436 .parent
= TYPE_SYS_BUS_DEVICE
,
1437 .instance_size
= sizeof(stellaris_i2c_state
),
1438 .instance_init
= stellaris_i2c_init
,
1439 .class_init
= stellaris_i2c_class_init
,
1442 static void stellaris_adc_class_init(ObjectClass
*klass
, void *data
)
1444 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1445 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
1447 rc
->phases
.hold
= stellaris_adc_reset_hold
;
1448 dc
->vmsd
= &vmstate_stellaris_adc
;
1451 static const TypeInfo stellaris_adc_info
= {
1452 .name
= TYPE_STELLARIS_ADC
,
1453 .parent
= TYPE_SYS_BUS_DEVICE
,
1454 .instance_size
= sizeof(StellarisADCState
),
1455 .instance_init
= stellaris_adc_init
,
1456 .class_init
= stellaris_adc_class_init
,
1459 static void stellaris_sys_class_init(ObjectClass
*klass
, void *data
)
1461 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1462 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
1464 dc
->vmsd
= &vmstate_stellaris_sys
;
1465 rc
->phases
.enter
= stellaris_sys_reset_enter
;
1466 rc
->phases
.hold
= stellaris_sys_reset_hold
;
1467 rc
->phases
.exit
= stellaris_sys_reset_exit
;
1468 device_class_set_props(dc
, stellaris_sys_properties
);
1471 static const TypeInfo stellaris_sys_info
= {
1472 .name
= TYPE_STELLARIS_SYS
,
1473 .parent
= TYPE_SYS_BUS_DEVICE
,
1474 .instance_size
= sizeof(ssys_state
),
1475 .instance_init
= stellaris_sys_instance_init
,
1476 .class_init
= stellaris_sys_class_init
,
1479 static void stellaris_register_types(void)
1481 type_register_static(&stellaris_i2c_info
);
1482 type_register_static(&stellaris_adc_info
);
1483 type_register_static(&stellaris_sys_info
);
1486 type_init(stellaris_register_types
)