hw/arm/stm32l4x5_soc.c

   1 /*
   2  * STM32L4x5 SoC family
   3  *
   4  * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
   5  * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
   6  *
   7  * SPDX-License-Identifier: GPL-2.0-or-later
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  *
  12  * This work is heavily inspired by the stm32f405_soc by Alistair Francis.
  13  * Original code is licensed under the MIT License:
  14  *
  15  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
  16  */
  17
  18 /*
  19  * The reference used is the STMicroElectronics RM0351 Reference manual
  20  * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
  21  * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qemu/units.h"
  26 #include "qapi/error.h"
  27 #include "exec/address-spaces.h"
  28 #include "sysemu/sysemu.h"
  29 #include "hw/arm/stm32l4x5_soc.h"
  30 #include "hw/qdev-clock.h"
  31 #include "hw/misc/unimp.h"
  32
  33 #define FLASH_BASE_ADDRESS 0x08000000
  34 #define SRAM1_BASE_ADDRESS 0x20000000
  35 #define SRAM1_SIZE (96 * KiB)
  36 #define SRAM2_BASE_ADDRESS 0x10000000
  37 #define SRAM2_SIZE (32 * KiB)
  38
  39 #define EXTI_ADDR 0x40010400
  40
  41 #define NUM_EXTI_IRQ 40
  42 /* Match exti line connections with their CPU IRQ number */
  43 /* See Vector Table (Reference Manual p.396) */
  44 static const int exti_irq[NUM_EXTI_IRQ] = {
  45     6,                      /* GPIO[0]                 */
  46     7,                      /* GPIO[1]                 */
  47     8,                      /* GPIO[2]                 */
  48     9,                      /* GPIO[3]                 */
  49     10,                     /* GPIO[4]                 */
  50     23, 23, 23, 23, 23,     /* GPIO[5..9]              */
  51     40, 40, 40, 40, 40, 40, /* GPIO[10..15]            */
  52     1,                      /* PVD                     */
  53     67,                     /* OTG_FS_WKUP, Direct     */
  54     41,                     /* RTC_ALARM               */
  55     2,                      /* RTC_TAMP_STAMP2/CSS_LSE */
  56     3,                      /* RTC wakeup timer        */
  57     63,                     /* COMP1                   */
  58     63,                     /* COMP2                   */
  59     31,                     /* I2C1 wakeup, Direct     */
  60     33,                     /* I2C2 wakeup, Direct     */
  61     72,                     /* I2C3 wakeup, Direct     */
  62     37,                     /* USART1 wakeup, Direct   */
  63     38,                     /* USART2 wakeup, Direct   */
  64     39,                     /* USART3 wakeup, Direct   */
  65     52,                     /* UART4 wakeup, Direct    */
  66     53,                     /* UART4 wakeup, Direct    */
  67     70,                     /* LPUART1 wakeup, Direct  */
  68     65,                     /* LPTIM1, Direct          */
  69     66,                     /* LPTIM2, Direct          */
  70     76,                     /* SWPMI1 wakeup, Direct   */
  71     1,                      /* PVM1 wakeup             */
  72     1,                      /* PVM2 wakeup             */
  73     1,                      /* PVM3 wakeup             */
  74     1,                      /* PVM4 wakeup             */
  75     78                      /* LCD wakeup, Direct      */
  76 };
  77
  78 static void stm32l4x5_soc_initfn(Object *obj)
  79 {
  80     Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
  81
  82     object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI);
  83
  84     s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
  85     s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
  86 }
  87
  88 static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
  89 {
  90     ERRP_GUARD();
  91     Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc);
  92     const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc);
  93     MemoryRegion *system_memory = get_system_memory();
  94     DeviceState *armv7m;
  95     SysBusDevice *busdev;
  96
  97     /*
  98      * We use s->refclk internally and only define it with qdev_init_clock_in()
  99      * so it is correctly parented and not leaked on an init/deinit; it is not
 100      * intended as an externally exposed clock.
 101      */
 102     if (clock_has_source(s->refclk)) {
 103         error_setg(errp, "refclk clock must not be wired up by the board code");
 104         return;
 105     }
 106
 107     if (!clock_has_source(s->sysclk)) {
 108         error_setg(errp, "sysclk clock must be wired up by the board code");
 109         return;
 110     }
 111
 112     /*
 113      * TODO: ideally we should model the SoC RCC and its ability to
 114      * change the sysclk frequency and define different sysclk sources.
 115      */
 116
 117     /* The refclk always runs at frequency HCLK / 8 */
 118     clock_set_mul_div(s->refclk, 8, 1);
 119     clock_set_source(s->refclk, s->sysclk);
 120
 121     if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",
 122                                 sc->flash_size, errp)) {
 123         return;
 124     }
 125     memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
 126                              "flash_boot_alias", &s->flash, 0,
 127                              sc->flash_size);
 128
 129     memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
 130     memory_region_add_subregion(system_memory, 0, &s->flash_alias);
 131
 132     if (!memory_region_init_ram(&s->sram1, OBJECT(dev_soc), "SRAM1", SRAM1_SIZE,
 133                                 errp)) {
 134         return;
 135     }
 136     memory_region_add_subregion(system_memory, SRAM1_BASE_ADDRESS, &s->sram1);
 137
 138     if (!memory_region_init_ram(&s->sram2, OBJECT(dev_soc), "SRAM2", SRAM2_SIZE,
 139                                 errp)) {
 140         return;
 141     }
 142     memory_region_add_subregion(system_memory, SRAM2_BASE_ADDRESS, &s->sram2);
 143
 144     object_initialize_child(OBJECT(dev_soc), "armv7m", &s->armv7m, TYPE_ARMV7M);
 145     armv7m = DEVICE(&s->armv7m);
 146     qdev_prop_set_uint32(armv7m, "num-irq", 96);
 147     qdev_prop_set_uint32(armv7m, "num-prio-bits", 4);
 148     qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
 149     qdev_prop_set_bit(armv7m, "enable-bitband", true);
 150     qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
 151     qdev_connect_clock_in(armv7m, "refclk", s->refclk);
 152     object_property_set_link(OBJECT(&s->armv7m), "memory",
 153                              OBJECT(system_memory), &error_abort);
 154     if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
 155         return;
 156     }
 157
 158     busdev = SYS_BUS_DEVICE(&s->exti);
 159     if (!sysbus_realize(busdev, errp)) {
 160         return;
 161     }
 162     sysbus_mmio_map(busdev, 0, EXTI_ADDR);
 163     for (unsigned i = 0; i < NUM_EXTI_IRQ; i++) {
 164         sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
 165     }
 166
 167     /* APB1 BUS */
 168     create_unimplemented_device("TIM2",      0x40000000, 0x400);
 169     create_unimplemented_device("TIM3",      0x40000400, 0x400);
 170     create_unimplemented_device("TIM4",      0x40000800, 0x400);
 171     create_unimplemented_device("TIM5",      0x40000C00, 0x400);
 172     create_unimplemented_device("TIM6",      0x40001000, 0x400);
 173     create_unimplemented_device("TIM7",      0x40001400, 0x400);
 174     /* RESERVED:    0x40001800, 0x1000 */
 175     create_unimplemented_device("RTC",       0x40002800, 0x400);
 176     create_unimplemented_device("WWDG",      0x40002C00, 0x400);
 177     create_unimplemented_device("IWDG",      0x40003000, 0x400);
 178     /* RESERVED:    0x40001800, 0x400 */
 179     create_unimplemented_device("SPI2",      0x40003800, 0x400);
 180     create_unimplemented_device("SPI3",      0x40003C00, 0x400);
 181     /* RESERVED:    0x40004000, 0x400 */
 182     create_unimplemented_device("USART2",    0x40004400, 0x400);
 183     create_unimplemented_device("USART3",    0x40004800, 0x400);
 184     create_unimplemented_device("UART4",     0x40004C00, 0x400);
 185     create_unimplemented_device("UART5",     0x40005000, 0x400);
 186     create_unimplemented_device("I2C1",      0x40005400, 0x400);
 187     create_unimplemented_device("I2C2",      0x40005800, 0x400);
 188     create_unimplemented_device("I2C3",      0x40005C00, 0x400);
 189     /* RESERVED:    0x40006000, 0x400 */
 190     create_unimplemented_device("CAN1",      0x40006400, 0x400);
 191     /* RESERVED:    0x40006800, 0x400 */
 192     create_unimplemented_device("PWR",       0x40007000, 0x400);
 193     create_unimplemented_device("DAC1",      0x40007400, 0x400);
 194     create_unimplemented_device("OPAMP",     0x40007800, 0x400);
 195     create_unimplemented_device("LPTIM1",    0x40007C00, 0x400);
 196     create_unimplemented_device("LPUART1",   0x40008000, 0x400);
 197     /* RESERVED:    0x40008400, 0x400 */
 198     create_unimplemented_device("SWPMI1",    0x40008800, 0x400);
 199     /* RESERVED:    0x40008C00, 0x800 */
 200     create_unimplemented_device("LPTIM2",    0x40009400, 0x400);
 201     /* RESERVED:    0x40009800, 0x6800 */
 202
 203     /* APB2 BUS */
 204     create_unimplemented_device("SYSCFG",    0x40010000, 0x30);
 205     create_unimplemented_device("VREFBUF",   0x40010030, 0x1D0);
 206     create_unimplemented_device("COMP",      0x40010200, 0x200);
 207     /* RESERVED:    0x40010800, 0x1400 */
 208     create_unimplemented_device("FIREWALL",  0x40011C00, 0x400);
 209     /* RESERVED:    0x40012000, 0x800 */
 210     create_unimplemented_device("SDMMC1",    0x40012800, 0x400);
 211     create_unimplemented_device("TIM1",      0x40012C00, 0x400);
 212     create_unimplemented_device("SPI1",      0x40013000, 0x400);
 213     create_unimplemented_device("TIM8",      0x40013400, 0x400);
 214     create_unimplemented_device("USART1",    0x40013800, 0x400);
 215     /* RESERVED:    0x40013C00, 0x400 */
 216     create_unimplemented_device("TIM15",     0x40014000, 0x400);
 217     create_unimplemented_device("TIM16",     0x40014400, 0x400);
 218     create_unimplemented_device("TIM17",     0x40014800, 0x400);
 219     /* RESERVED:    0x40014C00, 0x800 */
 220     create_unimplemented_device("SAI1",      0x40015400, 0x400);
 221     create_unimplemented_device("SAI2",      0x40015800, 0x400);
 222     /* RESERVED:    0x40015C00, 0x400 */
 223     create_unimplemented_device("DFSDM1",    0x40016000, 0x400);
 224     /* RESERVED:    0x40016400, 0x9C00 */
 225
 226     /* AHB1 BUS */
 227     create_unimplemented_device("DMA1",      0x40020000, 0x400);
 228     create_unimplemented_device("DMA2",      0x40020400, 0x400);
 229     /* RESERVED:    0x40020800, 0x800 */
 230     create_unimplemented_device("RCC",       0x40021000, 0x400);
 231     /* RESERVED:    0x40021400, 0xC00 */
 232     create_unimplemented_device("FLASH",     0x40022000, 0x400);
 233     /* RESERVED:    0x40022400, 0xC00 */
 234     create_unimplemented_device("CRC",       0x40023000, 0x400);
 235     /* RESERVED:    0x40023400, 0x400 */
 236     create_unimplemented_device("TSC",       0x40024000, 0x400);
 237
 238     /* RESERVED:    0x40024400, 0x7FDBC00 */
 239
 240     /* AHB2 BUS */
 241     create_unimplemented_device("GPIOA",     0x48000000, 0x400);
 242     create_unimplemented_device("GPIOB",     0x48000400, 0x400);
 243     create_unimplemented_device("GPIOC",     0x48000800, 0x400);
 244     create_unimplemented_device("GPIOD",     0x48000C00, 0x400);
 245     create_unimplemented_device("GPIOE",     0x48001000, 0x400);
 246     create_unimplemented_device("GPIOF",     0x48001400, 0x400);
 247     create_unimplemented_device("GPIOG",     0x48001800, 0x400);
 248     create_unimplemented_device("GPIOH",     0x48001C00, 0x400);
 249     /* RESERVED:    0x48002000, 0x7FDBC00 */
 250     create_unimplemented_device("OTG_FS",    0x50000000, 0x40000);
 251     create_unimplemented_device("ADC",       0x50040000, 0x400);
 252     /* RESERVED:    0x50040400, 0x20400 */
 253     create_unimplemented_device("RNG",       0x50060800, 0x400);
 254
 255     /* AHB3 BUS */
 256     create_unimplemented_device("FMC",       0xA0000000, 0x1000);
 257     create_unimplemented_device("QUADSPI",   0xA0001000, 0x400);
 258 }
 259
 260 static void stm32l4x5_soc_class_init(ObjectClass *klass, void *data)
 261 {
 262
 263     DeviceClass *dc = DEVICE_CLASS(klass);
 264
 265     dc->realize = stm32l4x5_soc_realize;
 266     /* Reason: Mapped at fixed location on the system bus */
 267     dc->user_creatable = false;
 268     /* No vmstate or reset required: device has no internal state */
 269 }
 270
 271 static void stm32l4x5xc_soc_class_init(ObjectClass *oc, void *data)
 272 {
 273     Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc);
 274
 275     ssc->flash_size = 256 * KiB;
 276 }
 277
 278 static void stm32l4x5xe_soc_class_init(ObjectClass *oc, void *data)
 279 {
 280     Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc);
 281
 282     ssc->flash_size = 512 * KiB;
 283 }
 284
 285 static void stm32l4x5xg_soc_class_init(ObjectClass *oc, void *data)
 286 {
 287     Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc);
 288
 289     ssc->flash_size = 1 * MiB;
 290 }
 291
 292 static const TypeInfo stm32l4x5_soc_types[] = {
 293     {
 294         .name           = TYPE_STM32L4X5XC_SOC,
 295         .parent         = TYPE_STM32L4X5_SOC,
 296         .class_init     = stm32l4x5xc_soc_class_init,
 297     }, {
 298         .name           = TYPE_STM32L4X5XE_SOC,
 299         .parent         = TYPE_STM32L4X5_SOC,
 300         .class_init     = stm32l4x5xe_soc_class_init,
 301     }, {
 302         .name           = TYPE_STM32L4X5XG_SOC,
 303         .parent         = TYPE_STM32L4X5_SOC,
 304         .class_init     = stm32l4x5xg_soc_class_init,
 305     }, {
 306         .name           = TYPE_STM32L4X5_SOC,
 307         .parent         = TYPE_SYS_BUS_DEVICE,
 308         .instance_size  = sizeof(Stm32l4x5SocState),
 309         .instance_init  = stm32l4x5_soc_initfn,
 310         .class_size     = sizeof(Stm32l4x5SocClass),
 311         .class_init     = stm32l4x5_soc_class_init,
 312         .abstract       = true,
 313     }
 314 };
 315
 316 DEFINE_TYPES(stm32l4x5_soc_types)