hw/arm/strongarm.c

   1 /*
   2  * StrongARM SA-1100/SA-1110 emulation
   3  *
   4  * Copyright (C) 2011 Dmitry Eremin-Solenikov
   5  *
   6  * Largely based on StrongARM emulation:
   7  * Copyright (c) 2006 Openedhand Ltd.
   8  * Written by Andrzej Zaborowski <balrog@zabor.org>
   9  *
  10  * UART code based on QEMU 16550A UART emulation
  11  * Copyright (c) 2003-2004 Fabrice Bellard
  12  * Copyright (c) 2008 Citrix Systems, Inc.
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License version 2 as
  16  *  published by the Free Software Foundation.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License along
  24  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  25  *
  26  *  Contributions after 2012-01-13 are licensed under the terms of the
  27  *  GNU GPL, version 2 or (at your option) any later version.
  28  */
  29 #include "hw/sysbus.h"
  30 #include "strongarm.h"
  31 #include "qemu/error-report.h"
  32 #include "hw/arm/arm.h"
  33 #include "sysemu/char.h"
  34 #include "sysemu/sysemu.h"
  35 #include "hw/ssi.h"
  36
  37 //#define DEBUG
  38
  39 /*
  40  TODO
  41  - Implement cp15, c14 ?
  42  - Implement cp15, c15 !!! (idle used in L)
  43  - Implement idle mode handling/DIM
  44  - Implement sleep mode/Wake sources
  45  - Implement reset control
  46  - Implement memory control regs
  47  - PCMCIA handling
  48  - Maybe support MBGNT/MBREQ
  49  - DMA channels
  50  - GPCLK
  51  - IrDA
  52  - MCP
  53  - Enhance UART with modem signals
  54  */
  55
  56 #ifdef DEBUG
  57 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
  58 #else
  59 # define DPRINTF(format, ...) do { } while (0)
  60 #endif
  61
  62 static struct {
  63     hwaddr io_base;
  64     int irq;
  65 } sa_serial[] = {
  66     { 0x80010000, SA_PIC_UART1 },
  67     { 0x80030000, SA_PIC_UART2 },
  68     { 0x80050000, SA_PIC_UART3 },
  69     { 0, 0 }
  70 };
  71
  72 /* Interrupt Controller */
  73 typedef struct {
  74     SysBusDevice busdev;
  75     MemoryRegion iomem;
  76     qemu_irq    irq;
  77     qemu_irq    fiq;
  78
  79     uint32_t pending;
  80     uint32_t enabled;
  81     uint32_t is_fiq;
  82     uint32_t int_idle;
  83 } StrongARMPICState;
  84
  85 #define ICIP    0x00
  86 #define ICMR    0x04
  87 #define ICLR    0x08
  88 #define ICFP    0x10
  89 #define ICPR    0x20
  90 #define ICCR    0x0c
  91
  92 #define SA_PIC_SRCS     32
  93
  94
  95 static void strongarm_pic_update(void *opaque)
  96 {
  97     StrongARMPICState *s = opaque;
  98
  99     /* FIXME: reflect DIM */
 100     qemu_set_irq(s->fiq, s->pending & s->enabled &  s->is_fiq);
 101     qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
 102 }
 103
 104 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
 105 {
 106     StrongARMPICState *s = opaque;
 107
 108     if (level) {
 109         s->pending |= 1 << irq;
 110     } else {
 111         s->pending &= ~(1 << irq);
 112     }
 113
 114     strongarm_pic_update(s);
 115 }
 116
 117 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
 118                                        unsigned size)
 119 {
 120     StrongARMPICState *s = opaque;
 121
 122     switch (offset) {
 123     case ICIP:
 124         return s->pending & ~s->is_fiq & s->enabled;
 125     case ICMR:
 126         return s->enabled;
 127     case ICLR:
 128         return s->is_fiq;
 129     case ICCR:
 130         return s->int_idle == 0;
 131     case ICFP:
 132         return s->pending & s->is_fiq & s->enabled;
 133     case ICPR:
 134         return s->pending;
 135     default:
 136         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 137                         __func__, offset);
 138         return 0;
 139     }
 140 }
 141
 142 static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
 143                                     uint64_t value, unsigned size)
 144 {
 145     StrongARMPICState *s = opaque;
 146
 147     switch (offset) {
 148     case ICMR:
 149         s->enabled = value;
 150         break;
 151     case ICLR:
 152         s->is_fiq = value;
 153         break;
 154     case ICCR:
 155         s->int_idle = (value & 1) ? 0 : ~0;
 156         break;
 157     default:
 158         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 159                         __func__, offset);
 160         break;
 161     }
 162     strongarm_pic_update(s);
 163 }
 164
 165 static const MemoryRegionOps strongarm_pic_ops = {
 166     .read = strongarm_pic_mem_read,
 167     .write = strongarm_pic_mem_write,
 168     .endianness = DEVICE_NATIVE_ENDIAN,
 169 };
 170
 171 static int strongarm_pic_initfn(SysBusDevice *dev)
 172 {
 173     StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);
 174
 175     qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);
 176     memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_pic_ops, s,
 177                           "pic", 0x1000);
 178     sysbus_init_mmio(dev, &s->iomem);
 179     sysbus_init_irq(dev, &s->irq);
 180     sysbus_init_irq(dev, &s->fiq);
 181
 182     return 0;
 183 }
 184
 185 static int strongarm_pic_post_load(void *opaque, int version_id)
 186 {
 187     strongarm_pic_update(opaque);
 188     return 0;
 189 }
 190
 191 static VMStateDescription vmstate_strongarm_pic_regs = {
 192     .name = "strongarm_pic",
 193     .version_id = 0,
 194     .minimum_version_id = 0,
 195     .minimum_version_id_old = 0,
 196     .post_load = strongarm_pic_post_load,
 197     .fields = (VMStateField[]) {
 198         VMSTATE_UINT32(pending, StrongARMPICState),
 199         VMSTATE_UINT32(enabled, StrongARMPICState),
 200         VMSTATE_UINT32(is_fiq, StrongARMPICState),
 201         VMSTATE_UINT32(int_idle, StrongARMPICState),
 202         VMSTATE_END_OF_LIST(),
 203     },
 204 };
 205
 206 static void strongarm_pic_class_init(ObjectClass *klass, void *data)
 207 {
 208     DeviceClass *dc = DEVICE_CLASS(klass);
 209     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 210
 211     k->init = strongarm_pic_initfn;
 212     dc->desc = "StrongARM PIC";
 213     dc->vmsd = &vmstate_strongarm_pic_regs;
 214 }
 215
 216 static const TypeInfo strongarm_pic_info = {
 217     .name          = "strongarm_pic",
 218     .parent        = TYPE_SYS_BUS_DEVICE,
 219     .instance_size = sizeof(StrongARMPICState),
 220     .class_init    = strongarm_pic_class_init,
 221 };
 222
 223 /* Real-Time Clock */
 224 #define RTAR 0x00 /* RTC Alarm register */
 225 #define RCNR 0x04 /* RTC Counter register */
 226 #define RTTR 0x08 /* RTC Timer Trim register */
 227 #define RTSR 0x10 /* RTC Status register */
 228
 229 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
 230 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
 231 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
 232 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
 233
 234 /* 16 LSB of RTTR are clockdiv for internal trim logic,
 235  * trim delete isn't emulated, so
 236  * f = 32 768 / (RTTR_trim + 1) */
 237
 238 typedef struct {
 239     SysBusDevice busdev;
 240     MemoryRegion iomem;
 241     uint32_t rttr;
 242     uint32_t rtsr;
 243     uint32_t rtar;
 244     uint32_t last_rcnr;
 245     int64_t last_hz;
 246     QEMUTimer *rtc_alarm;
 247     QEMUTimer *rtc_hz;
 248     qemu_irq rtc_irq;
 249     qemu_irq rtc_hz_irq;
 250 } StrongARMRTCState;
 251
 252 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
 253 {
 254     qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
 255     qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
 256 }
 257
 258 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
 259 {
 260     int64_t rt = qemu_get_clock_ms(rtc_clock);
 261     s->last_rcnr += ((rt - s->last_hz) << 15) /
 262             (1000 * ((s->rttr & 0xffff) + 1));
 263     s->last_hz = rt;
 264 }
 265
 266 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
 267 {
 268     if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
 269         qemu_mod_timer(s->rtc_hz, s->last_hz + 1000);
 270     } else {
 271         qemu_del_timer(s->rtc_hz);
 272     }
 273
 274     if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
 275         qemu_mod_timer(s->rtc_alarm, s->last_hz +
 276                 (((s->rtar - s->last_rcnr) * 1000 *
 277                   ((s->rttr & 0xffff) + 1)) >> 15));
 278     } else {
 279         qemu_del_timer(s->rtc_alarm);
 280     }
 281 }
 282
 283 static inline void strongarm_rtc_alarm_tick(void *opaque)
 284 {
 285     StrongARMRTCState *s = opaque;
 286     s->rtsr |= RTSR_AL;
 287     strongarm_rtc_timer_update(s);
 288     strongarm_rtc_int_update(s);
 289 }
 290
 291 static inline void strongarm_rtc_hz_tick(void *opaque)
 292 {
 293     StrongARMRTCState *s = opaque;
 294     s->rtsr |= RTSR_HZ;
 295     strongarm_rtc_timer_update(s);
 296     strongarm_rtc_int_update(s);
 297 }
 298
 299 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
 300                                    unsigned size)
 301 {
 302     StrongARMRTCState *s = opaque;
 303
 304     switch (addr) {
 305     case RTTR:
 306         return s->rttr;
 307     case RTSR:
 308         return s->rtsr;
 309     case RTAR:
 310         return s->rtar;
 311     case RCNR:
 312         return s->last_rcnr +
 313                 ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
 314                 (1000 * ((s->rttr & 0xffff) + 1));
 315     default:
 316         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 317         return 0;
 318     }
 319 }
 320
 321 static void strongarm_rtc_write(void *opaque, hwaddr addr,
 322                                 uint64_t value, unsigned size)
 323 {
 324     StrongARMRTCState *s = opaque;
 325     uint32_t old_rtsr;
 326
 327     switch (addr) {
 328     case RTTR:
 329         strongarm_rtc_hzupdate(s);
 330         s->rttr = value;
 331         strongarm_rtc_timer_update(s);
 332         break;
 333
 334     case RTSR:
 335         old_rtsr = s->rtsr;
 336         s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
 337                   (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
 338
 339         if (s->rtsr != old_rtsr) {
 340             strongarm_rtc_timer_update(s);
 341         }
 342
 343         strongarm_rtc_int_update(s);
 344         break;
 345
 346     case RTAR:
 347         s->rtar = value;
 348         strongarm_rtc_timer_update(s);
 349         break;
 350
 351     case RCNR:
 352         strongarm_rtc_hzupdate(s);
 353         s->last_rcnr = value;
 354         strongarm_rtc_timer_update(s);
 355         break;
 356
 357     default:
 358         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 359     }
 360 }
 361
 362 static const MemoryRegionOps strongarm_rtc_ops = {
 363     .read = strongarm_rtc_read,
 364     .write = strongarm_rtc_write,
 365     .endianness = DEVICE_NATIVE_ENDIAN,
 366 };
 367
 368 static int strongarm_rtc_init(SysBusDevice *dev)
 369 {
 370     StrongARMRTCState *s = FROM_SYSBUS(StrongARMRTCState, dev);
 371     struct tm tm;
 372
 373     s->rttr = 0x0;
 374     s->rtsr = 0;
 375
 376     qemu_get_timedate(&tm, 0);
 377
 378     s->last_rcnr = (uint32_t) mktimegm(&tm);
 379     s->last_hz = qemu_get_clock_ms(rtc_clock);
 380
 381     s->rtc_alarm = qemu_new_timer_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
 382     s->rtc_hz = qemu_new_timer_ms(rtc_clock, strongarm_rtc_hz_tick, s);
 383
 384     sysbus_init_irq(dev, &s->rtc_irq);
 385     sysbus_init_irq(dev, &s->rtc_hz_irq);
 386
 387     memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_rtc_ops, s,
 388                           "rtc", 0x10000);
 389     sysbus_init_mmio(dev, &s->iomem);
 390
 391     return 0;
 392 }
 393
 394 static void strongarm_rtc_pre_save(void *opaque)
 395 {
 396     StrongARMRTCState *s = opaque;
 397
 398     strongarm_rtc_hzupdate(s);
 399 }
 400
 401 static int strongarm_rtc_post_load(void *opaque, int version_id)
 402 {
 403     StrongARMRTCState *s = opaque;
 404
 405     strongarm_rtc_timer_update(s);
 406     strongarm_rtc_int_update(s);
 407
 408     return 0;
 409 }
 410
 411 static const VMStateDescription vmstate_strongarm_rtc_regs = {
 412     .name = "strongarm-rtc",
 413     .version_id = 0,
 414     .minimum_version_id = 0,
 415     .minimum_version_id_old = 0,
 416     .pre_save = strongarm_rtc_pre_save,
 417     .post_load = strongarm_rtc_post_load,
 418     .fields = (VMStateField[]) {
 419         VMSTATE_UINT32(rttr, StrongARMRTCState),
 420         VMSTATE_UINT32(rtsr, StrongARMRTCState),
 421         VMSTATE_UINT32(rtar, StrongARMRTCState),
 422         VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
 423         VMSTATE_INT64(last_hz, StrongARMRTCState),
 424         VMSTATE_END_OF_LIST(),
 425     },
 426 };
 427
 428 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
 429 {
 430     DeviceClass *dc = DEVICE_CLASS(klass);
 431     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 432
 433     k->init = strongarm_rtc_init;
 434     dc->desc = "StrongARM RTC Controller";
 435     dc->vmsd = &vmstate_strongarm_rtc_regs;
 436 }
 437
 438 static const TypeInfo strongarm_rtc_sysbus_info = {
 439     .name          = "strongarm-rtc",
 440     .parent        = TYPE_SYS_BUS_DEVICE,
 441     .instance_size = sizeof(StrongARMRTCState),
 442     .class_init    = strongarm_rtc_sysbus_class_init,
 443 };
 444
 445 /* GPIO */
 446 #define GPLR 0x00
 447 #define GPDR 0x04
 448 #define GPSR 0x08
 449 #define GPCR 0x0c
 450 #define GRER 0x10
 451 #define GFER 0x14
 452 #define GEDR 0x18
 453 #define GAFR 0x1c
 454
 455 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
 456 struct StrongARMGPIOInfo {
 457     SysBusDevice busdev;
 458     MemoryRegion iomem;
 459     qemu_irq handler[28];
 460     qemu_irq irqs[11];
 461     qemu_irq irqX;
 462
 463     uint32_t ilevel;
 464     uint32_t olevel;
 465     uint32_t dir;
 466     uint32_t rising;
 467     uint32_t falling;
 468     uint32_t status;
 469     uint32_t gpsr;
 470     uint32_t gafr;
 471
 472     uint32_t prev_level;
 473 };
 474
 475
 476 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
 477 {
 478     int i;
 479     for (i = 0; i < 11; i++) {
 480         qemu_set_irq(s->irqs[i], s->status & (1 << i));
 481     }
 482
 483     qemu_set_irq(s->irqX, (s->status & ~0x7ff));
 484 }
 485
 486 static void strongarm_gpio_set(void *opaque, int line, int level)
 487 {
 488     StrongARMGPIOInfo *s = opaque;
 489     uint32_t mask;
 490
 491     mask = 1 << line;
 492
 493     if (level) {
 494         s->status |= s->rising & mask &
 495                 ~s->ilevel & ~s->dir;
 496         s->ilevel |= mask;
 497     } else {
 498         s->status |= s->falling & mask &
 499                 s->ilevel & ~s->dir;
 500         s->ilevel &= ~mask;
 501     }
 502
 503     if (s->status & mask) {
 504         strongarm_gpio_irq_update(s);
 505     }
 506 }
 507
 508 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
 509 {
 510     uint32_t level, diff;
 511     int bit;
 512
 513     level = s->olevel & s->dir;
 514
 515     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 516         bit = ffs(diff) - 1;
 517         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 518     }
 519
 520     s->prev_level = level;
 521 }
 522
 523 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
 524                                     unsigned size)
 525 {
 526     StrongARMGPIOInfo *s = opaque;
 527
 528     switch (offset) {
 529     case GPDR:        /* GPIO Pin-Direction registers */
 530         return s->dir;
 531
 532     case GPSR:        /* GPIO Pin-Output Set registers */
 533         DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
 534                         __func__, offset);
 535         return s->gpsr;    /* Return last written value.  */
 536
 537     case GPCR:        /* GPIO Pin-Output Clear registers */
 538         DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
 539                         __func__, offset);
 540         return 31337;        /* Specified as unpredictable in the docs.  */
 541
 542     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 543         return s->rising;
 544
 545     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 546         return s->falling;
 547
 548     case GAFR:        /* GPIO Alternate Function registers */
 549         return s->gafr;
 550
 551     case GPLR:        /* GPIO Pin-Level registers */
 552         return (s->olevel & s->dir) |
 553                (s->ilevel & ~s->dir);
 554
 555     case GEDR:        /* GPIO Edge Detect Status registers */
 556         return s->status;
 557
 558     default:
 559         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 560     }
 561
 562     return 0;
 563 }
 564
 565 static void strongarm_gpio_write(void *opaque, hwaddr offset,
 566                                  uint64_t value, unsigned size)
 567 {
 568     StrongARMGPIOInfo *s = opaque;
 569
 570     switch (offset) {
 571     case GPDR:        /* GPIO Pin-Direction registers */
 572         s->dir = value;
 573         strongarm_gpio_handler_update(s);
 574         break;
 575
 576     case GPSR:        /* GPIO Pin-Output Set registers */
 577         s->olevel |= value;
 578         strongarm_gpio_handler_update(s);
 579         s->gpsr = value;
 580         break;
 581
 582     case GPCR:        /* GPIO Pin-Output Clear registers */
 583         s->olevel &= ~value;
 584         strongarm_gpio_handler_update(s);
 585         break;
 586
 587     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 588         s->rising = value;
 589         break;
 590
 591     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 592         s->falling = value;
 593         break;
 594
 595     case GAFR:        /* GPIO Alternate Function registers */
 596         s->gafr = value;
 597         break;
 598
 599     case GEDR:        /* GPIO Edge Detect Status registers */
 600         s->status &= ~value;
 601         strongarm_gpio_irq_update(s);
 602         break;
 603
 604     default:
 605         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 606     }
 607 }
 608
 609 static const MemoryRegionOps strongarm_gpio_ops = {
 610     .read = strongarm_gpio_read,
 611     .write = strongarm_gpio_write,
 612     .endianness = DEVICE_NATIVE_ENDIAN,
 613 };
 614
 615 static DeviceState *strongarm_gpio_init(hwaddr base,
 616                 DeviceState *pic)
 617 {
 618     DeviceState *dev;
 619     int i;
 620
 621     dev = qdev_create(NULL, "strongarm-gpio");
 622     qdev_init_nofail(dev);
 623
 624     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 625     for (i = 0; i < 12; i++)
 626         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 627                     qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
 628
 629     return dev;
 630 }
 631
 632 static int strongarm_gpio_initfn(SysBusDevice *dev)
 633 {
 634     StrongARMGPIOInfo *s;
 635     int i;
 636
 637     s = FROM_SYSBUS(StrongARMGPIOInfo, dev);
 638
 639     qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28);
 640     qdev_init_gpio_out(&dev->qdev, s->handler, 28);
 641
 642     memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_gpio_ops, s,
 643                           "gpio", 0x1000);
 644
 645     sysbus_init_mmio(dev, &s->iomem);
 646     for (i = 0; i < 11; i++) {
 647         sysbus_init_irq(dev, &s->irqs[i]);
 648     }
 649     sysbus_init_irq(dev, &s->irqX);
 650
 651     return 0;
 652 }
 653
 654 static const VMStateDescription vmstate_strongarm_gpio_regs = {
 655     .name = "strongarm-gpio",
 656     .version_id = 0,
 657     .minimum_version_id = 0,
 658     .minimum_version_id_old = 0,
 659     .fields = (VMStateField[]) {
 660         VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
 661         VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
 662         VMSTATE_UINT32(dir, StrongARMGPIOInfo),
 663         VMSTATE_UINT32(rising, StrongARMGPIOInfo),
 664         VMSTATE_UINT32(falling, StrongARMGPIOInfo),
 665         VMSTATE_UINT32(status, StrongARMGPIOInfo),
 666         VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
 667         VMSTATE_END_OF_LIST(),
 668     },
 669 };
 670
 671 static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
 672 {
 673     DeviceClass *dc = DEVICE_CLASS(klass);
 674     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 675
 676     k->init = strongarm_gpio_initfn;
 677     dc->desc = "StrongARM GPIO controller";
 678 }
 679
 680 static const TypeInfo strongarm_gpio_info = {
 681     .name          = "strongarm-gpio",
 682     .parent        = TYPE_SYS_BUS_DEVICE,
 683     .instance_size = sizeof(StrongARMGPIOInfo),
 684     .class_init    = strongarm_gpio_class_init,
 685 };
 686
 687 /* Peripheral Pin Controller */
 688 #define PPDR 0x00
 689 #define PPSR 0x04
 690 #define PPAR 0x08
 691 #define PSDR 0x0c
 692 #define PPFR 0x10
 693
 694 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
 695 struct StrongARMPPCInfo {
 696     SysBusDevice busdev;
 697     MemoryRegion iomem;
 698     qemu_irq handler[28];
 699
 700     uint32_t ilevel;
 701     uint32_t olevel;
 702     uint32_t dir;
 703     uint32_t ppar;
 704     uint32_t psdr;
 705     uint32_t ppfr;
 706
 707     uint32_t prev_level;
 708 };
 709
 710 static void strongarm_ppc_set(void *opaque, int line, int level)
 711 {
 712     StrongARMPPCInfo *s = opaque;
 713
 714     if (level) {
 715         s->ilevel |= 1 << line;
 716     } else {
 717         s->ilevel &= ~(1 << line);
 718     }
 719 }
 720
 721 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
 722 {
 723     uint32_t level, diff;
 724     int bit;
 725
 726     level = s->olevel & s->dir;
 727
 728     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 729         bit = ffs(diff) - 1;
 730         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 731     }
 732
 733     s->prev_level = level;
 734 }
 735
 736 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
 737                                    unsigned size)
 738 {
 739     StrongARMPPCInfo *s = opaque;
 740
 741     switch (offset) {
 742     case PPDR:        /* PPC Pin Direction registers */
 743         return s->dir | ~0x3fffff;
 744
 745     case PPSR:        /* PPC Pin State registers */
 746         return (s->olevel & s->dir) |
 747                (s->ilevel & ~s->dir) |
 748                ~0x3fffff;
 749
 750     case PPAR:
 751         return s->ppar | ~0x41000;
 752
 753     case PSDR:
 754         return s->psdr;
 755
 756     case PPFR:
 757         return s->ppfr | ~0x7f001;
 758
 759     default:
 760         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 761     }
 762
 763     return 0;
 764 }
 765
 766 static void strongarm_ppc_write(void *opaque, hwaddr offset,
 767                                 uint64_t value, unsigned size)
 768 {
 769     StrongARMPPCInfo *s = opaque;
 770
 771     switch (offset) {
 772     case PPDR:        /* PPC Pin Direction registers */
 773         s->dir = value & 0x3fffff;
 774         strongarm_ppc_handler_update(s);
 775         break;
 776
 777     case PPSR:        /* PPC Pin State registers */
 778         s->olevel = value & s->dir & 0x3fffff;
 779         strongarm_ppc_handler_update(s);
 780         break;
 781
 782     case PPAR:
 783         s->ppar = value & 0x41000;
 784         break;
 785
 786     case PSDR:
 787         s->psdr = value & 0x3fffff;
 788         break;
 789
 790     case PPFR:
 791         s->ppfr = value & 0x7f001;
 792         break;
 793
 794     default:
 795         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 796     }
 797 }
 798
 799 static const MemoryRegionOps strongarm_ppc_ops = {
 800     .read = strongarm_ppc_read,
 801     .write = strongarm_ppc_write,
 802     .endianness = DEVICE_NATIVE_ENDIAN,
 803 };
 804
 805 static int strongarm_ppc_init(SysBusDevice *dev)
 806 {
 807     StrongARMPPCInfo *s;
 808
 809     s = FROM_SYSBUS(StrongARMPPCInfo, dev);
 810
 811     qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22);
 812     qdev_init_gpio_out(&dev->qdev, s->handler, 22);
 813
 814     memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ppc_ops, s,
 815                           "ppc", 0x1000);
 816
 817     sysbus_init_mmio(dev, &s->iomem);
 818
 819     return 0;
 820 }
 821
 822 static const VMStateDescription vmstate_strongarm_ppc_regs = {
 823     .name = "strongarm-ppc",
 824     .version_id = 0,
 825     .minimum_version_id = 0,
 826     .minimum_version_id_old = 0,
 827     .fields = (VMStateField[]) {
 828         VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
 829         VMSTATE_UINT32(olevel, StrongARMPPCInfo),
 830         VMSTATE_UINT32(dir, StrongARMPPCInfo),
 831         VMSTATE_UINT32(ppar, StrongARMPPCInfo),
 832         VMSTATE_UINT32(psdr, StrongARMPPCInfo),
 833         VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
 834         VMSTATE_END_OF_LIST(),
 835     },
 836 };
 837
 838 static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
 839 {
 840     DeviceClass *dc = DEVICE_CLASS(klass);
 841     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 842
 843     k->init = strongarm_ppc_init;
 844     dc->desc = "StrongARM PPC controller";
 845 }
 846
 847 static const TypeInfo strongarm_ppc_info = {
 848     .name          = "strongarm-ppc",
 849     .parent        = TYPE_SYS_BUS_DEVICE,
 850     .instance_size = sizeof(StrongARMPPCInfo),
 851     .class_init    = strongarm_ppc_class_init,
 852 };
 853
 854 /* UART Ports */
 855 #define UTCR0 0x00
 856 #define UTCR1 0x04
 857 #define UTCR2 0x08
 858 #define UTCR3 0x0c
 859 #define UTDR  0x14
 860 #define UTSR0 0x1c
 861 #define UTSR1 0x20
 862
 863 #define UTCR0_PE  (1 << 0) /* Parity enable */
 864 #define UTCR0_OES (1 << 1) /* Even parity */
 865 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
 866 #define UTCR0_DSS (1 << 3) /* 8-bit data */
 867
 868 #define UTCR3_RXE (1 << 0) /* Rx enable */
 869 #define UTCR3_TXE (1 << 1) /* Tx enable */
 870 #define UTCR3_BRK (1 << 2) /* Force Break */
 871 #define UTCR3_RIE (1 << 3) /* Rx int enable */
 872 #define UTCR3_TIE (1 << 4) /* Tx int enable */
 873 #define UTCR3_LBM (1 << 5) /* Loopback */
 874
 875 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
 876 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
 877 #define UTSR0_RID (1 << 2) /* Receiver Idle */
 878 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
 879 #define UTSR0_REB (1 << 4) /* Receiver end break */
 880 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
 881
 882 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
 883 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
 884 #define UTSR1_PRE (1 << 3) /* Parity error */
 885 #define UTSR1_FRE (1 << 4) /* Frame error */
 886 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
 887
 888 #define RX_FIFO_PRE (1 << 8)
 889 #define RX_FIFO_FRE (1 << 9)
 890 #define RX_FIFO_ROR (1 << 10)
 891
 892 typedef struct {
 893     SysBusDevice busdev;
 894     MemoryRegion iomem;
 895     CharDriverState *chr;
 896     qemu_irq irq;
 897
 898     uint8_t utcr0;
 899     uint16_t brd;
 900     uint8_t utcr3;
 901     uint8_t utsr0;
 902     uint8_t utsr1;
 903
 904     uint8_t tx_fifo[8];
 905     uint8_t tx_start;
 906     uint8_t tx_len;
 907     uint16_t rx_fifo[12]; /* value + error flags in high bits */
 908     uint8_t rx_start;
 909     uint8_t rx_len;
 910
 911     uint64_t char_transmit_time; /* time to transmit a char in ticks*/
 912     bool wait_break_end;
 913     QEMUTimer *rx_timeout_timer;
 914     QEMUTimer *tx_timer;
 915 } StrongARMUARTState;
 916
 917 static void strongarm_uart_update_status(StrongARMUARTState *s)
 918 {
 919     uint16_t utsr1 = 0;
 920
 921     if (s->tx_len != 8) {
 922         utsr1 |= UTSR1_TNF;
 923     }
 924
 925     if (s->rx_len != 0) {
 926         uint16_t ent = s->rx_fifo[s->rx_start];
 927
 928         utsr1 |= UTSR1_RNE;
 929         if (ent & RX_FIFO_PRE) {
 930             s->utsr1 |= UTSR1_PRE;
 931         }
 932         if (ent & RX_FIFO_FRE) {
 933             s->utsr1 |= UTSR1_FRE;
 934         }
 935         if (ent & RX_FIFO_ROR) {
 936             s->utsr1 |= UTSR1_ROR;
 937         }
 938     }
 939
 940     s->utsr1 = utsr1;
 941 }
 942
 943 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
 944 {
 945     uint16_t utsr0 = s->utsr0 &
 946             (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
 947     int i;
 948
 949     if ((s->utcr3 & UTCR3_TXE) &&
 950                 (s->utcr3 & UTCR3_TIE) &&
 951                 s->tx_len <= 4) {
 952         utsr0 |= UTSR0_TFS;
 953     }
 954
 955     if ((s->utcr3 & UTCR3_RXE) &&
 956                 (s->utcr3 & UTCR3_RIE) &&
 957                 s->rx_len > 4) {
 958         utsr0 |= UTSR0_RFS;
 959     }
 960
 961     for (i = 0; i < s->rx_len && i < 4; i++)
 962         if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
 963             utsr0 |= UTSR0_EIF;
 964             break;
 965         }
 966
 967     s->utsr0 = utsr0;
 968     qemu_set_irq(s->irq, utsr0);
 969 }
 970
 971 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
 972 {
 973     int speed, parity, data_bits, stop_bits, frame_size;
 974     QEMUSerialSetParams ssp;
 975
 976     /* Start bit. */
 977     frame_size = 1;
 978     if (s->utcr0 & UTCR0_PE) {
 979         /* Parity bit. */
 980         frame_size++;
 981         if (s->utcr0 & UTCR0_OES) {
 982             parity = 'E';
 983         } else {
 984             parity = 'O';
 985         }
 986     } else {
 987             parity = 'N';
 988     }
 989     if (s->utcr0 & UTCR0_SBS) {
 990         stop_bits = 2;
 991     } else {
 992         stop_bits = 1;
 993     }
 994
 995     data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
 996     frame_size += data_bits + stop_bits;
 997     speed = 3686400 / 16 / (s->brd + 1);
 998     ssp.speed = speed;
 999     ssp.parity = parity;
1000     ssp.data_bits = data_bits;
1001     ssp.stop_bits = stop_bits;
1002     s->char_transmit_time =  (get_ticks_per_sec() / speed) * frame_size;
1003     if (s->chr) {
1004         qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1005     }
1006
1007     DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
1008             speed, parity, data_bits, stop_bits);
1009 }
1010
1011 static void strongarm_uart_rx_to(void *opaque)
1012 {
1013     StrongARMUARTState *s = opaque;
1014
1015     if (s->rx_len) {
1016         s->utsr0 |= UTSR0_RID;
1017         strongarm_uart_update_int_status(s);
1018     }
1019 }
1020
1021 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1022 {
1023     if ((s->utcr3 & UTCR3_RXE) == 0) {
1024         /* rx disabled */
1025         return;
1026     }
1027
1028     if (s->wait_break_end) {
1029         s->utsr0 |= UTSR0_REB;
1030         s->wait_break_end = false;
1031     }
1032
1033     if (s->rx_len < 12) {
1034         s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1035         s->rx_len++;
1036     } else
1037         s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1038 }
1039
1040 static int strongarm_uart_can_receive(void *opaque)
1041 {
1042     StrongARMUARTState *s = opaque;
1043
1044     if (s->rx_len == 12) {
1045         return 0;
1046     }
1047     /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1048     if (s->rx_len < 8) {
1049         return 8 - s->rx_len;
1050     }
1051     return 1;
1052 }
1053
1054 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1055 {
1056     StrongARMUARTState *s = opaque;
1057     int i;
1058
1059     for (i = 0; i < size; i++) {
1060         strongarm_uart_rx_push(s, buf[i]);
1061     }
1062
1063     /* call the timeout receive callback in 3 char transmit time */
1064     qemu_mod_timer(s->rx_timeout_timer,
1065                     qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1066
1067     strongarm_uart_update_status(s);
1068     strongarm_uart_update_int_status(s);
1069 }
1070
1071 static void strongarm_uart_event(void *opaque, int event)
1072 {
1073     StrongARMUARTState *s = opaque;
1074     if (event == CHR_EVENT_BREAK) {
1075         s->utsr0 |= UTSR0_RBB;
1076         strongarm_uart_rx_push(s, RX_FIFO_FRE);
1077         s->wait_break_end = true;
1078         strongarm_uart_update_status(s);
1079         strongarm_uart_update_int_status(s);
1080     }
1081 }
1082
1083 static void strongarm_uart_tx(void *opaque)
1084 {
1085     StrongARMUARTState *s = opaque;
1086     uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
1087
1088     if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1089         strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1090     } else if (s->chr) {
1091         qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1);
1092     }
1093
1094     s->tx_start = (s->tx_start + 1) % 8;
1095     s->tx_len--;
1096     if (s->tx_len) {
1097         qemu_mod_timer(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1098     }
1099     strongarm_uart_update_status(s);
1100     strongarm_uart_update_int_status(s);
1101 }
1102
1103 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
1104                                     unsigned size)
1105 {
1106     StrongARMUARTState *s = opaque;
1107     uint16_t ret;
1108
1109     switch (addr) {
1110     case UTCR0:
1111         return s->utcr0;
1112
1113     case UTCR1:
1114         return s->brd >> 8;
1115
1116     case UTCR2:
1117         return s->brd & 0xff;
1118
1119     case UTCR3:
1120         return s->utcr3;
1121
1122     case UTDR:
1123         if (s->rx_len != 0) {
1124             ret = s->rx_fifo[s->rx_start];
1125             s->rx_start = (s->rx_start + 1) % 12;
1126             s->rx_len--;
1127             strongarm_uart_update_status(s);
1128             strongarm_uart_update_int_status(s);
1129             return ret;
1130         }
1131         return 0;
1132
1133     case UTSR0:
1134         return s->utsr0;
1135
1136     case UTSR1:
1137         return s->utsr1;
1138
1139     default:
1140         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1141         return 0;
1142     }
1143 }
1144
1145 static void strongarm_uart_write(void *opaque, hwaddr addr,
1146                                  uint64_t value, unsigned size)
1147 {
1148     StrongARMUARTState *s = opaque;
1149
1150     switch (addr) {
1151     case UTCR0:
1152         s->utcr0 = value & 0x7f;
1153         strongarm_uart_update_parameters(s);
1154         break;
1155
1156     case UTCR1:
1157         s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1158         strongarm_uart_update_parameters(s);
1159         break;
1160
1161     case UTCR2:
1162         s->brd = (s->brd & 0xf00) | (value & 0xff);
1163         strongarm_uart_update_parameters(s);
1164         break;
1165
1166     case UTCR3:
1167         s->utcr3 = value & 0x3f;
1168         if ((s->utcr3 & UTCR3_RXE) == 0) {
1169             s->rx_len = 0;
1170         }
1171         if ((s->utcr3 & UTCR3_TXE) == 0) {
1172             s->tx_len = 0;
1173         }
1174         strongarm_uart_update_status(s);
1175         strongarm_uart_update_int_status(s);
1176         break;
1177
1178     case UTDR:
1179         if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1180             s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1181             s->tx_len++;
1182             strongarm_uart_update_status(s);
1183             strongarm_uart_update_int_status(s);
1184             if (s->tx_len == 1) {
1185                 strongarm_uart_tx(s);
1186             }
1187         }
1188         break;
1189
1190     case UTSR0:
1191         s->utsr0 = s->utsr0 & ~(value &
1192                 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1193         strongarm_uart_update_int_status(s);
1194         break;
1195
1196     default:
1197         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1198     }
1199 }
1200
1201 static const MemoryRegionOps strongarm_uart_ops = {
1202     .read = strongarm_uart_read,
1203     .write = strongarm_uart_write,
1204     .endianness = DEVICE_NATIVE_ENDIAN,
1205 };
1206
1207 static int strongarm_uart_init(SysBusDevice *dev)
1208 {
1209     StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev);
1210
1211     memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_uart_ops, s,
1212                           "uart", 0x10000);
1213     sysbus_init_mmio(dev, &s->iomem);
1214     sysbus_init_irq(dev, &s->irq);
1215
1216     s->rx_timeout_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_rx_to, s);
1217     s->tx_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_tx, s);
1218
1219     if (s->chr) {
1220         qemu_chr_add_handlers(s->chr,
1221                         strongarm_uart_can_receive,
1222                         strongarm_uart_receive,
1223                         strongarm_uart_event,
1224                         s);
1225     }
1226
1227     return 0;
1228 }
1229
1230 static void strongarm_uart_reset(DeviceState *dev)
1231 {
1232     StrongARMUARTState *s = DO_UPCAST(StrongARMUARTState, busdev.qdev, dev);
1233
1234     s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1235     s->brd = 23;    /* 9600 */
1236     /* enable send & recv - this actually violates spec */
1237     s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1238
1239     s->rx_len = s->tx_len = 0;
1240
1241     strongarm_uart_update_parameters(s);
1242     strongarm_uart_update_status(s);
1243     strongarm_uart_update_int_status(s);
1244 }
1245
1246 static int strongarm_uart_post_load(void *opaque, int version_id)
1247 {
1248     StrongARMUARTState *s = opaque;
1249
1250     strongarm_uart_update_parameters(s);
1251     strongarm_uart_update_status(s);
1252     strongarm_uart_update_int_status(s);
1253
1254     /* tx and restart timer */
1255     if (s->tx_len) {
1256         strongarm_uart_tx(s);
1257     }
1258
1259     /* restart rx timeout timer */
1260     if (s->rx_len) {
1261         qemu_mod_timer(s->rx_timeout_timer,
1262                 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1263     }
1264
1265     return 0;
1266 }
1267
1268 static const VMStateDescription vmstate_strongarm_uart_regs = {
1269     .name = "strongarm-uart",
1270     .version_id = 0,
1271     .minimum_version_id = 0,
1272     .minimum_version_id_old = 0,
1273     .post_load = strongarm_uart_post_load,
1274     .fields = (VMStateField[]) {
1275         VMSTATE_UINT8(utcr0, StrongARMUARTState),
1276         VMSTATE_UINT16(brd, StrongARMUARTState),
1277         VMSTATE_UINT8(utcr3, StrongARMUARTState),
1278         VMSTATE_UINT8(utsr0, StrongARMUARTState),
1279         VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1280         VMSTATE_UINT8(tx_start, StrongARMUARTState),
1281         VMSTATE_UINT8(tx_len, StrongARMUARTState),
1282         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1283         VMSTATE_UINT8(rx_start, StrongARMUARTState),
1284         VMSTATE_UINT8(rx_len, StrongARMUARTState),
1285         VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1286         VMSTATE_END_OF_LIST(),
1287     },
1288 };
1289
1290 static Property strongarm_uart_properties[] = {
1291     DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1292     DEFINE_PROP_END_OF_LIST(),
1293 };
1294
1295 static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1296 {
1297     DeviceClass *dc = DEVICE_CLASS(klass);
1298     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1299
1300     k->init = strongarm_uart_init;
1301     dc->desc = "StrongARM UART controller";
1302     dc->reset = strongarm_uart_reset;
1303     dc->vmsd = &vmstate_strongarm_uart_regs;
1304     dc->props = strongarm_uart_properties;
1305 }
1306
1307 static const TypeInfo strongarm_uart_info = {
1308     .name          = "strongarm-uart",
1309     .parent        = TYPE_SYS_BUS_DEVICE,
1310     .instance_size = sizeof(StrongARMUARTState),
1311     .class_init    = strongarm_uart_class_init,
1312 };
1313
1314 /* Synchronous Serial Ports */
1315 typedef struct {
1316     SysBusDevice busdev;
1317     MemoryRegion iomem;
1318     qemu_irq irq;
1319     SSIBus *bus;
1320
1321     uint16_t sscr[2];
1322     uint16_t sssr;
1323
1324     uint16_t rx_fifo[8];
1325     uint8_t rx_level;
1326     uint8_t rx_start;
1327 } StrongARMSSPState;
1328
1329 #define SSCR0 0x60 /* SSP Control register 0 */
1330 #define SSCR1 0x64 /* SSP Control register 1 */
1331 #define SSDR  0x6c /* SSP Data register */
1332 #define SSSR  0x74 /* SSP Status register */
1333
1334 /* Bitfields for above registers */
1335 #define SSCR0_SPI(x)    (((x) & 0x30) == 0x00)
1336 #define SSCR0_SSP(x)    (((x) & 0x30) == 0x10)
1337 #define SSCR0_UWIRE(x)  (((x) & 0x30) == 0x20)
1338 #define SSCR0_PSP(x)    (((x) & 0x30) == 0x30)
1339 #define SSCR0_SSE       (1 << 7)
1340 #define SSCR0_DSS(x)    (((x) & 0xf) + 1)
1341 #define SSCR1_RIE       (1 << 0)
1342 #define SSCR1_TIE       (1 << 1)
1343 #define SSCR1_LBM       (1 << 2)
1344 #define SSSR_TNF        (1 << 2)
1345 #define SSSR_RNE        (1 << 3)
1346 #define SSSR_TFS        (1 << 5)
1347 #define SSSR_RFS        (1 << 6)
1348 #define SSSR_ROR        (1 << 7)
1349 #define SSSR_RW         0x0080
1350
1351 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1352 {
1353     int level = 0;
1354
1355     level |= (s->sssr & SSSR_ROR);
1356     level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);
1357     level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);
1358     qemu_set_irq(s->irq, level);
1359 }
1360
1361 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1362 {
1363     s->sssr &= ~SSSR_TFS;
1364     s->sssr &= ~SSSR_TNF;
1365     if (s->sscr[0] & SSCR0_SSE) {
1366         if (s->rx_level >= 4) {
1367             s->sssr |= SSSR_RFS;
1368         } else {
1369             s->sssr &= ~SSSR_RFS;
1370         }
1371         if (s->rx_level) {
1372             s->sssr |= SSSR_RNE;
1373         } else {
1374             s->sssr &= ~SSSR_RNE;
1375         }
1376         /* TX FIFO is never filled, so it is always in underrun
1377            condition if SSP is enabled */
1378         s->sssr |= SSSR_TFS;
1379         s->sssr |= SSSR_TNF;
1380     }
1381
1382     strongarm_ssp_int_update(s);
1383 }
1384
1385 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
1386                                    unsigned size)
1387 {
1388     StrongARMSSPState *s = opaque;
1389     uint32_t retval;
1390
1391     switch (addr) {
1392     case SSCR0:
1393         return s->sscr[0];
1394     case SSCR1:
1395         return s->sscr[1];
1396     case SSSR:
1397         return s->sssr;
1398     case SSDR:
1399         if (~s->sscr[0] & SSCR0_SSE) {
1400             return 0xffffffff;
1401         }
1402         if (s->rx_level < 1) {
1403             printf("%s: SSP Rx Underrun\n", __func__);
1404             return 0xffffffff;
1405         }
1406         s->rx_level--;
1407         retval = s->rx_fifo[s->rx_start++];
1408         s->rx_start &= 0x7;
1409         strongarm_ssp_fifo_update(s);
1410         return retval;
1411     default:
1412         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1413         break;
1414     }
1415     return 0;
1416 }
1417
1418 static void strongarm_ssp_write(void *opaque, hwaddr addr,
1419                                 uint64_t value, unsigned size)
1420 {
1421     StrongARMSSPState *s = opaque;
1422
1423     switch (addr) {
1424     case SSCR0:
1425         s->sscr[0] = value & 0xffbf;
1426         if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1427             printf("%s: Wrong data size: %i bits\n", __func__,
1428                    (int)SSCR0_DSS(value));
1429         }
1430         if (!(value & SSCR0_SSE)) {
1431             s->sssr = 0;
1432             s->rx_level = 0;
1433         }
1434         strongarm_ssp_fifo_update(s);
1435         break;
1436
1437     case SSCR1:
1438         s->sscr[1] = value & 0x2f;
1439         if (value & SSCR1_LBM) {
1440             printf("%s: Attempt to use SSP LBM mode\n", __func__);
1441         }
1442         strongarm_ssp_fifo_update(s);
1443         break;
1444
1445     case SSSR:
1446         s->sssr &= ~(value & SSSR_RW);
1447         strongarm_ssp_int_update(s);
1448         break;
1449
1450     case SSDR:
1451         if (SSCR0_UWIRE(s->sscr[0])) {
1452             value &= 0xff;
1453         } else
1454             /* Note how 32bits overflow does no harm here */
1455             value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1456
1457         /* Data goes from here to the Tx FIFO and is shifted out from
1458          * there directly to the slave, no need to buffer it.
1459          */
1460         if (s->sscr[0] & SSCR0_SSE) {
1461             uint32_t readval;
1462             if (s->sscr[1] & SSCR1_LBM) {
1463                 readval = value;
1464             } else {
1465                 readval = ssi_transfer(s->bus, value);
1466             }
1467
1468             if (s->rx_level < 0x08) {
1469                 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1470             } else {
1471                 s->sssr |= SSSR_ROR;
1472             }
1473         }
1474         strongarm_ssp_fifo_update(s);
1475         break;
1476
1477     default:
1478         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1479         break;
1480     }
1481 }
1482
1483 static const MemoryRegionOps strongarm_ssp_ops = {
1484     .read = strongarm_ssp_read,
1485     .write = strongarm_ssp_write,
1486     .endianness = DEVICE_NATIVE_ENDIAN,
1487 };
1488
1489 static int strongarm_ssp_post_load(void *opaque, int version_id)
1490 {
1491     StrongARMSSPState *s = opaque;
1492
1493     strongarm_ssp_fifo_update(s);
1494
1495     return 0;
1496 }
1497
1498 static int strongarm_ssp_init(SysBusDevice *dev)
1499 {
1500     StrongARMSSPState *s = FROM_SYSBUS(StrongARMSSPState, dev);
1501
1502     sysbus_init_irq(dev, &s->irq);
1503
1504     memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ssp_ops, s,
1505                           "ssp", 0x1000);
1506     sysbus_init_mmio(dev, &s->iomem);
1507
1508     s->bus = ssi_create_bus(&dev->qdev, "ssi");
1509     return 0;
1510 }
1511
1512 static void strongarm_ssp_reset(DeviceState *dev)
1513 {
1514     StrongARMSSPState *s = DO_UPCAST(StrongARMSSPState, busdev.qdev, dev);
1515     s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1516     s->rx_start = 0;
1517     s->rx_level = 0;
1518 }
1519
1520 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1521     .name = "strongarm-ssp",
1522     .version_id = 0,
1523     .minimum_version_id = 0,
1524     .minimum_version_id_old = 0,
1525     .post_load = strongarm_ssp_post_load,
1526     .fields = (VMStateField[]) {
1527         VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1528         VMSTATE_UINT16(sssr, StrongARMSSPState),
1529         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1530         VMSTATE_UINT8(rx_start, StrongARMSSPState),
1531         VMSTATE_UINT8(rx_level, StrongARMSSPState),
1532         VMSTATE_END_OF_LIST(),
1533     },
1534 };
1535
1536 static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1537 {
1538     DeviceClass *dc = DEVICE_CLASS(klass);
1539     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1540
1541     k->init = strongarm_ssp_init;
1542     dc->desc = "StrongARM SSP controller";
1543     dc->reset = strongarm_ssp_reset;
1544     dc->vmsd = &vmstate_strongarm_ssp_regs;
1545 }
1546
1547 static const TypeInfo strongarm_ssp_info = {
1548     .name          = "strongarm-ssp",
1549     .parent        = TYPE_SYS_BUS_DEVICE,
1550     .instance_size = sizeof(StrongARMSSPState),
1551     .class_init    = strongarm_ssp_class_init,
1552 };
1553
1554 /* Main CPU functions */
1555 StrongARMState *sa1110_init(MemoryRegion *sysmem,
1556                             unsigned int sdram_size, const char *rev)
1557 {
1558     StrongARMState *s;
1559     qemu_irq *pic;
1560     int i;
1561
1562     s = g_malloc0(sizeof(StrongARMState));
1563
1564     if (!rev) {
1565         rev = "sa1110-b5";
1566     }
1567
1568     if (strncmp(rev, "sa1110", 6)) {
1569         error_report("Machine requires a SA1110 processor.");
1570         exit(1);
1571     }
1572
1573     s->cpu = cpu_arm_init(rev);
1574
1575     if (!s->cpu) {
1576         error_report("Unable to find CPU definition");
1577         exit(1);
1578     }
1579
1580     memory_region_init_ram(&s->sdram, NULL, "strongarm.sdram", sdram_size);
1581     vmstate_register_ram_global(&s->sdram);
1582     memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1583
1584     pic = arm_pic_init_cpu(s->cpu);
1585     s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1586                     pic[ARM_PIC_CPU_IRQ], pic[ARM_PIC_CPU_FIQ], NULL);
1587
1588     sysbus_create_varargs("pxa25x-timer", 0x90000000,
1589                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1590                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1591                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1592                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1593                     NULL);
1594
1595     sysbus_create_simple("strongarm-rtc", 0x90010000,
1596                     qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1597
1598     s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1599
1600     s->ppc = sysbus_create_varargs("strongarm-ppc", 0x90060000, NULL);
1601
1602     for (i = 0; sa_serial[i].io_base; i++) {
1603         DeviceState *dev = qdev_create(NULL, "strongarm-uart");
1604         qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1605         qdev_init_nofail(dev);
1606         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
1607                 sa_serial[i].io_base);
1608         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
1609                 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1610     }
1611
1612     s->ssp = sysbus_create_varargs("strongarm-ssp", 0x80070000,
1613                 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1614     s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1615
1616     return s;
1617 }
1618
1619 static void strongarm_register_types(void)
1620 {
1621     type_register_static(&strongarm_pic_info);
1622     type_register_static(&strongarm_rtc_sysbus_info);
1623     type_register_static(&strongarm_gpio_info);
1624     type_register_static(&strongarm_ppc_info);
1625     type_register_static(&strongarm_uart_info);
1626     type_register_static(&strongarm_ssp_info);
1627 }
1628
1629 type_init(strongarm_register_types)