hw/arm/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "hw/sysbus.h"
  27 #include "hw/arm/arm.h"
  28 #include "hw/arm/primecell.h"
  29 #include "hw/devices.h"
  30 #include "net/net.h"
  31 #include "sysemu/sysemu.h"
  32 #include "hw/boards.h"
  33 #include "hw/loader.h"
  34 #include "exec/address-spaces.h"
  35 #include "sysemu/block-backend.h"
  36 #include "hw/block/flash.h"
  37 #include "sysemu/device_tree.h"
  38 #include "qemu/error-report.h"
  39 #include <libfdt.h>
  40
  41 #define VEXPRESS_BOARD_ID 0x8e0
  42 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  43 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  44
  45 /* Number of virtio transports to create (0..8; limited by
  46  * number of available IRQ lines).
  47  */
  48 #define NUM_VIRTIO_TRANSPORTS 4
  49
  50 /* Address maps for peripherals:
  51  * the Versatile Express motherboard has two possible maps,
  52  * the "legacy" one (used for A9) and the "Cortex-A Series"
  53  * map (used for newer cores).
  54  * Individual daughterboards can also have different maps for
  55  * their peripherals.
  56  */
  57
  58 enum {
  59     VE_SYSREGS,
  60     VE_SP810,
  61     VE_SERIALPCI,
  62     VE_PL041,
  63     VE_MMCI,
  64     VE_KMI0,
  65     VE_KMI1,
  66     VE_UART0,
  67     VE_UART1,
  68     VE_UART2,
  69     VE_UART3,
  70     VE_WDT,
  71     VE_TIMER01,
  72     VE_TIMER23,
  73     VE_SERIALDVI,
  74     VE_RTC,
  75     VE_COMPACTFLASH,
  76     VE_CLCD,
  77     VE_NORFLASH0,
  78     VE_NORFLASH1,
  79     VE_NORFLASHALIAS,
  80     VE_SRAM,
  81     VE_VIDEORAM,
  82     VE_ETHERNET,
  83     VE_USB,
  84     VE_DAPROM,
  85     VE_VIRTIO,
  86 };
  87
  88 static hwaddr motherboard_legacy_map[] = {
  89     [VE_NORFLASHALIAS] = 0,
  90     /* CS7: 0x10000000 .. 0x10020000 */
  91     [VE_SYSREGS] = 0x10000000,
  92     [VE_SP810] = 0x10001000,
  93     [VE_SERIALPCI] = 0x10002000,
  94     [VE_PL041] = 0x10004000,
  95     [VE_MMCI] = 0x10005000,
  96     [VE_KMI0] = 0x10006000,
  97     [VE_KMI1] = 0x10007000,
  98     [VE_UART0] = 0x10009000,
  99     [VE_UART1] = 0x1000a000,
 100     [VE_UART2] = 0x1000b000,
 101     [VE_UART3] = 0x1000c000,
 102     [VE_WDT] = 0x1000f000,
 103     [VE_TIMER01] = 0x10011000,
 104     [VE_TIMER23] = 0x10012000,
 105     [VE_VIRTIO] = 0x10013000,
 106     [VE_SERIALDVI] = 0x10016000,
 107     [VE_RTC] = 0x10017000,
 108     [VE_COMPACTFLASH] = 0x1001a000,
 109     [VE_CLCD] = 0x1001f000,
 110     /* CS0: 0x40000000 .. 0x44000000 */
 111     [VE_NORFLASH0] = 0x40000000,
 112     /* CS1: 0x44000000 .. 0x48000000 */
 113     [VE_NORFLASH1] = 0x44000000,
 114     /* CS2: 0x48000000 .. 0x4a000000 */
 115     [VE_SRAM] = 0x48000000,
 116     /* CS3: 0x4c000000 .. 0x50000000 */
 117     [VE_VIDEORAM] = 0x4c000000,
 118     [VE_ETHERNET] = 0x4e000000,
 119     [VE_USB] = 0x4f000000,
 120 };
 121
 122 static hwaddr motherboard_aseries_map[] = {
 123     [VE_NORFLASHALIAS] = 0,
 124     /* CS0: 0x08000000 .. 0x0c000000 */
 125     [VE_NORFLASH0] = 0x08000000,
 126     /* CS4: 0x0c000000 .. 0x10000000 */
 127     [VE_NORFLASH1] = 0x0c000000,
 128     /* CS5: 0x10000000 .. 0x14000000 */
 129     /* CS1: 0x14000000 .. 0x18000000 */
 130     [VE_SRAM] = 0x14000000,
 131     /* CS2: 0x18000000 .. 0x1c000000 */
 132     [VE_VIDEORAM] = 0x18000000,
 133     [VE_ETHERNET] = 0x1a000000,
 134     [VE_USB] = 0x1b000000,
 135     /* CS3: 0x1c000000 .. 0x20000000 */
 136     [VE_DAPROM] = 0x1c000000,
 137     [VE_SYSREGS] = 0x1c010000,
 138     [VE_SP810] = 0x1c020000,
 139     [VE_SERIALPCI] = 0x1c030000,
 140     [VE_PL041] = 0x1c040000,
 141     [VE_MMCI] = 0x1c050000,
 142     [VE_KMI0] = 0x1c060000,
 143     [VE_KMI1] = 0x1c070000,
 144     [VE_UART0] = 0x1c090000,
 145     [VE_UART1] = 0x1c0a0000,
 146     [VE_UART2] = 0x1c0b0000,
 147     [VE_UART3] = 0x1c0c0000,
 148     [VE_WDT] = 0x1c0f0000,
 149     [VE_TIMER01] = 0x1c110000,
 150     [VE_TIMER23] = 0x1c120000,
 151     [VE_VIRTIO] = 0x1c130000,
 152     [VE_SERIALDVI] = 0x1c160000,
 153     [VE_RTC] = 0x1c170000,
 154     [VE_COMPACTFLASH] = 0x1c1a0000,
 155     [VE_CLCD] = 0x1c1f0000,
 156 };
 157
 158 /* Structure defining the peculiarities of a specific daughterboard */
 159
 160 typedef struct VEDBoardInfo VEDBoardInfo;
 161
 162 typedef struct {
 163     MachineClass parent;
 164     VEDBoardInfo *daughterboard;
 165 } VexpressMachineClass;
 166
 167 typedef struct {
 168     MachineState parent;
 169     bool secure;
 170 } VexpressMachineState;
 171
 172 #define TYPE_VEXPRESS_MACHINE   "vexpress"
 173 #define TYPE_VEXPRESS_A9_MACHINE   MACHINE_TYPE_NAME("vexpress-a9")
 174 #define TYPE_VEXPRESS_A15_MACHINE   MACHINE_TYPE_NAME("vexpress-a15")
 175 #define VEXPRESS_MACHINE(obj) \
 176     OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE)
 177 #define VEXPRESS_MACHINE_GET_CLASS(obj) \
 178     OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE)
 179 #define VEXPRESS_MACHINE_CLASS(klass) \
 180     OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE)
 181
 182 typedef void DBoardInitFn(const VexpressMachineState *machine,
 183                           ram_addr_t ram_size,
 184                           const char *cpu_model,
 185                           qemu_irq *pic);
 186
 187 struct VEDBoardInfo {
 188     struct arm_boot_info bootinfo;
 189     const hwaddr *motherboard_map;
 190     hwaddr loader_start;
 191     const hwaddr gic_cpu_if_addr;
 192     uint32_t proc_id;
 193     uint32_t num_voltage_sensors;
 194     const uint32_t *voltages;
 195     uint32_t num_clocks;
 196     const uint32_t *clocks;
 197     DBoardInitFn *init;
 198 };
 199
 200 static void init_cpus(const char *cpu_model, const char *privdev,
 201                       hwaddr periphbase, qemu_irq *pic, bool secure)
 202 {
 203     ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 204     DeviceState *dev;
 205     SysBusDevice *busdev;
 206     int n;
 207
 208     if (!cpu_oc) {
 209         fprintf(stderr, "Unable to find CPU definition\n");
 210         exit(1);
 211     }
 212
 213     /* Create the actual CPUs */
 214     for (n = 0; n < smp_cpus; n++) {
 215         Object *cpuobj = object_new(object_class_get_name(cpu_oc));
 216
 217         if (!secure) {
 218             object_property_set_bool(cpuobj, false, "has_el3", NULL);
 219         }
 220
 221         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 222             object_property_set_int(cpuobj, periphbase,
 223                                     "reset-cbar", &error_abort);
 224         }
 225         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
 226     }
 227
 228     /* Create the private peripheral devices (including the GIC);
 229      * this must happen after the CPUs are created because a15mpcore_priv
 230      * wires itself up to the CPU's generic_timer gpio out lines.
 231      */
 232     dev = qdev_create(NULL, privdev);
 233     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 234     qdev_init_nofail(dev);
 235     busdev = SYS_BUS_DEVICE(dev);
 236     sysbus_mmio_map(busdev, 0, periphbase);
 237
 238     /* Interrupts [42:0] are from the motherboard;
 239      * [47:43] are reserved; [63:48] are daughterboard
 240      * peripherals. Note that some documentation numbers
 241      * external interrupts starting from 32 (because there
 242      * are internal interrupts 0..31).
 243      */
 244     for (n = 0; n < 64; n++) {
 245         pic[n] = qdev_get_gpio_in(dev, n);
 246     }
 247
 248     /* Connect the CPUs to the GIC */
 249     for (n = 0; n < smp_cpus; n++) {
 250         DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
 251
 252         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 253         sysbus_connect_irq(busdev, n + smp_cpus,
 254                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 255     }
 256 }
 257
 258 static void a9_daughterboard_init(const VexpressMachineState *vms,
 259                                   ram_addr_t ram_size,
 260                                   const char *cpu_model,
 261                                   qemu_irq *pic)
 262 {
 263     MemoryRegion *sysmem = get_system_memory();
 264     MemoryRegion *ram = g_new(MemoryRegion, 1);
 265     MemoryRegion *lowram = g_new(MemoryRegion, 1);
 266     ram_addr_t low_ram_size;
 267
 268     if (!cpu_model) {
 269         cpu_model = "cortex-a9";
 270     }
 271
 272     if (ram_size > 0x40000000) {
 273         /* 1GB is the maximum the address space permits */
 274         fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
 275         exit(1);
 276     }
 277
 278     memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem",
 279                                          ram_size);
 280     low_ram_size = ram_size;
 281     if (low_ram_size > 0x4000000) {
 282         low_ram_size = 0x4000000;
 283     }
 284     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 285      * address space should in theory be remappable to various
 286      * things including ROM or RAM; we always map the RAM there.
 287      */
 288     memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size);
 289     memory_region_add_subregion(sysmem, 0x0, lowram);
 290     memory_region_add_subregion(sysmem, 0x60000000, ram);
 291
 292     /* 0x1e000000 A9MPCore (SCU) private memory region */
 293     init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic, vms->secure);
 294
 295     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 296
 297     /* 0x10020000 PL111 CLCD (daughterboard) */
 298     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 299
 300     /* 0x10060000 AXI RAM */
 301     /* 0x100e0000 PL341 Dynamic Memory Controller */
 302     /* 0x100e1000 PL354 Static Memory Controller */
 303     /* 0x100e2000 System Configuration Controller */
 304
 305     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 306     /* 0x100e5000 SP805 Watchdog module */
 307     /* 0x100e6000 BP147 TrustZone Protection Controller */
 308     /* 0x100e9000 PL301 'Fast' AXI matrix */
 309     /* 0x100ea000 PL301 'Slow' AXI matrix */
 310     /* 0x100ec000 TrustZone Address Space Controller */
 311     /* 0x10200000 CoreSight debug APB */
 312     /* 0x1e00a000 PL310 L2 Cache Controller */
 313     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 314 }
 315
 316 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
 317  * values are in microvolts.
 318  */
 319 static const uint32_t a9_voltages[] = {
 320     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
 321     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
 322     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
 323     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
 324     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
 325     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
 326 };
 327
 328 /* Reset values for daughterboard oscillators (in Hz) */
 329 static const uint32_t a9_clocks[] = {
 330     45000000, /* AMBA AXI ACLK: 45MHz */
 331     23750000, /* daughterboard CLCD clock: 23.75MHz */
 332     66670000, /* Test chip reference clock: 66.67MHz */
 333 };
 334
 335 static VEDBoardInfo a9_daughterboard = {
 336     .motherboard_map = motherboard_legacy_map,
 337     .loader_start = 0x60000000,
 338     .gic_cpu_if_addr = 0x1e000100,
 339     .proc_id = 0x0c000191,
 340     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
 341     .voltages = a9_voltages,
 342     .num_clocks = ARRAY_SIZE(a9_clocks),
 343     .clocks = a9_clocks,
 344     .init = a9_daughterboard_init,
 345 };
 346
 347 static void a15_daughterboard_init(const VexpressMachineState *vms,
 348                                    ram_addr_t ram_size,
 349                                    const char *cpu_model,
 350                                    qemu_irq *pic)
 351 {
 352     MemoryRegion *sysmem = get_system_memory();
 353     MemoryRegion *ram = g_new(MemoryRegion, 1);
 354     MemoryRegion *sram = g_new(MemoryRegion, 1);
 355
 356     if (!cpu_model) {
 357         cpu_model = "cortex-a15";
 358     }
 359
 360     {
 361         /* We have to use a separate 64 bit variable here to avoid the gcc
 362          * "comparison is always false due to limited range of data type"
 363          * warning if we are on a host where ram_addr_t is 32 bits.
 364          */
 365         uint64_t rsz = ram_size;
 366         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 367             fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
 368             exit(1);
 369         }
 370     }
 371
 372     memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem",
 373                                          ram_size);
 374     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 375     memory_region_add_subregion(sysmem, 0x80000000, ram);
 376
 377     /* 0x2c000000 A15MPCore private memory region (GIC) */
 378     init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic, vms->secure);
 379
 380     /* A15 daughterboard peripherals: */
 381
 382     /* 0x20000000: CoreSight interfaces: not modelled */
 383     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 384     /* 0x2a420000: SCC: not modelled */
 385     /* 0x2a430000: system counter: not modelled */
 386     /* 0x2b000000: HDLCD controller: not modelled */
 387     /* 0x2b060000: SP805 watchdog: not modelled */
 388     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 389     /* 0x2e000000: system SRAM */
 390     memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000,
 391                            &error_fatal);
 392     vmstate_register_ram_global(sram);
 393     memory_region_add_subregion(sysmem, 0x2e000000, sram);
 394
 395     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 396     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 397 }
 398
 399 static const uint32_t a15_voltages[] = {
 400     900000, /* Vcore: 0.9V : CPU core voltage */
 401 };
 402
 403 static const uint32_t a15_clocks[] = {
 404     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
 405     0, /* OSCCLK1: reserved */
 406     0, /* OSCCLK2: reserved */
 407     0, /* OSCCLK3: reserved */
 408     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
 409     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
 410     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
 411     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
 412     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
 413 };
 414
 415 static VEDBoardInfo a15_daughterboard = {
 416     .motherboard_map = motherboard_aseries_map,
 417     .loader_start = 0x80000000,
 418     .gic_cpu_if_addr = 0x2c002000,
 419     .proc_id = 0x14000237,
 420     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
 421     .voltages = a15_voltages,
 422     .num_clocks = ARRAY_SIZE(a15_clocks),
 423     .clocks = a15_clocks,
 424     .init = a15_daughterboard_init,
 425 };
 426
 427 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
 428                                 hwaddr addr, hwaddr size, uint32_t intc,
 429                                 int irq)
 430 {
 431     /* Add a virtio_mmio node to the device tree blob:
 432      *   virtio_mmio@ADDRESS {
 433      *       compatible = "virtio,mmio";
 434      *       reg = <ADDRESS, SIZE>;
 435      *       interrupt-parent = <&intc>;
 436      *       interrupts = <0, irq, 1>;
 437      *   }
 438      * (Note that the format of the interrupts property is dependent on the
 439      * interrupt controller that interrupt-parent points to; these are for
 440      * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
 441      */
 442     int rc;
 443     char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
 444
 445     rc = qemu_fdt_add_subnode(fdt, nodename);
 446     rc |= qemu_fdt_setprop_string(fdt, nodename,
 447                                   "compatible", "virtio,mmio");
 448     rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
 449                                        acells, addr, scells, size);
 450     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
 451     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
 452     g_free(nodename);
 453     if (rc) {
 454         return -1;
 455     }
 456     return 0;
 457 }
 458
 459 static uint32_t find_int_controller(void *fdt)
 460 {
 461     /* Find the FDT node corresponding to the interrupt controller
 462      * for virtio-mmio devices. We do this by scanning the fdt for
 463      * a node with the right compatibility, since we know there is
 464      * only one GIC on a vexpress board.
 465      * We return the phandle of the node, or 0 if none was found.
 466      */
 467     const char *compat = "arm,cortex-a9-gic";
 468     int offset;
 469
 470     offset = fdt_node_offset_by_compatible(fdt, -1, compat);
 471     if (offset >= 0) {
 472         return fdt_get_phandle(fdt, offset);
 473     }
 474     return 0;
 475 }
 476
 477 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
 478 {
 479     uint32_t acells, scells, intc;
 480     const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
 481
 482     acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
 483                                    NULL, &error_fatal);
 484     scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
 485                                    NULL, &error_fatal);
 486     intc = find_int_controller(fdt);
 487     if (!intc) {
 488         /* Not fatal, we just won't provide virtio. This will
 489          * happen with older device tree blobs.
 490          */
 491         fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in "
 492                 "dtb; will not include virtio-mmio devices in the dtb.\n");
 493     } else {
 494         int i;
 495         const hwaddr *map = daughterboard->motherboard_map;
 496
 497         /* We iterate backwards here because adding nodes
 498          * to the dtb puts them in last-first.
 499          */
 500         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 501             add_virtio_mmio_node(fdt, acells, scells,
 502                                  map[VE_VIRTIO] + 0x200 * i,
 503                                  0x200, intc, 40 + i);
 504         }
 505     }
 506 }
 507
 508
 509 /* Open code a private version of pflash registration since we
 510  * need to set non-default device width for VExpress platform.
 511  */
 512 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name,
 513                                           DriveInfo *di)
 514 {
 515     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
 516
 517     if (di) {
 518         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di),
 519                             &error_abort);
 520     }
 521
 522     qdev_prop_set_uint32(dev, "num-blocks",
 523                          VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
 524     qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
 525     qdev_prop_set_uint8(dev, "width", 4);
 526     qdev_prop_set_uint8(dev, "device-width", 2);
 527     qdev_prop_set_bit(dev, "big-endian", false);
 528     qdev_prop_set_uint16(dev, "id0", 0x89);
 529     qdev_prop_set_uint16(dev, "id1", 0x18);
 530     qdev_prop_set_uint16(dev, "id2", 0x00);
 531     qdev_prop_set_uint16(dev, "id3", 0x00);
 532     qdev_prop_set_string(dev, "name", name);
 533     qdev_init_nofail(dev);
 534
 535     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 536     return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
 537 }
 538
 539 static void vexpress_common_init(MachineState *machine)
 540 {
 541     VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
 542     VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
 543     VEDBoardInfo *daughterboard = vmc->daughterboard;
 544     DeviceState *dev, *sysctl, *pl041;
 545     qemu_irq pic[64];
 546     uint32_t sys_id;
 547     DriveInfo *dinfo;
 548     pflash_t *pflash0;
 549     ram_addr_t vram_size, sram_size;
 550     MemoryRegion *sysmem = get_system_memory();
 551     MemoryRegion *vram = g_new(MemoryRegion, 1);
 552     MemoryRegion *sram = g_new(MemoryRegion, 1);
 553     MemoryRegion *flashalias = g_new(MemoryRegion, 1);
 554     MemoryRegion *flash0mem;
 555     const hwaddr *map = daughterboard->motherboard_map;
 556     int i;
 557
 558     daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic);
 559
 560     /*
 561      * If a bios file was provided, attempt to map it into memory
 562      */
 563     if (bios_name) {
 564         char *fn;
 565         int image_size;
 566
 567         if (drive_get(IF_PFLASH, 0, 0)) {
 568             error_report("The contents of the first flash device may be "
 569                          "specified with -bios or with -drive if=pflash... "
 570                          "but you cannot use both options at once");
 571             exit(1);
 572         }
 573         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 574         if (!fn) {
 575             error_report("Could not find ROM image '%s'", bios_name);
 576             exit(1);
 577         }
 578         image_size = load_image_targphys(fn, map[VE_NORFLASH0],
 579                                          VEXPRESS_FLASH_SIZE);
 580         g_free(fn);
 581         if (image_size < 0) {
 582             error_report("Could not load ROM image '%s'", bios_name);
 583             exit(1);
 584         }
 585     }
 586
 587     /* Motherboard peripherals: the wiring is the same but the
 588      * addresses vary between the legacy and A-Series memory maps.
 589      */
 590
 591     sys_id = 0x1190f500;
 592
 593     sysctl = qdev_create(NULL, "realview_sysctl");
 594     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 595     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
 596     qdev_prop_set_uint32(sysctl, "len-db-voltage",
 597                          daughterboard->num_voltage_sensors);
 598     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
 599         char *propname = g_strdup_printf("db-voltage[%d]", i);
 600         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
 601         g_free(propname);
 602     }
 603     qdev_prop_set_uint32(sysctl, "len-db-clock",
 604                          daughterboard->num_clocks);
 605     for (i = 0; i < daughterboard->num_clocks; i++) {
 606         char *propname = g_strdup_printf("db-clock[%d]", i);
 607         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
 608         g_free(propname);
 609     }
 610     qdev_init_nofail(sysctl);
 611     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 612
 613     /* VE_SP810: not modelled */
 614     /* VE_SERIALPCI: not modelled */
 615
 616     pl041 = qdev_create(NULL, "pl041");
 617     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 618     qdev_init_nofail(pl041);
 619     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
 620     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
 621
 622     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 623     /* Wire up MMC card detect and read-only signals */
 624     qdev_connect_gpio_out(dev, 0,
 625                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 626     qdev_connect_gpio_out(dev, 1,
 627                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 628
 629     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 630     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 631
 632     sysbus_create_simple("pl011", map[VE_UART0], pic[5]);
 633     sysbus_create_simple("pl011", map[VE_UART1], pic[6]);
 634     sysbus_create_simple("pl011", map[VE_UART2], pic[7]);
 635     sysbus_create_simple("pl011", map[VE_UART3], pic[8]);
 636
 637     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 638     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 639
 640     /* VE_SERIALDVI: not modelled */
 641
 642     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 643
 644     /* VE_COMPACTFLASH: not modelled */
 645
 646     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 647
 648     dinfo = drive_get_next(IF_PFLASH);
 649     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
 650                                        dinfo);
 651     if (!pflash0) {
 652         fprintf(stderr, "vexpress: error registering flash 0.\n");
 653         exit(1);
 654     }
 655
 656     if (map[VE_NORFLASHALIAS] != -1) {
 657         /* Map flash 0 as an alias into low memory */
 658         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
 659         memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
 660                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);
 661         memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
 662     }
 663
 664     dinfo = drive_get_next(IF_PFLASH);
 665     if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
 666                                   dinfo)) {
 667         fprintf(stderr, "vexpress: error registering flash 1.\n");
 668         exit(1);
 669     }
 670
 671     sram_size = 0x2000000;
 672     memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
 673                            &error_fatal);
 674     vmstate_register_ram_global(sram);
 675     memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
 676
 677     vram_size = 0x800000;
 678     memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
 679                            &error_fatal);
 680     vmstate_register_ram_global(vram);
 681     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
 682
 683     /* 0x4e000000 LAN9118 Ethernet */
 684     if (nd_table[0].used) {
 685         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 686     }
 687
 688     /* VE_USB: not modelled */
 689
 690     /* VE_DAPROM: not modelled */
 691
 692     /* Create mmio transports, so the user can create virtio backends
 693      * (which will be automatically plugged in to the transports). If
 694      * no backend is created the transport will just sit harmlessly idle.
 695      */
 696     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 697         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
 698                              pic[40 + i]);
 699     }
 700
 701     daughterboard->bootinfo.ram_size = machine->ram_size;
 702     daughterboard->bootinfo.kernel_filename = machine->kernel_filename;
 703     daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline;
 704     daughterboard->bootinfo.initrd_filename = machine->initrd_filename;
 705     daughterboard->bootinfo.nb_cpus = smp_cpus;
 706     daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
 707     daughterboard->bootinfo.loader_start = daughterboard->loader_start;
 708     daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
 709     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 710     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 711     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
 712     /* Indicate that when booting Linux we should be in secure state */
 713     daughterboard->bootinfo.secure_boot = true;
 714     arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
 715 }
 716
 717 static bool vexpress_get_secure(Object *obj, Error **errp)
 718 {
 719     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 720
 721     return vms->secure;
 722 }
 723
 724 static void vexpress_set_secure(Object *obj, bool value, Error **errp)
 725 {
 726     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 727
 728     vms->secure = value;
 729 }
 730
 731 static void vexpress_instance_init(Object *obj)
 732 {
 733     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 734
 735     /* EL3 is enabled by default on vexpress */
 736     vms->secure = true;
 737     object_property_add_bool(obj, "secure", vexpress_get_secure,
 738                              vexpress_set_secure, NULL);
 739     object_property_set_description(obj, "secure",
 740                                     "Set on/off to enable/disable the ARM "
 741                                     "Security Extensions (TrustZone)",
 742                                     NULL);
 743 }
 744
 745 static void vexpress_class_init(ObjectClass *oc, void *data)
 746 {
 747     MachineClass *mc = MACHINE_CLASS(oc);
 748
 749     mc->desc = "ARM Versatile Express";
 750     mc->init = vexpress_common_init;
 751     mc->block_default_type = IF_SCSI;
 752     mc->max_cpus = 4;
 753 }
 754
 755 static void vexpress_a9_class_init(ObjectClass *oc, void *data)
 756 {
 757     MachineClass *mc = MACHINE_CLASS(oc);
 758     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 759
 760     mc->desc = "ARM Versatile Express for Cortex-A9";
 761
 762     vmc->daughterboard = &a9_daughterboard;
 763 }
 764
 765 static void vexpress_a15_class_init(ObjectClass *oc, void *data)
 766 {
 767     MachineClass *mc = MACHINE_CLASS(oc);
 768     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 769
 770     mc->desc = "ARM Versatile Express for Cortex-A15";
 771
 772     vmc->daughterboard = &a15_daughterboard;
 773 }
 774
 775 static const TypeInfo vexpress_info = {
 776     .name = TYPE_VEXPRESS_MACHINE,
 777     .parent = TYPE_MACHINE,
 778     .abstract = true,
 779     .instance_size = sizeof(VexpressMachineState),
 780     .instance_init = vexpress_instance_init,
 781     .class_size = sizeof(VexpressMachineClass),
 782     .class_init = vexpress_class_init,
 783 };
 784
 785 static const TypeInfo vexpress_a9_info = {
 786     .name = TYPE_VEXPRESS_A9_MACHINE,
 787     .parent = TYPE_VEXPRESS_MACHINE,
 788     .class_init = vexpress_a9_class_init,
 789 };
 790
 791 static const TypeInfo vexpress_a15_info = {
 792     .name = TYPE_VEXPRESS_A15_MACHINE,
 793     .parent = TYPE_VEXPRESS_MACHINE,
 794     .class_init = vexpress_a15_class_init,
 795 };
 796
 797 static void vexpress_machine_init(void)
 798 {
 799     type_register_static(&vexpress_info);
 800     type_register_static(&vexpress_a9_info);
 801     type_register_static(&vexpress_a15_info);
 802 }
 803
 804 type_init(vexpress_machine_init);