1 /* Support for generating ACPI tables and passing them to Guests
3 * ARM virt ACPI generation
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (C) 2006 Fabrice Bellard
7 * Copyright (C) 2013 Red Hat Inc
9 * Author: Michael S. Tsirkin <mst@redhat.com>
11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
13 * Author: Shannon Zhao <zhaoshenglong@huawei.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
29 #include "qemu-common.h"
30 #include "hw/arm/virt-acpi-build.h"
31 #include "qemu/bitmap.h"
34 #include "target-arm/cpu.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
41 #include "hw/acpi/aml-build.h"
42 #include "hw/pci/pcie_host.h"
43 #include "hw/pci/pci.h"
45 #define ARM_SPI_BASE 32
47 typedef struct VirtAcpiCpuInfo
{
48 DECLARE_BITMAP(found_cpus
, VIRT_ACPI_CPU_ID_LIMIT
);
51 static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo
*cpuinfo
)
55 memset(cpuinfo
->found_cpus
, 0, sizeof cpuinfo
->found_cpus
);
57 set_bit(cpu
->cpu_index
, cpuinfo
->found_cpus
);
61 static void acpi_dsdt_add_cpus(Aml
*scope
, int smp_cpus
)
65 for (i
= 0; i
< smp_cpus
; i
++) {
66 Aml
*dev
= aml_device("C%03x", i
);
67 aml_append(dev
, aml_name_decl("_HID", aml_string("ACPI0007")));
68 aml_append(dev
, aml_name_decl("_UID", aml_int(i
)));
69 aml_append(scope
, dev
);
73 static void acpi_dsdt_add_uart(Aml
*scope
, const MemMapEntry
*uart_memmap
,
76 Aml
*dev
= aml_device("COM0");
77 aml_append(dev
, aml_name_decl("_HID", aml_string("ARMH0011")));
78 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
80 Aml
*crs
= aml_resource_template();
81 aml_append(crs
, aml_memory32_fixed(uart_memmap
->base
,
82 uart_memmap
->size
, AML_READ_WRITE
));
84 aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
85 AML_EXCLUSIVE
, uart_irq
));
86 aml_append(dev
, aml_name_decl("_CRS", crs
));
88 /* The _ADR entry is used to link this device to the UART described
89 * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
91 aml_append(dev
, aml_name_decl("_ADR", aml_int(uart_memmap
->base
)));
93 aml_append(scope
, dev
);
96 static void acpi_dsdt_add_rtc(Aml
*scope
, const MemMapEntry
*rtc_memmap
,
99 Aml
*dev
= aml_device("RTC0");
100 aml_append(dev
, aml_name_decl("_HID", aml_string("LNRO0013")));
101 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
103 Aml
*crs
= aml_resource_template();
104 aml_append(crs
, aml_memory32_fixed(rtc_memmap
->base
,
105 rtc_memmap
->size
, AML_READ_WRITE
));
107 aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
108 AML_EXCLUSIVE
, rtc_irq
));
109 aml_append(dev
, aml_name_decl("_CRS", crs
));
110 aml_append(scope
, dev
);
113 static void acpi_dsdt_add_flash(Aml
*scope
, const MemMapEntry
*flash_memmap
)
116 hwaddr base
= flash_memmap
->base
;
117 hwaddr size
= flash_memmap
->size
;
119 dev
= aml_device("FLS0");
120 aml_append(dev
, aml_name_decl("_HID", aml_string("LNRO0015")));
121 aml_append(dev
, aml_name_decl("_UID", aml_int(0)));
123 crs
= aml_resource_template();
124 aml_append(crs
, aml_memory32_fixed(base
, size
, AML_READ_WRITE
));
125 aml_append(dev
, aml_name_decl("_CRS", crs
));
126 aml_append(scope
, dev
);
128 dev
= aml_device("FLS1");
129 aml_append(dev
, aml_name_decl("_HID", aml_string("LNRO0015")));
130 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
131 crs
= aml_resource_template();
132 aml_append(crs
, aml_memory32_fixed(base
+ size
, size
, AML_READ_WRITE
));
133 aml_append(dev
, aml_name_decl("_CRS", crs
));
134 aml_append(scope
, dev
);
137 static void acpi_dsdt_add_virtio(Aml
*scope
,
138 const MemMapEntry
*virtio_mmio_memmap
,
139 int mmio_irq
, int num
)
141 hwaddr base
= virtio_mmio_memmap
->base
;
142 hwaddr size
= virtio_mmio_memmap
->size
;
146 for (i
= 0; i
< num
; i
++) {
147 Aml
*dev
= aml_device("VR%02u", i
);
148 aml_append(dev
, aml_name_decl("_HID", aml_string("LNRO0005")));
149 aml_append(dev
, aml_name_decl("_UID", aml_int(i
)));
151 Aml
*crs
= aml_resource_template();
152 aml_append(crs
, aml_memory32_fixed(base
, size
, AML_READ_WRITE
));
154 aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
155 AML_EXCLUSIVE
, irq
+ i
));
156 aml_append(dev
, aml_name_decl("_CRS", crs
));
157 aml_append(scope
, dev
);
162 static void acpi_dsdt_add_pci(Aml
*scope
, const MemMapEntry
*memmap
, int irq
)
164 Aml
*method
, *crs
, *ifctx
, *UUID
, *ifctx1
, *elsectx
, *buf
;
166 hwaddr base_mmio
= memmap
[VIRT_PCIE_MMIO
].base
;
167 hwaddr size_mmio
= memmap
[VIRT_PCIE_MMIO
].size
;
168 hwaddr base_pio
= memmap
[VIRT_PCIE_PIO
].base
;
169 hwaddr size_pio
= memmap
[VIRT_PCIE_PIO
].size
;
170 hwaddr base_ecam
= memmap
[VIRT_PCIE_ECAM
].base
;
171 hwaddr size_ecam
= memmap
[VIRT_PCIE_ECAM
].size
;
172 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
174 Aml
*dev
= aml_device("%s", "PCI0");
175 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A08")));
176 aml_append(dev
, aml_name_decl("_CID", aml_string("PNP0A03")));
177 aml_append(dev
, aml_name_decl("_SEG", aml_int(0)));
178 aml_append(dev
, aml_name_decl("_BBN", aml_int(0)));
179 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
180 aml_append(dev
, aml_name_decl("_UID", aml_string("PCI0")));
181 aml_append(dev
, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
183 /* Declare the PCI Routing Table. */
184 Aml
*rt_pkg
= aml_package(nr_pcie_buses
* PCI_NUM_PINS
);
185 for (bus_no
= 0; bus_no
< nr_pcie_buses
; bus_no
++) {
186 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
187 int gsi
= (i
+ bus_no
) % PCI_NUM_PINS
;
188 Aml
*pkg
= aml_package(4);
189 aml_append(pkg
, aml_int((bus_no
<< 16) | 0xFFFF));
190 aml_append(pkg
, aml_int(i
));
191 aml_append(pkg
, aml_name("GSI%d", gsi
));
192 aml_append(pkg
, aml_int(0));
193 aml_append(rt_pkg
, pkg
);
196 aml_append(dev
, aml_name_decl("_PRT", rt_pkg
));
198 /* Create GSI link device */
199 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
200 Aml
*dev_gsi
= aml_device("GSI%d", i
);
201 aml_append(dev_gsi
, aml_name_decl("_HID", aml_string("PNP0C0F")));
202 aml_append(dev_gsi
, aml_name_decl("_UID", aml_int(0)));
203 crs
= aml_resource_template();
205 aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
206 AML_EXCLUSIVE
, irq
+ i
));
207 aml_append(dev_gsi
, aml_name_decl("_PRS", crs
));
208 crs
= aml_resource_template();
210 aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
211 AML_EXCLUSIVE
, irq
+ i
));
212 aml_append(dev_gsi
, aml_name_decl("_CRS", crs
));
213 method
= aml_method("_SRS", 1);
214 aml_append(dev_gsi
, method
);
215 aml_append(dev
, dev_gsi
);
218 method
= aml_method("_CBA", 0);
219 aml_append(method
, aml_return(aml_int(base_ecam
)));
220 aml_append(dev
, method
);
222 method
= aml_method("_CRS", 0);
223 Aml
*rbuf
= aml_resource_template();
225 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
226 0x0000, 0x0000, nr_pcie_buses
- 1, 0x0000,
229 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
230 AML_NON_CACHEABLE
, AML_READ_WRITE
, 0x0000, base_mmio
,
231 base_mmio
+ size_mmio
- 1, 0x0000, size_mmio
));
233 aml_dword_io(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
234 AML_ENTIRE_RANGE
, 0x0000, 0x0000, size_pio
- 1, base_pio
,
237 aml_append(method
, aml_name_decl("RBUF", rbuf
));
238 aml_append(method
, aml_return(rbuf
));
239 aml_append(dev
, method
);
241 /* Declare an _OSC (OS Control Handoff) method */
242 aml_append(dev
, aml_name_decl("SUPP", aml_int(0)));
243 aml_append(dev
, aml_name_decl("CTRL", aml_int(0)));
244 method
= aml_method("_OSC", 4);
246 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
248 /* PCI Firmware Specification 3.0
249 * 4.5.1. _OSC Interface for PCI Host Bridge Devices
250 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
251 * identified by the Universal Unique IDentifier (UUID)
252 * 33DB4D5B-1FF7-401C-9657-7441C03DD766
254 UUID
= aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
255 ifctx
= aml_if(aml_equal(aml_arg(0), UUID
));
257 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
259 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
260 aml_append(ifctx
, aml_store(aml_name("CDW2"), aml_name("SUPP")));
261 aml_append(ifctx
, aml_store(aml_name("CDW3"), aml_name("CTRL")));
262 aml_append(ifctx
, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
265 ifctx1
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
266 aml_append(ifctx1
, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
268 aml_append(ifctx
, ifctx1
);
270 ifctx1
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
271 aml_append(ifctx1
, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
273 aml_append(ifctx
, ifctx1
);
275 aml_append(ifctx
, aml_store(aml_name("CTRL"), aml_name("CDW3")));
276 aml_append(ifctx
, aml_return(aml_arg(3)));
277 aml_append(method
, ifctx
);
279 elsectx
= aml_else();
280 aml_append(elsectx
, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
282 aml_append(elsectx
, aml_return(aml_arg(3)));
283 aml_append(method
, elsectx
);
284 aml_append(dev
, method
);
286 method
= aml_method("_DSM", 4);
288 /* PCI Firmware Specification 3.0
289 * 4.6.1. _DSM for PCI Express Slot Information
290 * The UUID in _DSM in this context is
291 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
293 UUID
= aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
294 ifctx
= aml_if(aml_equal(aml_arg(0), UUID
));
295 ifctx1
= aml_if(aml_equal(aml_arg(2), aml_int(0)));
296 uint8_t byte_list
[1] = {1};
297 buf
= aml_buffer(1, byte_list
);
298 aml_append(ifctx1
, aml_return(buf
));
299 aml_append(ifctx
, ifctx1
);
300 aml_append(method
, ifctx
);
303 buf
= aml_buffer(1, byte_list
);
304 aml_append(method
, aml_return(buf
));
305 aml_append(dev
, method
);
307 Aml
*dev_rp0
= aml_device("%s", "RP0");
308 aml_append(dev_rp0
, aml_name_decl("_ADR", aml_int(0)));
309 aml_append(dev
, dev_rp0
);
310 aml_append(scope
, dev
);
315 build_rsdp(GArray
*rsdp_table
, GArray
*linker
, unsigned rsdt
)
317 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
319 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, 16,
320 true /* fseg memory */);
322 memcpy(&rsdp
->signature
, "RSD PTR ", sizeof(rsdp
->signature
));
323 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, sizeof(rsdp
->oem_id
));
324 rsdp
->length
= cpu_to_le32(sizeof(*rsdp
));
325 rsdp
->revision
= 0x02;
328 rsdp
->rsdt_physical_address
= cpu_to_le32(rsdt
);
329 /* Address to be filled by Guest linker */
330 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_RSDP_FILE
,
331 ACPI_BUILD_TABLE_FILE
,
332 rsdp_table
, &rsdp
->rsdt_physical_address
,
333 sizeof rsdp
->rsdt_physical_address
);
335 /* Checksum to be filled by Guest linker */
336 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
337 rsdp
, rsdp
, sizeof *rsdp
, &rsdp
->checksum
);
343 build_spcr(GArray
*table_data
, GArray
*linker
, VirtGuestInfo
*guest_info
)
345 AcpiSerialPortConsoleRedirection
*spcr
;
346 const MemMapEntry
*uart_memmap
= &guest_info
->memmap
[VIRT_UART
];
347 int irq
= guest_info
->irqmap
[VIRT_UART
] + ARM_SPI_BASE
;
349 spcr
= acpi_data_push(table_data
, sizeof(*spcr
));
351 spcr
->interface_type
= 0x3; /* ARM PL011 UART */
353 spcr
->base_address
.space_id
= AML_SYSTEM_MEMORY
;
354 spcr
->base_address
.bit_width
= 8;
355 spcr
->base_address
.bit_offset
= 0;
356 spcr
->base_address
.access_width
= 1;
357 spcr
->base_address
.address
= cpu_to_le64(uart_memmap
->base
);
359 spcr
->interrupt_types
= (1 << 3); /* Bit[3] ARMH GIC interrupt */
360 spcr
->gsi
= cpu_to_le32(irq
); /* Global System Interrupt */
362 spcr
->baud
= 3; /* Baud Rate: 3 = 9600 */
363 spcr
->parity
= 0; /* No Parity */
364 spcr
->stopbits
= 1; /* 1 Stop bit */
365 spcr
->flowctrl
= (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */
366 spcr
->term_type
= 0; /* Terminal Type: 0 = VT100 */
368 spcr
->pci_device_id
= 0xffff; /* PCI Device ID: not a PCI device */
369 spcr
->pci_vendor_id
= 0xffff; /* PCI Vendor ID: not a PCI device */
371 build_header(linker
, table_data
, (void *)spcr
, "SPCR", sizeof(*spcr
), 2);
375 build_mcfg(GArray
*table_data
, GArray
*linker
, VirtGuestInfo
*guest_info
)
378 const MemMapEntry
*memmap
= guest_info
->memmap
;
379 int len
= sizeof(*mcfg
) + sizeof(mcfg
->allocation
[0]);
381 mcfg
= acpi_data_push(table_data
, len
);
382 mcfg
->allocation
[0].address
= cpu_to_le64(memmap
[VIRT_PCIE_ECAM
].base
);
384 /* Only a single allocation so no need to play with segments */
385 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
386 mcfg
->allocation
[0].start_bus_number
= 0;
387 mcfg
->allocation
[0].end_bus_number
= (memmap
[VIRT_PCIE_ECAM
].size
388 / PCIE_MMCFG_SIZE_MIN
) - 1;
390 build_header(linker
, table_data
, (void *)mcfg
, "MCFG", len
, 5);
395 build_gtdt(GArray
*table_data
, GArray
*linker
)
397 int gtdt_start
= table_data
->len
;
398 AcpiGenericTimerTable
*gtdt
;
400 gtdt
= acpi_data_push(table_data
, sizeof *gtdt
);
401 /* The interrupt values are the same with the device tree when adding 16 */
402 gtdt
->secure_el1_interrupt
= ARCH_TIMER_S_EL1_IRQ
+ 16;
403 gtdt
->secure_el1_flags
= ACPI_EDGE_SENSITIVE
;
405 gtdt
->non_secure_el1_interrupt
= ARCH_TIMER_NS_EL1_IRQ
+ 16;
406 gtdt
->non_secure_el1_flags
= ACPI_EDGE_SENSITIVE
;
408 gtdt
->virtual_timer_interrupt
= ARCH_TIMER_VIRT_IRQ
+ 16;
409 gtdt
->virtual_timer_flags
= ACPI_EDGE_SENSITIVE
;
411 gtdt
->non_secure_el2_interrupt
= ARCH_TIMER_NS_EL2_IRQ
+ 16;
412 gtdt
->non_secure_el2_flags
= ACPI_EDGE_SENSITIVE
;
414 build_header(linker
, table_data
,
415 (void *)(table_data
->data
+ gtdt_start
), "GTDT",
416 table_data
->len
- gtdt_start
, 5);
421 build_madt(GArray
*table_data
, GArray
*linker
, VirtGuestInfo
*guest_info
,
422 VirtAcpiCpuInfo
*cpuinfo
)
424 int madt_start
= table_data
->len
;
425 const MemMapEntry
*memmap
= guest_info
->memmap
;
426 AcpiMultipleApicTable
*madt
;
427 AcpiMadtGenericDistributor
*gicd
;
430 madt
= acpi_data_push(table_data
, sizeof *madt
);
432 for (i
= 0; i
< guest_info
->smp_cpus
; i
++) {
433 AcpiMadtGenericInterrupt
*gicc
= acpi_data_push(table_data
,
435 gicc
->type
= ACPI_APIC_GENERIC_INTERRUPT
;
436 gicc
->length
= sizeof(*gicc
);
437 gicc
->base_address
= memmap
[VIRT_GIC_CPU
].base
;
438 gicc
->cpu_interface_number
= i
;
441 if (test_bit(i
, cpuinfo
->found_cpus
)) {
442 gicc
->flags
= cpu_to_le32(ACPI_GICC_ENABLED
);
446 gicd
= acpi_data_push(table_data
, sizeof *gicd
);
447 gicd
->type
= ACPI_APIC_GENERIC_DISTRIBUTOR
;
448 gicd
->length
= sizeof(*gicd
);
449 gicd
->base_address
= memmap
[VIRT_GIC_DIST
].base
;
451 build_header(linker
, table_data
,
452 (void *)(table_data
->data
+ madt_start
), "APIC",
453 table_data
->len
- madt_start
, 5);
458 build_fadt(GArray
*table_data
, GArray
*linker
, unsigned dsdt
)
460 AcpiFadtDescriptorRev5_1
*fadt
= acpi_data_push(table_data
, sizeof(*fadt
));
462 /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */
463 fadt
->flags
= cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI
);
464 fadt
->arm_boot_flags
= cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2
) |
465 (1 << ACPI_FADT_ARM_PSCI_USE_HVC
));
467 /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */
468 fadt
->minor_revision
= 0x1;
470 fadt
->dsdt
= cpu_to_le32(dsdt
);
471 /* DSDT address to be filled by Guest linker */
472 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
473 ACPI_BUILD_TABLE_FILE
,
474 table_data
, &fadt
->dsdt
,
477 build_header(linker
, table_data
,
478 (void *)fadt
, "FACP", sizeof(*fadt
), 5);
483 build_dsdt(GArray
*table_data
, GArray
*linker
, VirtGuestInfo
*guest_info
)
486 const MemMapEntry
*memmap
= guest_info
->memmap
;
487 const int *irqmap
= guest_info
->irqmap
;
489 dsdt
= init_aml_allocator();
490 /* Reserve space for header */
491 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
493 scope
= aml_scope("\\_SB");
494 acpi_dsdt_add_cpus(scope
, guest_info
->smp_cpus
);
495 acpi_dsdt_add_uart(scope
, &memmap
[VIRT_UART
],
496 (irqmap
[VIRT_UART
] + ARM_SPI_BASE
));
497 acpi_dsdt_add_rtc(scope
, &memmap
[VIRT_RTC
],
498 (irqmap
[VIRT_RTC
] + ARM_SPI_BASE
));
499 acpi_dsdt_add_flash(scope
, &memmap
[VIRT_FLASH
]);
500 acpi_dsdt_add_virtio(scope
, &memmap
[VIRT_MMIO
],
501 (irqmap
[VIRT_MMIO
] + ARM_SPI_BASE
), NUM_VIRTIO_TRANSPORTS
);
502 acpi_dsdt_add_pci(scope
, memmap
, (irqmap
[VIRT_PCIE
] + ARM_SPI_BASE
));
504 aml_append(dsdt
, scope
);
506 /* copy AML table into ACPI tables blob and patch header there */
507 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
508 build_header(linker
, table_data
,
509 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
510 "DSDT", dsdt
->buf
->len
, 5);
511 free_aml_allocator();
515 struct AcpiBuildState
{
516 /* Copy of table in RAM (for patching). */
517 MemoryRegion
*table_mr
;
518 MemoryRegion
*rsdp_mr
;
519 MemoryRegion
*linker_mr
;
520 /* Is table patched? */
522 VirtGuestInfo
*guest_info
;
526 void virt_acpi_build(VirtGuestInfo
*guest_info
, AcpiBuildTables
*tables
)
528 GArray
*table_offsets
;
530 VirtAcpiCpuInfo cpuinfo
;
531 GArray
*tables_blob
= tables
->table_data
;
533 virt_acpi_get_cpu_info(&cpuinfo
);
535 table_offsets
= g_array_new(false, true /* clear */,
538 bios_linker_loader_alloc(tables
->linker
, ACPI_BUILD_TABLE_FILE
,
539 64, false /* high memory */);
542 * The ACPI v5.1 tables for Hardware-reduced ACPI platform are:
551 /* DSDT is pointed to by FADT */
552 dsdt
= tables_blob
->len
;
553 build_dsdt(tables_blob
, tables
->linker
, guest_info
);
555 /* FADT MADT GTDT SPCR pointed to by RSDT */
556 acpi_add_table(table_offsets
, tables_blob
);
557 build_fadt(tables_blob
, tables
->linker
, dsdt
);
559 acpi_add_table(table_offsets
, tables_blob
);
560 build_madt(tables_blob
, tables
->linker
, guest_info
, &cpuinfo
);
562 acpi_add_table(table_offsets
, tables_blob
);
563 build_gtdt(tables_blob
, tables
->linker
);
565 acpi_add_table(table_offsets
, tables_blob
);
566 build_mcfg(tables_blob
, tables
->linker
, guest_info
);
568 acpi_add_table(table_offsets
, tables_blob
);
569 build_spcr(tables_blob
, tables
->linker
, guest_info
);
571 /* RSDT is pointed to by RSDP */
572 rsdt
= tables_blob
->len
;
573 build_rsdt(tables_blob
, tables
->linker
, table_offsets
);
575 /* RSDP is in FSEG memory, so allocate it separately */
576 build_rsdp(tables
->rsdp
, tables
->linker
, rsdt
);
578 /* Cleanup memory that's no longer used. */
579 g_array_free(table_offsets
, true);
582 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
584 uint32_t size
= acpi_data_len(data
);
586 /* Make sure RAM size is correct - in case it got changed
587 * e.g. by migration */
588 memory_region_ram_resize(mr
, size
, &error_abort
);
590 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
591 memory_region_set_dirty(mr
, 0, size
);
594 static void virt_acpi_build_update(void *build_opaque
, uint32_t offset
)
596 AcpiBuildState
*build_state
= build_opaque
;
597 AcpiBuildTables tables
;
599 /* No state to update or already patched? Nothing to do. */
600 if (!build_state
|| build_state
->patched
) {
603 build_state
->patched
= true;
605 acpi_build_tables_init(&tables
);
607 virt_acpi_build(build_state
->guest_info
, &tables
);
609 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
610 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
611 acpi_ram_update(build_state
->linker_mr
, tables
.linker
);
614 acpi_build_tables_cleanup(&tables
, true);
617 static void virt_acpi_build_reset(void *build_opaque
)
619 AcpiBuildState
*build_state
= build_opaque
;
620 build_state
->patched
= false;
623 static MemoryRegion
*acpi_add_rom_blob(AcpiBuildState
*build_state
,
624 GArray
*blob
, const char *name
,
627 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
628 name
, virt_acpi_build_update
, build_state
);
631 static const VMStateDescription vmstate_virt_acpi_build
= {
632 .name
= "virt_acpi_build",
634 .minimum_version_id
= 1,
635 .fields
= (VMStateField
[]) {
636 VMSTATE_BOOL(patched
, AcpiBuildState
),
637 VMSTATE_END_OF_LIST()
641 void virt_acpi_setup(VirtGuestInfo
*guest_info
)
643 AcpiBuildTables tables
;
644 AcpiBuildState
*build_state
;
646 if (!guest_info
->fw_cfg
) {
647 trace_virt_acpi_setup();
652 trace_virt_acpi_setup();
656 build_state
= g_malloc0(sizeof *build_state
);
657 build_state
->guest_info
= guest_info
;
659 acpi_build_tables_init(&tables
);
660 virt_acpi_build(build_state
->guest_info
, &tables
);
662 /* Now expose it all to Guest */
663 build_state
->table_mr
= acpi_add_rom_blob(build_state
, tables
.table_data
,
664 ACPI_BUILD_TABLE_FILE
,
665 ACPI_BUILD_TABLE_MAX_SIZE
);
666 assert(build_state
->table_mr
!= NULL
);
668 build_state
->linker_mr
=
669 acpi_add_rom_blob(build_state
, tables
.linker
, "etc/table-loader", 0);
671 fw_cfg_add_file(guest_info
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
672 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
674 build_state
->rsdp_mr
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
675 ACPI_BUILD_RSDP_FILE
, 0);
677 qemu_register_reset(virt_acpi_build_reset
, build_state
);
678 virt_acpi_build_reset(build_state
);
679 vmstate_register(NULL
, 0, &vmstate_virt_acpi_build
, build_state
);
681 /* Cleanup tables but don't free the memory: we track it
684 acpi_build_tables_cleanup(&tables
, false);