hw/arm/xlnx-versal.c

   1 /*
   2  * Xilinx Versal SoC model.
   3  *
   4  * Copyright (c) 2018 Xilinx Inc.
   5  * Written by Edgar E. Iglesias
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 or
   9  * (at your option) any later version.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "qemu/log.h"
  15 #include "qemu/module.h"
  16 #include "hw/sysbus.h"
  17 #include "net/net.h"
  18 #include "sysemu/sysemu.h"
  19 #include "sysemu/kvm.h"
  20 #include "hw/arm/boot.h"
  21 #include "kvm_arm.h"
  22 #include "hw/misc/unimp.h"
  23 #include "hw/intc/arm_gicv3_common.h"
  24 #include "hw/arm/xlnx-versal.h"
  25 #include "hw/char/pl011.h"
  26
  27 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
  28 #define GEM_REVISION        0x40070106
  29
  30 static void versal_create_apu_cpus(Versal *s)
  31 {
  32     int i;
  33
  34     for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
  35         Object *obj;
  36         char *name;
  37
  38         obj = object_new(XLNX_VERSAL_ACPU_TYPE);
  39         if (!obj) {
  40             /* Secondary CPUs start in PSCI powered-down state */
  41             error_report("Unable to create apu.cpu[%d] of type %s",
  42                          i, XLNX_VERSAL_ACPU_TYPE);
  43             exit(EXIT_FAILURE);
  44         }
  45
  46         name = g_strdup_printf("apu-cpu[%d]", i);
  47         object_property_add_child(OBJECT(s), name, obj, &error_fatal);
  48         g_free(name);
  49
  50         object_property_set_int(obj, s->cfg.psci_conduit,
  51                                 "psci-conduit", &error_abort);
  52         if (i) {
  53             object_property_set_bool(obj, true,
  54                                      "start-powered-off", &error_abort);
  55         }
  56
  57         object_property_set_int(obj, ARRAY_SIZE(s->fpd.apu.cpu),
  58                                 "core-count", &error_abort);
  59         object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
  60                                  &error_abort);
  61         object_property_set_bool(obj, true, "realized", &error_fatal);
  62         s->fpd.apu.cpu[i] = ARM_CPU(obj);
  63     }
  64 }
  65
  66 static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
  67 {
  68     static const uint64_t addrs[] = {
  69         MM_GIC_APU_DIST_MAIN,
  70         MM_GIC_APU_REDIST_0
  71     };
  72     SysBusDevice *gicbusdev;
  73     DeviceState *gicdev;
  74     int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);
  75     int i;
  76
  77     sysbus_init_child_obj(OBJECT(s), "apu-gic",
  78                           &s->fpd.apu.gic, sizeof(s->fpd.apu.gic),
  79                           gicv3_class_name());
  80     gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);
  81     gicdev = DEVICE(&s->fpd.apu.gic);
  82     qdev_prop_set_uint32(gicdev, "revision", 3);
  83     qdev_prop_set_uint32(gicdev, "num-cpu", 2);
  84     qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32);
  85     qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
  86     qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2);
  87     qdev_prop_set_bit(gicdev, "has-security-extensions", true);
  88
  89     object_property_set_bool(OBJECT(&s->fpd.apu.gic), true, "realized",
  90                                     &error_fatal);
  91
  92     for (i = 0; i < ARRAY_SIZE(addrs); i++) {
  93         MemoryRegion *mr;
  94
  95         mr = sysbus_mmio_get_region(gicbusdev, i);
  96         memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr);
  97     }
  98
  99     for (i = 0; i < nr_apu_cpus; i++) {
 100         DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]);
 101         int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
 102         qemu_irq maint_irq;
 103         int ti;
 104         /* Mapping from the output timer irq lines from the CPU to the
 105          * GIC PPI inputs.
 106          */
 107         const int timer_irq[] = {
 108             [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ,
 109             [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ,
 110             [GTIMER_HYP]  = VERSAL_TIMER_NS_EL2_IRQ,
 111             [GTIMER_SEC]  = VERSAL_TIMER_S_EL1_IRQ,
 112         };
 113
 114         for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) {
 115             qdev_connect_gpio_out(cpudev, ti,
 116                                   qdev_get_gpio_in(gicdev,
 117                                                    ppibase + timer_irq[ti]));
 118         }
 119         maint_irq = qdev_get_gpio_in(gicdev,
 120                                         ppibase + VERSAL_GIC_MAINT_IRQ);
 121         qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
 122                                     0, maint_irq);
 123         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 124         sysbus_connect_irq(gicbusdev, i + nr_apu_cpus,
 125                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 126         sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus,
 127                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
 128         sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus,
 129                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
 130     }
 131
 132     for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) {
 133         pic[i] = qdev_get_gpio_in(gicdev, i);
 134     }
 135 }
 136
 137 static void versal_create_uarts(Versal *s, qemu_irq *pic)
 138 {
 139     int i;
 140
 141     for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
 142         static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0};
 143         static const uint64_t addrs[] = { MM_UART0, MM_UART1 };
 144         char *name = g_strdup_printf("uart%d", i);
 145         DeviceState *dev;
 146         MemoryRegion *mr;
 147
 148         dev = qdev_create(NULL, TYPE_PL011);
 149         s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);
 150         qdev_prop_set_chr(dev, "chardev", serial_hd(i));
 151         object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
 152         qdev_init_nofail(dev);
 153
 154         mr = sysbus_mmio_get_region(s->lpd.iou.uart[i], 0);
 155         memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
 156
 157         sysbus_connect_irq(s->lpd.iou.uart[i], 0, pic[irqs[i]]);
 158         g_free(name);
 159     }
 160 }
 161
 162 static void versal_create_gems(Versal *s, qemu_irq *pic)
 163 {
 164     int i;
 165
 166     for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
 167         static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0};
 168         static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 };
 169         char *name = g_strdup_printf("gem%d", i);
 170         NICInfo *nd = &nd_table[i];
 171         DeviceState *dev;
 172         MemoryRegion *mr;
 173
 174         dev = qdev_create(NULL, "cadence_gem");
 175         s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev);
 176         object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
 177         if (nd->used) {
 178             qemu_check_nic_model(nd, "cadence_gem");
 179             qdev_set_nic_properties(dev, nd);
 180         }
 181         object_property_set_int(OBJECT(s->lpd.iou.gem[i]),
 182                                 2, "num-priority-queues",
 183                                 &error_abort);
 184         object_property_set_link(OBJECT(s->lpd.iou.gem[i]),
 185                                  OBJECT(&s->mr_ps), "dma",
 186                                  &error_abort);
 187         qdev_init_nofail(dev);
 188
 189         mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0);
 190         memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
 191
 192         sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]);
 193         g_free(name);
 194     }
 195 }
 196
 197 /* This takes the board allocated linear DDR memory and creates aliases
 198  * for each split DDR range/aperture on the Versal address map.
 199  */
 200 static void versal_map_ddr(Versal *s)
 201 {
 202     uint64_t size = memory_region_size(s->cfg.mr_ddr);
 203     /* Describes the various split DDR access regions.  */
 204     static const struct {
 205         uint64_t base;
 206         uint64_t size;
 207     } addr_ranges[] = {
 208         { MM_TOP_DDR, MM_TOP_DDR_SIZE },
 209         { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
 210         { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
 211         { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
 212     };
 213     uint64_t offset = 0;
 214     int i;
 215
 216     assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges));
 217     for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
 218         char *name;
 219         uint64_t mapsize;
 220
 221         mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
 222         name = g_strdup_printf("noc-ddr-range%d", i);
 223         /* Create the MR alias.  */
 224         memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s),
 225                                  name, s->cfg.mr_ddr,
 226                                  offset, mapsize);
 227
 228         /* Map it onto the NoC MR.  */
 229         memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base,
 230                                     &s->noc.mr_ddr_ranges[i]);
 231         offset += mapsize;
 232         size -= mapsize;
 233         g_free(name);
 234     }
 235 }
 236
 237 static void versal_unimp_area(Versal *s, const char *name,
 238                                 MemoryRegion *mr,
 239                                 hwaddr base, hwaddr size)
 240 {
 241     DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
 242     MemoryRegion *mr_dev;
 243
 244     qdev_prop_set_string(dev, "name", name);
 245     qdev_prop_set_uint64(dev, "size", size);
 246     object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
 247     qdev_init_nofail(dev);
 248
 249     mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 250     memory_region_add_subregion(mr, base, mr_dev);
 251 }
 252
 253 static void versal_unimp(Versal *s)
 254 {
 255     versal_unimp_area(s, "psm", &s->mr_ps,
 256                         MM_PSM_START, MM_PSM_END - MM_PSM_START);
 257     versal_unimp_area(s, "crl", &s->mr_ps,
 258                         MM_CRL, MM_CRL_SIZE);
 259     versal_unimp_area(s, "crf", &s->mr_ps,
 260                         MM_FPD_CRF, MM_FPD_CRF_SIZE);
 261     versal_unimp_area(s, "crp", &s->mr_ps,
 262                         MM_PMC_CRP, MM_PMC_CRP_SIZE);
 263     versal_unimp_area(s, "iou-scntr", &s->mr_ps,
 264                         MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
 265     versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
 266                         MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE);
 267 }
 268
 269 static void versal_realize(DeviceState *dev, Error **errp)
 270 {
 271     Versal *s = XLNX_VERSAL(dev);
 272     qemu_irq pic[XLNX_VERSAL_NR_IRQS];
 273
 274     versal_create_apu_cpus(s);
 275     versal_create_apu_gic(s, pic);
 276     versal_create_uarts(s, pic);
 277     versal_create_gems(s, pic);
 278     versal_map_ddr(s);
 279     versal_unimp(s);
 280
 281     /* Create the On Chip Memory (OCM).  */
 282     memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm",
 283                            MM_OCM_SIZE, &error_fatal);
 284
 285     memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
 286     memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
 287 }
 288
 289 static void versal_init(Object *obj)
 290 {
 291     Versal *s = XLNX_VERSAL(obj);
 292
 293     memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
 294     memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
 295 }
 296
 297 static Property versal_properties[] = {
 298     DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION,
 299                      MemoryRegion *),
 300     DEFINE_PROP_UINT32("psci-conduit", Versal, cfg.psci_conduit, 0),
 301     DEFINE_PROP_END_OF_LIST()
 302 };
 303
 304 static void versal_class_init(ObjectClass *klass, void *data)
 305 {
 306     DeviceClass *dc = DEVICE_CLASS(klass);
 307
 308     dc->realize = versal_realize;
 309     device_class_set_props(dc, versal_properties);
 310     /* No VMSD since we haven't got any top-level SoC state to save.  */
 311 }
 312
 313 static const TypeInfo versal_info = {
 314     .name = TYPE_XLNX_VERSAL,
 315     .parent = TYPE_SYS_BUS_DEVICE,
 316     .instance_size = sizeof(Versal),
 317     .instance_init = versal_init,
 318     .class_init = versal_class_init,
 319 };
 320
 321 static void versal_register_types(void)
 322 {
 323     type_register_static(&versal_info);
 324 }
 325
 326 type_init(versal_register_types);