2 * Xilinx Versal SoC model.
4 * Copyright (c) 2018 Xilinx Inc.
5 * Written by Edgar E. Iglesias
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
15 #include "qemu/module.h"
16 #include "hw/sysbus.h"
18 #include "sysemu/sysemu.h"
19 #include "sysemu/kvm.h"
20 #include "hw/arm/boot.h"
22 #include "hw/misc/unimp.h"
23 #include "hw/intc/arm_gicv3_common.h"
24 #include "hw/arm/xlnx-versal.h"
25 #include "hw/char/pl011.h"
27 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
28 #define GEM_REVISION 0x40070106
30 static void versal_create_apu_cpus(Versal
*s
)
34 for (i
= 0; i
< ARRAY_SIZE(s
->fpd
.apu
.cpu
); i
++) {
38 obj
= object_new(XLNX_VERSAL_ACPU_TYPE
);
40 /* Secondary CPUs start in PSCI powered-down state */
41 error_report("Unable to create apu.cpu[%d] of type %s",
42 i
, XLNX_VERSAL_ACPU_TYPE
);
46 name
= g_strdup_printf("apu-cpu[%d]", i
);
47 object_property_add_child(OBJECT(s
), name
, obj
, &error_fatal
);
50 object_property_set_int(obj
, s
->cfg
.psci_conduit
,
51 "psci-conduit", &error_abort
);
53 object_property_set_bool(obj
, true,
54 "start-powered-off", &error_abort
);
57 object_property_set_int(obj
, ARRAY_SIZE(s
->fpd
.apu
.cpu
),
58 "core-count", &error_abort
);
59 object_property_set_link(obj
, OBJECT(&s
->fpd
.apu
.mr
), "memory",
61 object_property_set_bool(obj
, true, "realized", &error_fatal
);
62 s
->fpd
.apu
.cpu
[i
] = ARM_CPU(obj
);
66 static void versal_create_apu_gic(Versal
*s
, qemu_irq
*pic
)
68 static const uint64_t addrs
[] = {
72 SysBusDevice
*gicbusdev
;
74 int nr_apu_cpus
= ARRAY_SIZE(s
->fpd
.apu
.cpu
);
77 sysbus_init_child_obj(OBJECT(s
), "apu-gic",
78 &s
->fpd
.apu
.gic
, sizeof(s
->fpd
.apu
.gic
),
80 gicbusdev
= SYS_BUS_DEVICE(&s
->fpd
.apu
.gic
);
81 gicdev
= DEVICE(&s
->fpd
.apu
.gic
);
82 qdev_prop_set_uint32(gicdev
, "revision", 3);
83 qdev_prop_set_uint32(gicdev
, "num-cpu", 2);
84 qdev_prop_set_uint32(gicdev
, "num-irq", XLNX_VERSAL_NR_IRQS
+ 32);
85 qdev_prop_set_uint32(gicdev
, "len-redist-region-count", 1);
86 qdev_prop_set_uint32(gicdev
, "redist-region-count[0]", 2);
87 qdev_prop_set_bit(gicdev
, "has-security-extensions", true);
89 object_property_set_bool(OBJECT(&s
->fpd
.apu
.gic
), true, "realized",
92 for (i
= 0; i
< ARRAY_SIZE(addrs
); i
++) {
95 mr
= sysbus_mmio_get_region(gicbusdev
, i
);
96 memory_region_add_subregion(&s
->fpd
.apu
.mr
, addrs
[i
], mr
);
99 for (i
= 0; i
< nr_apu_cpus
; i
++) {
100 DeviceState
*cpudev
= DEVICE(s
->fpd
.apu
.cpu
[i
]);
101 int ppibase
= XLNX_VERSAL_NR_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
104 /* Mapping from the output timer irq lines from the CPU to the
107 const int timer_irq
[] = {
108 [GTIMER_PHYS
] = VERSAL_TIMER_NS_EL1_IRQ
,
109 [GTIMER_VIRT
] = VERSAL_TIMER_VIRT_IRQ
,
110 [GTIMER_HYP
] = VERSAL_TIMER_NS_EL2_IRQ
,
111 [GTIMER_SEC
] = VERSAL_TIMER_S_EL1_IRQ
,
114 for (ti
= 0; ti
< ARRAY_SIZE(timer_irq
); ti
++) {
115 qdev_connect_gpio_out(cpudev
, ti
,
116 qdev_get_gpio_in(gicdev
,
117 ppibase
+ timer_irq
[ti
]));
119 maint_irq
= qdev_get_gpio_in(gicdev
,
120 ppibase
+ VERSAL_GIC_MAINT_IRQ
);
121 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
123 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
124 sysbus_connect_irq(gicbusdev
, i
+ nr_apu_cpus
,
125 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
126 sysbus_connect_irq(gicbusdev
, i
+ 2 * nr_apu_cpus
,
127 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
128 sysbus_connect_irq(gicbusdev
, i
+ 3 * nr_apu_cpus
,
129 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
132 for (i
= 0; i
< XLNX_VERSAL_NR_IRQS
; i
++) {
133 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
137 static void versal_create_uarts(Versal
*s
, qemu_irq
*pic
)
141 for (i
= 0; i
< ARRAY_SIZE(s
->lpd
.iou
.uart
); i
++) {
142 static const int irqs
[] = { VERSAL_UART0_IRQ_0
, VERSAL_UART1_IRQ_0
};
143 static const uint64_t addrs
[] = { MM_UART0
, MM_UART1
};
144 char *name
= g_strdup_printf("uart%d", i
);
148 dev
= qdev_create(NULL
, TYPE_PL011
);
149 s
->lpd
.iou
.uart
[i
] = SYS_BUS_DEVICE(dev
);
150 qdev_prop_set_chr(dev
, "chardev", serial_hd(i
));
151 object_property_add_child(OBJECT(s
), name
, OBJECT(dev
), &error_fatal
);
152 qdev_init_nofail(dev
);
154 mr
= sysbus_mmio_get_region(s
->lpd
.iou
.uart
[i
], 0);
155 memory_region_add_subregion(&s
->mr_ps
, addrs
[i
], mr
);
157 sysbus_connect_irq(s
->lpd
.iou
.uart
[i
], 0, pic
[irqs
[i
]]);
162 static void versal_create_gems(Versal
*s
, qemu_irq
*pic
)
166 for (i
= 0; i
< ARRAY_SIZE(s
->lpd
.iou
.gem
); i
++) {
167 static const int irqs
[] = { VERSAL_GEM0_IRQ_0
, VERSAL_GEM1_IRQ_0
};
168 static const uint64_t addrs
[] = { MM_GEM0
, MM_GEM1
};
169 char *name
= g_strdup_printf("gem%d", i
);
170 NICInfo
*nd
= &nd_table
[i
];
174 dev
= qdev_create(NULL
, "cadence_gem");
175 s
->lpd
.iou
.gem
[i
] = SYS_BUS_DEVICE(dev
);
176 object_property_add_child(OBJECT(s
), name
, OBJECT(dev
), &error_fatal
);
178 qemu_check_nic_model(nd
, "cadence_gem");
179 qdev_set_nic_properties(dev
, nd
);
181 object_property_set_int(OBJECT(s
->lpd
.iou
.gem
[i
]),
182 2, "num-priority-queues",
184 object_property_set_link(OBJECT(s
->lpd
.iou
.gem
[i
]),
185 OBJECT(&s
->mr_ps
), "dma",
187 qdev_init_nofail(dev
);
189 mr
= sysbus_mmio_get_region(s
->lpd
.iou
.gem
[i
], 0);
190 memory_region_add_subregion(&s
->mr_ps
, addrs
[i
], mr
);
192 sysbus_connect_irq(s
->lpd
.iou
.gem
[i
], 0, pic
[irqs
[i
]]);
197 static void versal_create_admas(Versal
*s
, qemu_irq
*pic
)
201 for (i
= 0; i
< ARRAY_SIZE(s
->lpd
.iou
.adma
); i
++) {
202 char *name
= g_strdup_printf("adma%d", i
);
206 dev
= qdev_create(NULL
, "xlnx.zdma");
207 s
->lpd
.iou
.adma
[i
] = SYS_BUS_DEVICE(dev
);
208 object_property_add_child(OBJECT(s
), name
, OBJECT(dev
), &error_fatal
);
209 qdev_init_nofail(dev
);
211 mr
= sysbus_mmio_get_region(s
->lpd
.iou
.adma
[i
], 0);
212 memory_region_add_subregion(&s
->mr_ps
,
213 MM_ADMA_CH0
+ i
* MM_ADMA_CH0_SIZE
, mr
);
215 sysbus_connect_irq(s
->lpd
.iou
.adma
[i
], 0, pic
[VERSAL_ADMA_IRQ_0
+ i
]);
220 /* This takes the board allocated linear DDR memory and creates aliases
221 * for each split DDR range/aperture on the Versal address map.
223 static void versal_map_ddr(Versal
*s
)
225 uint64_t size
= memory_region_size(s
->cfg
.mr_ddr
);
226 /* Describes the various split DDR access regions. */
227 static const struct {
231 { MM_TOP_DDR
, MM_TOP_DDR_SIZE
},
232 { MM_TOP_DDR_2
, MM_TOP_DDR_2_SIZE
},
233 { MM_TOP_DDR_3
, MM_TOP_DDR_3_SIZE
},
234 { MM_TOP_DDR_4
, MM_TOP_DDR_4_SIZE
}
239 assert(ARRAY_SIZE(addr_ranges
) == ARRAY_SIZE(s
->noc
.mr_ddr_ranges
));
240 for (i
= 0; i
< ARRAY_SIZE(addr_ranges
) && size
; i
++) {
244 mapsize
= size
< addr_ranges
[i
].size
? size
: addr_ranges
[i
].size
;
245 name
= g_strdup_printf("noc-ddr-range%d", i
);
246 /* Create the MR alias. */
247 memory_region_init_alias(&s
->noc
.mr_ddr_ranges
[i
], OBJECT(s
),
251 /* Map it onto the NoC MR. */
252 memory_region_add_subregion(&s
->mr_ps
, addr_ranges
[i
].base
,
253 &s
->noc
.mr_ddr_ranges
[i
]);
260 static void versal_unimp_area(Versal
*s
, const char *name
,
262 hwaddr base
, hwaddr size
)
264 DeviceState
*dev
= qdev_create(NULL
, TYPE_UNIMPLEMENTED_DEVICE
);
265 MemoryRegion
*mr_dev
;
267 qdev_prop_set_string(dev
, "name", name
);
268 qdev_prop_set_uint64(dev
, "size", size
);
269 object_property_add_child(OBJECT(s
), name
, OBJECT(dev
), &error_fatal
);
270 qdev_init_nofail(dev
);
272 mr_dev
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
273 memory_region_add_subregion(mr
, base
, mr_dev
);
276 static void versal_unimp(Versal
*s
)
278 versal_unimp_area(s
, "psm", &s
->mr_ps
,
279 MM_PSM_START
, MM_PSM_END
- MM_PSM_START
);
280 versal_unimp_area(s
, "crl", &s
->mr_ps
,
281 MM_CRL
, MM_CRL_SIZE
);
282 versal_unimp_area(s
, "crf", &s
->mr_ps
,
283 MM_FPD_CRF
, MM_FPD_CRF_SIZE
);
284 versal_unimp_area(s
, "crp", &s
->mr_ps
,
285 MM_PMC_CRP
, MM_PMC_CRP_SIZE
);
286 versal_unimp_area(s
, "iou-scntr", &s
->mr_ps
,
287 MM_IOU_SCNTR
, MM_IOU_SCNTR_SIZE
);
288 versal_unimp_area(s
, "iou-scntr-seucre", &s
->mr_ps
,
289 MM_IOU_SCNTRS
, MM_IOU_SCNTRS_SIZE
);
292 static void versal_realize(DeviceState
*dev
, Error
**errp
)
294 Versal
*s
= XLNX_VERSAL(dev
);
295 qemu_irq pic
[XLNX_VERSAL_NR_IRQS
];
297 versal_create_apu_cpus(s
);
298 versal_create_apu_gic(s
, pic
);
299 versal_create_uarts(s
, pic
);
300 versal_create_gems(s
, pic
);
301 versal_create_admas(s
, pic
);
305 /* Create the On Chip Memory (OCM). */
306 memory_region_init_ram(&s
->lpd
.mr_ocm
, OBJECT(s
), "ocm",
307 MM_OCM_SIZE
, &error_fatal
);
309 memory_region_add_subregion_overlap(&s
->mr_ps
, MM_OCM
, &s
->lpd
.mr_ocm
, 0);
310 memory_region_add_subregion_overlap(&s
->fpd
.apu
.mr
, 0, &s
->mr_ps
, 0);
313 static void versal_init(Object
*obj
)
315 Versal
*s
= XLNX_VERSAL(obj
);
317 memory_region_init(&s
->fpd
.apu
.mr
, obj
, "mr-apu", UINT64_MAX
);
318 memory_region_init(&s
->mr_ps
, obj
, "mr-ps-switch", UINT64_MAX
);
321 static Property versal_properties
[] = {
322 DEFINE_PROP_LINK("ddr", Versal
, cfg
.mr_ddr
, TYPE_MEMORY_REGION
,
324 DEFINE_PROP_UINT32("psci-conduit", Versal
, cfg
.psci_conduit
, 0),
325 DEFINE_PROP_END_OF_LIST()
328 static void versal_class_init(ObjectClass
*klass
, void *data
)
330 DeviceClass
*dc
= DEVICE_CLASS(klass
);
332 dc
->realize
= versal_realize
;
333 device_class_set_props(dc
, versal_properties
);
334 /* No VMSD since we haven't got any top-level SoC state to save. */
337 static const TypeInfo versal_info
= {
338 .name
= TYPE_XLNX_VERSAL
,
339 .parent
= TYPE_SYS_BUS_DEVICE
,
340 .instance_size
= sizeof(Versal
),
341 .instance_init
= versal_init
,
342 .class_init
= versal_class_init
,
345 static void versal_register_types(void)
347 type_register_static(&versal_info
);
350 type_init(versal_register_types
);