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[mirror_qemu.git] / hw / arm / xlnx-zcu102.c
1 /*
2 * Xilinx ZynqMP ZCU102 board
3 *
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "cpu.h"
21 #include "hw/arm/xlnx-zynqmp.h"
22 #include "hw/boards.h"
23 #include "qemu/error-report.h"
24 #include "qemu/log.h"
25 #include "sysemu/qtest.h"
26
27 typedef struct XlnxZCU102 {
28 MachineState parent_obj;
29
30 XlnxZynqMPState soc;
31
32 bool secure;
33 bool virt;
34 } XlnxZCU102;
35
36 #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
37 #define ZCU102_MACHINE(obj) \
38 OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE)
39
40 static struct arm_boot_info xlnx_zcu102_binfo;
41
42 static bool zcu102_get_secure(Object *obj, Error **errp)
43 {
44 XlnxZCU102 *s = ZCU102_MACHINE(obj);
45
46 return s->secure;
47 }
48
49 static void zcu102_set_secure(Object *obj, bool value, Error **errp)
50 {
51 XlnxZCU102 *s = ZCU102_MACHINE(obj);
52
53 s->secure = value;
54 }
55
56 static bool zcu102_get_virt(Object *obj, Error **errp)
57 {
58 XlnxZCU102 *s = ZCU102_MACHINE(obj);
59
60 return s->virt;
61 }
62
63 static void zcu102_set_virt(Object *obj, bool value, Error **errp)
64 {
65 XlnxZCU102 *s = ZCU102_MACHINE(obj);
66
67 s->virt = value;
68 }
69
70 static void xlnx_zcu102_init(MachineState *machine)
71 {
72 XlnxZCU102 *s = ZCU102_MACHINE(machine);
73 int i;
74 uint64_t ram_size = machine->ram_size;
75
76 /* Create the memory region to pass to the SoC */
77 if (ram_size > XLNX_ZYNQMP_MAX_RAM_SIZE) {
78 error_report("ERROR: RAM size 0x%" PRIx64 " above max supported of "
79 "0x%llx", ram_size,
80 XLNX_ZYNQMP_MAX_RAM_SIZE);
81 exit(1);
82 }
83
84 if (ram_size < 0x08000000) {
85 qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102",
86 ram_size);
87 }
88
89 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
90 TYPE_XLNX_ZYNQMP, &error_abort, NULL);
91
92 object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
93 "ddr-ram", &error_abort);
94 object_property_set_bool(OBJECT(&s->soc), s->secure, "secure",
95 &error_fatal);
96 object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization",
97 &error_fatal);
98
99 object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
100
101 /* Create and plug in the SD cards */
102 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
103 BusState *bus;
104 DriveInfo *di = drive_get_next(IF_SD);
105 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
106 DeviceState *carddev;
107 char *bus_name;
108
109 bus_name = g_strdup_printf("sd-bus%d", i);
110 bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
111 g_free(bus_name);
112 if (!bus) {
113 error_report("No SD bus found for SD card %d", i);
114 exit(1);
115 }
116 carddev = qdev_create(bus, TYPE_SD_CARD);
117 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
118 object_property_set_bool(OBJECT(carddev), true, "realized",
119 &error_fatal);
120 }
121
122 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
123 SSIBus *spi_bus;
124 DeviceState *flash_dev;
125 qemu_irq cs_line;
126 DriveInfo *dinfo = drive_get_next(IF_MTD);
127 gchar *bus_name = g_strdup_printf("spi%d", i);
128
129 spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
130 g_free(bus_name);
131
132 flash_dev = ssi_create_slave_no_init(spi_bus, "sst25wf080");
133 if (dinfo) {
134 qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo),
135 &error_fatal);
136 }
137 qdev_init_nofail(flash_dev);
138
139 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
140
141 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line);
142 }
143
144 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) {
145 SSIBus *spi_bus;
146 DeviceState *flash_dev;
147 qemu_irq cs_line;
148 DriveInfo *dinfo = drive_get_next(IF_MTD);
149 int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS;
150 gchar *bus_name = g_strdup_printf("qspi%d", bus);
151
152 spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
153 g_free(bus_name);
154
155 flash_dev = ssi_create_slave_no_init(spi_bus, "n25q512a11");
156 if (dinfo) {
157 qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo),
158 &error_fatal);
159 }
160 qdev_init_nofail(flash_dev);
161
162 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
163
164 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line);
165 }
166
167 /* TODO create and connect IDE devices for ide_drive_get() */
168
169 xlnx_zcu102_binfo.ram_size = ram_size;
170 xlnx_zcu102_binfo.loader_start = 0;
171 arm_load_kernel(s->soc.boot_cpu_ptr, machine, &xlnx_zcu102_binfo);
172 }
173
174 static void xlnx_zcu102_machine_instance_init(Object *obj)
175 {
176 XlnxZCU102 *s = ZCU102_MACHINE(obj);
177
178 /* Default to secure mode being disabled */
179 s->secure = false;
180 object_property_add_bool(obj, "secure", zcu102_get_secure,
181 zcu102_set_secure, NULL);
182 object_property_set_description(obj, "secure",
183 "Set on/off to enable/disable the ARM "
184 "Security Extensions (TrustZone)",
185 NULL);
186
187 /* Default to virt (EL2) being disabled */
188 s->virt = false;
189 object_property_add_bool(obj, "virtualization", zcu102_get_virt,
190 zcu102_set_virt, NULL);
191 object_property_set_description(obj, "virtualization",
192 "Set on/off to enable/disable emulating a "
193 "guest CPU which implements the ARM "
194 "Virtualization Extensions",
195 NULL);
196 }
197
198 static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
199 {
200 MachineClass *mc = MACHINE_CLASS(oc);
201
202 mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on " \
203 "the value of smp";
204 mc->init = xlnx_zcu102_init;
205 mc->block_default_type = IF_IDE;
206 mc->units_per_default_bus = 1;
207 mc->ignore_memory_transaction_failures = true;
208 mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
209 mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
210 mc->default_ram_id = "ddr-ram";
211 }
212
213 static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
214 .name = MACHINE_TYPE_NAME("xlnx-zcu102"),
215 .parent = TYPE_MACHINE,
216 .class_init = xlnx_zcu102_machine_class_init,
217 .instance_init = xlnx_zcu102_machine_instance_init,
218 .instance_size = sizeof(XlnxZCU102),
219 };
220
221 static void xlnx_zcu102_machine_init_register_types(void)
222 {
223 type_register_static(&xlnx_zcu102_machine_init_typeinfo);
224 }
225
226 type_init(xlnx_zcu102_machine_init_register_types)