2 * Xilinx Zynq MPSoC emulation
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu-common.h"
22 #include "hw/arm/xlnx-zynqmp.h"
23 #include "hw/intc/arm_gic_common.h"
24 #include "exec/address-spaces.h"
25 #include "sysemu/kvm.h"
28 #define GIC_NUM_SPI_INTR 160
30 #define ARM_PHYS_TIMER_PPI 30
31 #define ARM_VIRT_TIMER_PPI 27
33 #define GEM_REVISION 0x40070106
35 #define GIC_BASE_ADDR 0xf9000000
36 #define GIC_DIST_ADDR 0xf9010000
37 #define GIC_CPU_ADDR 0xf9020000
40 #define SATA_ADDR 0xFD0C0000
41 #define SATA_NUM_PORTS 2
43 #define QSPI_ADDR 0xff0f0000
44 #define LQSPI_ADDR 0xc0000000
47 #define DP_ADDR 0xfd4a0000
50 #define DPDMA_ADDR 0xfd4c0000
53 #define IPI_ADDR 0xFF300000
56 #define RTC_ADDR 0xffa60000
59 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
61 static const uint64_t gem_addr
[XLNX_ZYNQMP_NUM_GEMS
] = {
62 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
65 static const int gem_intr
[XLNX_ZYNQMP_NUM_GEMS
] = {
69 static const uint64_t uart_addr
[XLNX_ZYNQMP_NUM_UARTS
] = {
70 0xFF000000, 0xFF010000,
73 static const int uart_intr
[XLNX_ZYNQMP_NUM_UARTS
] = {
77 static const uint64_t sdhci_addr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
78 0xFF160000, 0xFF170000,
81 static const int sdhci_intr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
85 static const uint64_t spi_addr
[XLNX_ZYNQMP_NUM_SPIS
] = {
86 0xFF040000, 0xFF050000,
89 static const int spi_intr
[XLNX_ZYNQMP_NUM_SPIS
] = {
93 typedef struct XlnxZynqMPGICRegion
{
96 } XlnxZynqMPGICRegion
;
98 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions
[] = {
99 { .region_index
= 0, .address
= GIC_DIST_ADDR
, },
100 { .region_index
= 1, .address
= GIC_CPU_ADDR
, },
103 static inline int arm_gic_ppi_index(int cpu_nr
, int ppi_index
)
105 return GIC_NUM_SPI_INTR
+ cpu_nr
* GIC_INTERNAL
+ ppi_index
;
108 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState
*s
, const char *boot_cpu
,
113 int num_rpus
= MIN(smp_cpus
- XLNX_ZYNQMP_NUM_APU_CPUS
, XLNX_ZYNQMP_NUM_RPU_CPUS
);
115 for (i
= 0; i
< num_rpus
; i
++) {
118 object_initialize(&s
->rpu_cpu
[i
], sizeof(s
->rpu_cpu
[i
]),
119 "cortex-r5-" TYPE_ARM_CPU
);
120 object_property_add_child(OBJECT(s
), "rpu-cpu[*]",
121 OBJECT(&s
->rpu_cpu
[i
]), &error_abort
);
123 name
= object_get_canonical_path_component(OBJECT(&s
->rpu_cpu
[i
]));
124 if (strcmp(name
, boot_cpu
)) {
125 /* Secondary CPUs start in PSCI powered-down state */
126 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true,
127 "start-powered-off", &error_abort
);
129 s
->boot_cpu_ptr
= &s
->rpu_cpu
[i
];
133 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true, "reset-hivecs",
135 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true, "realized",
138 error_propagate(errp
, err
);
144 static void xlnx_zynqmp_init(Object
*obj
)
146 XlnxZynqMPState
*s
= XLNX_ZYNQMP(obj
);
148 int num_apus
= MIN(smp_cpus
, XLNX_ZYNQMP_NUM_APU_CPUS
);
150 for (i
= 0; i
< num_apus
; i
++) {
151 object_initialize(&s
->apu_cpu
[i
], sizeof(s
->apu_cpu
[i
]),
152 "cortex-a53-" TYPE_ARM_CPU
);
153 object_property_add_child(obj
, "apu-cpu[*]", OBJECT(&s
->apu_cpu
[i
]),
157 object_initialize(&s
->gic
, sizeof(s
->gic
), gic_class_name());
158 qdev_set_parent_bus(DEVICE(&s
->gic
), sysbus_get_default());
160 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
161 object_initialize(&s
->gem
[i
], sizeof(s
->gem
[i
]), TYPE_CADENCE_GEM
);
162 qdev_set_parent_bus(DEVICE(&s
->gem
[i
]), sysbus_get_default());
165 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
166 object_initialize(&s
->uart
[i
], sizeof(s
->uart
[i
]), TYPE_CADENCE_UART
);
167 qdev_set_parent_bus(DEVICE(&s
->uart
[i
]), sysbus_get_default());
170 object_initialize(&s
->sata
, sizeof(s
->sata
), TYPE_SYSBUS_AHCI
);
171 qdev_set_parent_bus(DEVICE(&s
->sata
), sysbus_get_default());
173 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
174 object_initialize(&s
->sdhci
[i
], sizeof(s
->sdhci
[i
]),
176 qdev_set_parent_bus(DEVICE(&s
->sdhci
[i
]),
177 sysbus_get_default());
180 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SPIS
; i
++) {
181 object_initialize(&s
->spi
[i
], sizeof(s
->spi
[i
]),
183 qdev_set_parent_bus(DEVICE(&s
->spi
[i
]), sysbus_get_default());
186 object_initialize(&s
->qspi
, sizeof(s
->qspi
), TYPE_XLNX_ZYNQMP_QSPIPS
);
187 qdev_set_parent_bus(DEVICE(&s
->qspi
), sysbus_get_default());
189 object_initialize(&s
->dp
, sizeof(s
->dp
), TYPE_XLNX_DP
);
190 qdev_set_parent_bus(DEVICE(&s
->dp
), sysbus_get_default());
192 object_initialize(&s
->dpdma
, sizeof(s
->dpdma
), TYPE_XLNX_DPDMA
);
193 qdev_set_parent_bus(DEVICE(&s
->dpdma
), sysbus_get_default());
195 object_initialize(&s
->ipi
, sizeof(s
->ipi
), TYPE_XLNX_ZYNQMP_IPI
);
196 qdev_set_parent_bus(DEVICE(&s
->ipi
), sysbus_get_default());
198 object_initialize(&s
->rtc
, sizeof(s
->rtc
), TYPE_XLNX_ZYNQMP_RTC
);
199 qdev_set_parent_bus(DEVICE(&s
->rtc
), sysbus_get_default());
202 static void xlnx_zynqmp_realize(DeviceState
*dev
, Error
**errp
)
204 XlnxZynqMPState
*s
= XLNX_ZYNQMP(dev
);
205 MemoryRegion
*system_memory
= get_system_memory();
208 int num_apus
= MIN(smp_cpus
, XLNX_ZYNQMP_NUM_APU_CPUS
);
209 const char *boot_cpu
= s
->boot_cpu
? s
->boot_cpu
: "apu-cpu[0]";
210 ram_addr_t ddr_low_size
, ddr_high_size
;
211 qemu_irq gic_spi
[GIC_NUM_SPI_INTR
];
214 ram_size
= memory_region_size(s
->ddr_ram
);
216 /* Create the DDR Memory Regions. User friendly checks should happen at
219 if (ram_size
> XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
) {
220 /* The RAM size is above the maximum available for the low DDR.
221 * Create the high DDR memory region as well.
223 assert(ram_size
<= XLNX_ZYNQMP_MAX_RAM_SIZE
);
224 ddr_low_size
= XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
225 ddr_high_size
= ram_size
- XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
227 memory_region_init_alias(&s
->ddr_ram_high
, NULL
,
228 "ddr-ram-high", s
->ddr_ram
,
229 ddr_low_size
, ddr_high_size
);
230 memory_region_add_subregion(get_system_memory(),
231 XLNX_ZYNQMP_HIGH_RAM_START
,
234 /* RAM must be non-zero */
236 ddr_low_size
= ram_size
;
239 memory_region_init_alias(&s
->ddr_ram_low
, NULL
,
240 "ddr-ram-low", s
->ddr_ram
,
242 memory_region_add_subregion(get_system_memory(), 0, &s
->ddr_ram_low
);
244 /* Create the four OCM banks */
245 for (i
= 0; i
< XLNX_ZYNQMP_NUM_OCM_BANKS
; i
++) {
246 char *ocm_name
= g_strdup_printf("zynqmp.ocm_ram_bank_%d", i
);
248 memory_region_init_ram(&s
->ocm_ram
[i
], NULL
, ocm_name
,
249 XLNX_ZYNQMP_OCM_RAM_SIZE
, &error_fatal
);
250 memory_region_add_subregion(get_system_memory(),
251 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS
+
252 i
* XLNX_ZYNQMP_OCM_RAM_SIZE
,
258 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-irq", GIC_NUM_SPI_INTR
+ 32);
259 qdev_prop_set_uint32(DEVICE(&s
->gic
), "revision", 2);
260 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-cpu", num_apus
);
262 /* Realize APUs before realizing the GIC. KVM requires this. */
263 for (i
= 0; i
< num_apus
; i
++) {
266 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), QEMU_PSCI_CONDUIT_SMC
,
267 "psci-conduit", &error_abort
);
269 name
= object_get_canonical_path_component(OBJECT(&s
->apu_cpu
[i
]));
270 if (strcmp(name
, boot_cpu
)) {
271 /* Secondary CPUs start in PSCI powered-down state */
272 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), true,
273 "start-powered-off", &error_abort
);
275 s
->boot_cpu_ptr
= &s
->apu_cpu
[i
];
279 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]),
280 s
->secure
, "has_el3", NULL
);
281 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]),
282 s
->virt
, "has_el2", NULL
);
283 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), GIC_BASE_ADDR
,
284 "reset-cbar", &error_abort
);
285 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), num_apus
,
286 "core-count", &error_abort
);
287 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), true, "realized",
290 error_propagate(errp
, err
);
295 object_property_set_bool(OBJECT(&s
->gic
), true, "realized", &err
);
297 error_propagate(errp
, err
);
301 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions
) == XLNX_ZYNQMP_GIC_REGIONS
);
302 for (i
= 0; i
< XLNX_ZYNQMP_GIC_REGIONS
; i
++) {
303 SysBusDevice
*gic
= SYS_BUS_DEVICE(&s
->gic
);
304 const XlnxZynqMPGICRegion
*r
= &xlnx_zynqmp_gic_regions
[i
];
305 MemoryRegion
*mr
= sysbus_mmio_get_region(gic
, r
->region_index
);
306 uint32_t addr
= r
->address
;
309 sysbus_mmio_map(gic
, r
->region_index
, addr
);
311 for (j
= 0; j
< XLNX_ZYNQMP_GIC_ALIASES
; j
++) {
312 MemoryRegion
*alias
= &s
->gic_mr
[i
][j
];
314 addr
+= XLNX_ZYNQMP_GIC_REGION_SIZE
;
315 memory_region_init_alias(alias
, OBJECT(s
), "zynqmp-gic-alias", mr
,
316 0, XLNX_ZYNQMP_GIC_REGION_SIZE
);
317 memory_region_add_subregion(system_memory
, addr
, alias
);
321 for (i
= 0; i
< num_apus
; i
++) {
324 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
,
325 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
327 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
328 arm_gic_ppi_index(i
, ARM_PHYS_TIMER_PPI
));
329 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), 0, irq
);
330 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
331 arm_gic_ppi_index(i
, ARM_VIRT_TIMER_PPI
));
332 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), 1, irq
);
336 info_report("The 'has_rpu' property is no longer required, to use the "
337 "RPUs just use -smp 6.");
340 xlnx_zynqmp_create_rpu(s
, boot_cpu
, &err
);
342 error_propagate(errp
, err
);
346 if (!s
->boot_cpu_ptr
) {
347 error_setg(errp
, "ZynqMP Boot cpu %s not found", boot_cpu
);
351 for (i
= 0; i
< GIC_NUM_SPI_INTR
; i
++) {
352 gic_spi
[i
] = qdev_get_gpio_in(DEVICE(&s
->gic
), i
);
355 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
356 NICInfo
*nd
= &nd_table
[i
];
359 qemu_check_nic_model(nd
, TYPE_CADENCE_GEM
);
360 qdev_set_nic_properties(DEVICE(&s
->gem
[i
]), nd
);
362 object_property_set_int(OBJECT(&s
->gem
[i
]), GEM_REVISION
, "revision",
364 object_property_set_int(OBJECT(&s
->gem
[i
]), 2, "num-priority-queues",
366 object_property_set_bool(OBJECT(&s
->gem
[i
]), true, "realized", &err
);
368 error_propagate(errp
, err
);
371 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gem
[i
]), 0, gem_addr
[i
]);
372 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gem
[i
]), 0,
373 gic_spi
[gem_intr
[i
]]);
376 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
377 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hd(i
));
378 object_property_set_bool(OBJECT(&s
->uart
[i
]), true, "realized", &err
);
380 error_propagate(errp
, err
);
383 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, uart_addr
[i
]);
384 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
385 gic_spi
[uart_intr
[i
]]);
388 object_property_set_int(OBJECT(&s
->sata
), SATA_NUM_PORTS
, "num-ports",
390 object_property_set_bool(OBJECT(&s
->sata
), true, "realized", &err
);
392 error_propagate(errp
, err
);
396 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sata
), 0, SATA_ADDR
);
397 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sata
), 0, gic_spi
[SATA_INTR
]);
399 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
400 char *bus_name
= g_strdup_printf("sd-bus%d", i
);
401 SysBusDevice
*sbd
= SYS_BUS_DEVICE(&s
->sdhci
[i
]);
402 Object
*sdhci
= OBJECT(&s
->sdhci
[i
]);
405 * - SD Host Controller Specification Version 3.00
406 * - SDIO Specification Version 3.0
407 * - eMMC Specification Version 4.51
409 object_property_set_uint(sdhci
, 3, "sd-spec-version", &err
);
410 object_property_set_uint(sdhci
, SDHCI_CAPABILITIES
, "capareg", &err
);
411 object_property_set_uint(sdhci
, UHS_I
, "uhs", &err
);
412 object_property_set_bool(sdhci
, true, "realized", &err
);
414 error_propagate(errp
, err
);
417 sysbus_mmio_map(sbd
, 0, sdhci_addr
[i
]);
418 sysbus_connect_irq(sbd
, 0, gic_spi
[sdhci_intr
[i
]]);
420 /* Alias controller SD bus to the SoC itself */
421 object_property_add_alias(OBJECT(s
), bus_name
, sdhci
, "sd-bus",
426 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SPIS
; i
++) {
429 object_property_set_bool(OBJECT(&s
->spi
[i
]), true, "realized", &err
);
431 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0, spi_addr
[i
]);
432 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
433 gic_spi
[spi_intr
[i
]]);
435 /* Alias controller SPI bus to the SoC itself */
436 bus_name
= g_strdup_printf("spi%d", i
);
437 object_property_add_alias(OBJECT(s
), bus_name
,
438 OBJECT(&s
->spi
[i
]), "spi0",
443 object_property_set_bool(OBJECT(&s
->qspi
), true, "realized", &err
);
444 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->qspi
), 0, QSPI_ADDR
);
445 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->qspi
), 1, LQSPI_ADDR
);
446 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->qspi
), 0, gic_spi
[QSPI_IRQ
]);
448 for (i
= 0; i
< XLNX_ZYNQMP_NUM_QSPI_BUS
; i
++) {
452 /* Alias controller SPI bus to the SoC itself */
453 bus_name
= g_strdup_printf("qspi%d", i
);
454 target_bus
= g_strdup_printf("spi%d", i
);
455 object_property_add_alias(OBJECT(s
), bus_name
,
456 OBJECT(&s
->qspi
), target_bus
,
462 object_property_set_bool(OBJECT(&s
->dp
), true, "realized", &err
);
464 error_propagate(errp
, err
);
467 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->dp
), 0, DP_ADDR
);
468 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dp
), 0, gic_spi
[DP_IRQ
]);
470 object_property_set_bool(OBJECT(&s
->dpdma
), true, "realized", &err
);
472 error_propagate(errp
, err
);
475 object_property_set_link(OBJECT(&s
->dp
), OBJECT(&s
->dpdma
), "dpdma",
477 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->dpdma
), 0, DPDMA_ADDR
);
478 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dpdma
), 0, gic_spi
[DPDMA_IRQ
]);
480 object_property_set_bool(OBJECT(&s
->ipi
), true, "realized", &err
);
482 error_propagate(errp
, err
);
485 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ipi
), 0, IPI_ADDR
);
486 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ipi
), 0, gic_spi
[IPI_IRQ
]);
488 object_property_set_bool(OBJECT(&s
->rtc
), true, "realized", &err
);
490 error_propagate(errp
, err
);
493 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->rtc
), 0, RTC_ADDR
);
494 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->rtc
), 0, gic_spi
[RTC_IRQ
]);
497 static Property xlnx_zynqmp_props
[] = {
498 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState
, boot_cpu
),
499 DEFINE_PROP_BOOL("secure", XlnxZynqMPState
, secure
, false),
500 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState
, virt
, false),
501 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState
, has_rpu
, false),
502 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState
, ddr_ram
, TYPE_MEMORY_REGION
,
504 DEFINE_PROP_END_OF_LIST()
507 static void xlnx_zynqmp_class_init(ObjectClass
*oc
, void *data
)
509 DeviceClass
*dc
= DEVICE_CLASS(oc
);
511 dc
->props
= xlnx_zynqmp_props
;
512 dc
->realize
= xlnx_zynqmp_realize
;
513 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
514 dc
->user_creatable
= false;
517 static const TypeInfo xlnx_zynqmp_type_info
= {
518 .name
= TYPE_XLNX_ZYNQMP
,
519 .parent
= TYPE_DEVICE
,
520 .instance_size
= sizeof(XlnxZynqMPState
),
521 .instance_init
= xlnx_zynqmp_init
,
522 .class_init
= xlnx_zynqmp_class_init
,
525 static void xlnx_zynqmp_register_types(void)
527 type_register_static(&xlnx_zynqmp_type_info
);
530 type_init(xlnx_zynqmp_register_types
)