hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu-common.h"
  21 #include "cpu.h"
  22 #include "hw/arm/xlnx-zynqmp.h"
  23 #include "hw/intc/arm_gic_common.h"
  24 #include "exec/address-spaces.h"
  25 #include "sysemu/kvm.h"
  26 #include "kvm_arm.h"
  27
  28 #define GIC_NUM_SPI_INTR 160
  29
  30 #define ARM_PHYS_TIMER_PPI  30
  31 #define ARM_VIRT_TIMER_PPI  27
  32
  33 #define GEM_REVISION        0x40070106
  34
  35 #define GIC_BASE_ADDR       0xf9000000
  36 #define GIC_DIST_ADDR       0xf9010000
  37 #define GIC_CPU_ADDR        0xf9020000
  38
  39 #define SATA_INTR           133
  40 #define SATA_ADDR           0xFD0C0000
  41 #define SATA_NUM_PORTS      2
  42
  43 #define QSPI_ADDR           0xff0f0000
  44 #define LQSPI_ADDR          0xc0000000
  45 #define QSPI_IRQ            15
  46
  47 #define DP_ADDR             0xfd4a0000
  48 #define DP_IRQ              113
  49
  50 #define DPDMA_ADDR          0xfd4c0000
  51 #define DPDMA_IRQ           116
  52
  53 #define IPI_ADDR            0xFF300000
  54 #define IPI_IRQ             64
  55
  56 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  57     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  58 };
  59
  60 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  61     57, 59, 61, 63,
  62 };
  63
  64 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  65     0xFF000000, 0xFF010000,
  66 };
  67
  68 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  69     21, 22,
  70 };
  71
  72 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
  73     0xFF160000, 0xFF170000,
  74 };
  75
  76 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
  77     48, 49,
  78 };
  79
  80 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
  81     0xFF040000, 0xFF050000,
  82 };
  83
  84 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
  85     19, 20,
  86 };
  87
  88 typedef struct XlnxZynqMPGICRegion {
  89     int region_index;
  90     uint32_t address;
  91 } XlnxZynqMPGICRegion;
  92
  93 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
  94     { .region_index = 0, .address = GIC_DIST_ADDR, },
  95     { .region_index = 1, .address = GIC_CPU_ADDR,  },
  96 };
  97
  98 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
  99 {
 100     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
 101 }
 102
 103 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
 104                                    Error **errp)
 105 {
 106     Error *err = NULL;
 107     int i;
 108     int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);
 109
 110     for (i = 0; i < num_rpus; i++) {
 111         char *name;
 112
 113         object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
 114                           "cortex-r5-" TYPE_ARM_CPU);
 115         object_property_add_child(OBJECT(s), "rpu-cpu[*]",
 116                                   OBJECT(&s->rpu_cpu[i]), &error_abort);
 117
 118         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
 119         if (strcmp(name, boot_cpu)) {
 120             /* Secondary CPUs start in PSCI powered-down state */
 121             object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
 122                                      "start-powered-off", &error_abort);
 123         } else {
 124             s->boot_cpu_ptr = &s->rpu_cpu[i];
 125         }
 126         g_free(name);
 127
 128         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
 129                                  &error_abort);
 130         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
 131                                  &err);
 132         if (err) {
 133             error_propagate(errp, err);
 134             return;
 135         }
 136     }
 137 }
 138
 139 static void xlnx_zynqmp_init(Object *obj)
 140 {
 141     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
 142     int i;
 143     int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 144
 145     for (i = 0; i < num_apus; i++) {
 146         object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
 147                           "cortex-a53-" TYPE_ARM_CPU);
 148         object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
 149                                   &error_abort);
 150     }
 151
 152     object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
 153     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
 154
 155     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 156         object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
 157         qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
 158     }
 159
 160     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 161         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
 162         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
 163     }
 164
 165     object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
 166     qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
 167
 168     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 169         object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
 170                           TYPE_SYSBUS_SDHCI);
 171         qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
 172                             sysbus_get_default());
 173     }
 174
 175     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 176         object_initialize(&s->spi[i], sizeof(s->spi[i]),
 177                           TYPE_XILINX_SPIPS);
 178         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
 179     }
 180
 181     object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS);
 182     qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default());
 183
 184     object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
 185     qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
 186
 187     object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
 188     qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
 189
 190     object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI);
 191     qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default());
 192 }
 193
 194 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 195 {
 196     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 197     MemoryRegion *system_memory = get_system_memory();
 198     uint8_t i;
 199     uint64_t ram_size;
 200     int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 201     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
 202     ram_addr_t ddr_low_size, ddr_high_size;
 203     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
 204     Error *err = NULL;
 205
 206     ram_size = memory_region_size(s->ddr_ram);
 207
 208     /* Create the DDR Memory Regions. User friendly checks should happen at
 209      * the board level
 210      */
 211     if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
 212         /* The RAM size is above the maximum available for the low DDR.
 213          * Create the high DDR memory region as well.
 214          */
 215         assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
 216         ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 217         ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 218
 219         memory_region_init_alias(&s->ddr_ram_high, NULL,
 220                                  "ddr-ram-high", s->ddr_ram,
 221                                   ddr_low_size, ddr_high_size);
 222         memory_region_add_subregion(get_system_memory(),
 223                                     XLNX_ZYNQMP_HIGH_RAM_START,
 224                                     &s->ddr_ram_high);
 225     } else {
 226         /* RAM must be non-zero */
 227         assert(ram_size);
 228         ddr_low_size = ram_size;
 229     }
 230
 231     memory_region_init_alias(&s->ddr_ram_low, NULL,
 232                              "ddr-ram-low", s->ddr_ram,
 233                               0, ddr_low_size);
 234     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
 235
 236     /* Create the four OCM banks */
 237     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
 238         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
 239
 240         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
 241                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
 242         memory_region_add_subregion(get_system_memory(),
 243                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
 244                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
 245                                     &s->ocm_ram[i]);
 246
 247         g_free(ocm_name);
 248     }
 249
 250     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 251     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 252     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
 253
 254     /* Realize APUs before realizing the GIC. KVM requires this.  */
 255     for (i = 0; i < num_apus; i++) {
 256         char *name;
 257
 258         object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
 259                                 "psci-conduit", &error_abort);
 260
 261         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 262         if (strcmp(name, boot_cpu)) {
 263             /* Secondary CPUs start in PSCI powered-down state */
 264             object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
 265                                      "start-powered-off", &error_abort);
 266         } else {
 267             s->boot_cpu_ptr = &s->apu_cpu[i];
 268         }
 269         g_free(name);
 270
 271         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 272                                  s->secure, "has_el3", NULL);
 273         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 274                                  s->virt, "has_el2", NULL);
 275         object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
 276                                 "reset-cbar", &error_abort);
 277         object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
 278                                  &err);
 279         if (err) {
 280             error_propagate(errp, err);
 281             return;
 282         }
 283     }
 284
 285     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 286     if (err) {
 287         error_propagate(errp, err);
 288         return;
 289     }
 290
 291     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 292     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 293         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 294         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 295         MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
 296         uint32_t addr = r->address;
 297         int j;
 298
 299         sysbus_mmio_map(gic, r->region_index, addr);
 300
 301         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 302             MemoryRegion *alias = &s->gic_mr[i][j];
 303
 304             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 305             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 306                                      0, XLNX_ZYNQMP_GIC_REGION_SIZE);
 307             memory_region_add_subregion(system_memory, addr, alias);
 308         }
 309     }
 310
 311     for (i = 0; i < num_apus; i++) {
 312         qemu_irq irq;
 313
 314         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 315                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 316                                             ARM_CPU_IRQ));
 317         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 318                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 319         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
 320         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 321                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 322         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
 323     }
 324
 325     if (s->has_rpu) {
 326         info_report("The 'has_rpu' property is no longer required, to use the "
 327                     "RPUs just use -smp 6.");
 328     }
 329
 330     xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
 331     if (err) {
 332         error_propagate(errp, err);
 333         return;
 334     }
 335
 336     if (!s->boot_cpu_ptr) {
 337         error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
 338         return;
 339     }
 340
 341     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 342         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 343     }
 344
 345     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 346         NICInfo *nd = &nd_table[i];
 347
 348         if (nd->used) {
 349             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 350             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 351         }
 352         object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
 353                                 &error_abort);
 354         object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
 355                                 &error_abort);
 356         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
 357         if (err) {
 358             error_propagate(errp, err);
 359             return;
 360         }
 361         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 362         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 363                            gic_spi[gem_intr[i]]);
 364     }
 365
 366     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 367         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
 368         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 369         if (err) {
 370             error_propagate(errp, err);
 371             return;
 372         }
 373         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 374         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 375                            gic_spi[uart_intr[i]]);
 376     }
 377
 378     object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
 379                             &error_abort);
 380     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
 381     if (err) {
 382         error_propagate(errp, err);
 383         return;
 384     }
 385
 386     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
 387     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
 388
 389     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 390         char *bus_name;
 391
 392         object_property_set_bool(OBJECT(&s->sdhci[i]), true,
 393                                  "realized", &err);
 394         if (err) {
 395             error_propagate(errp, err);
 396             return;
 397         }
 398         sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
 399                         sdhci_addr[i]);
 400         sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
 401                            gic_spi[sdhci_intr[i]]);
 402         /* Alias controller SD bus to the SoC itself */
 403         bus_name = g_strdup_printf("sd-bus%d", i);
 404         object_property_add_alias(OBJECT(s), bus_name,
 405                                   OBJECT(&s->sdhci[i]), "sd-bus",
 406                                   &error_abort);
 407         g_free(bus_name);
 408     }
 409
 410     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 411         gchar *bus_name;
 412
 413         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 414
 415         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 416         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 417                            gic_spi[spi_intr[i]]);
 418
 419         /* Alias controller SPI bus to the SoC itself */
 420         bus_name = g_strdup_printf("spi%d", i);
 421         object_property_add_alias(OBJECT(s), bus_name,
 422                                   OBJECT(&s->spi[i]), "spi0",
 423                                   &error_abort);
 424         g_free(bus_name);
 425     }
 426
 427     object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
 428     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
 429     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
 430     sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
 431
 432     for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
 433         gchar *bus_name;
 434         gchar *target_bus;
 435
 436         /* Alias controller SPI bus to the SoC itself */
 437         bus_name = g_strdup_printf("qspi%d", i);
 438         target_bus = g_strdup_printf("spi%d", i);
 439         object_property_add_alias(OBJECT(s), bus_name,
 440                                   OBJECT(&s->qspi), target_bus,
 441                                   &error_abort);
 442         g_free(bus_name);
 443         g_free(target_bus);
 444     }
 445
 446     object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
 447     if (err) {
 448         error_propagate(errp, err);
 449         return;
 450     }
 451     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
 452     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
 453
 454     object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
 455     if (err) {
 456         error_propagate(errp, err);
 457         return;
 458     }
 459     object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
 460                              &error_abort);
 461     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
 462     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
 463
 464     object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err);
 465     if (err) {
 466         error_propagate(errp, err);
 467         return;
 468     }
 469     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
 470     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
 471 }
 472
 473 static Property xlnx_zynqmp_props[] = {
 474     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 475     DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
 476     DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
 477     DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
 478     DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
 479                      MemoryRegion *),
 480     DEFINE_PROP_END_OF_LIST()
 481 };
 482
 483 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 484 {
 485     DeviceClass *dc = DEVICE_CLASS(oc);
 486
 487     dc->props = xlnx_zynqmp_props;
 488     dc->realize = xlnx_zynqmp_realize;
 489     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 490     dc->user_creatable = false;
 491 }
 492
 493 static const TypeInfo xlnx_zynqmp_type_info = {
 494     .name = TYPE_XLNX_ZYNQMP,
 495     .parent = TYPE_DEVICE,
 496     .instance_size = sizeof(XlnxZynqMPState),
 497     .instance_init = xlnx_zynqmp_init,
 498     .class_init = xlnx_zynqmp_class_init,
 499 };
 500
 501 static void xlnx_zynqmp_register_types(void)
 502 {
 503     type_register_static(&xlnx_zynqmp_type_info);
 504 }
 505
 506 type_init(xlnx_zynqmp_register_types)