2 * Xilinx Zynq MPSoC emulation
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu/module.h"
21 #include "hw/arm/xlnx-zynqmp.h"
22 #include "hw/intc/arm_gic_common.h"
23 #include "hw/misc/unimp.h"
24 #include "hw/boards.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/sysemu.h"
29 #define GIC_NUM_SPI_INTR 160
31 #define ARM_PHYS_TIMER_PPI 30
32 #define ARM_VIRT_TIMER_PPI 27
33 #define ARM_HYP_TIMER_PPI 26
34 #define ARM_SEC_TIMER_PPI 29
35 #define GIC_MAINTENANCE_PPI 25
37 #define GEM_REVISION 0x40070106
39 #define GIC_BASE_ADDR 0xf9000000
40 #define GIC_DIST_ADDR 0xf9010000
41 #define GIC_CPU_ADDR 0xf9020000
42 #define GIC_VIFACE_ADDR 0xf9040000
43 #define GIC_VCPU_ADDR 0xf9060000
46 #define SATA_ADDR 0xFD0C0000
47 #define SATA_NUM_PORTS 2
49 #define QSPI_ADDR 0xff0f0000
50 #define LQSPI_ADDR 0xc0000000
52 #define QSPI_DMA_ADDR 0xff0f0800
53 #define NUM_QSPI_IRQ_LINES 2
55 #define CRF_ADDR 0xfd1a0000
58 /* Serializer/Deserializer. */
59 #define SERDES_ADDR 0xfd400000
60 #define SERDES_SIZE 0x20000
62 #define DP_ADDR 0xfd4a0000
65 #define DPDMA_ADDR 0xfd4c0000
68 #define APU_ADDR 0xfd5c0000
71 #define IPI_ADDR 0xFF300000
74 #define RTC_ADDR 0xffa60000
77 #define BBRAM_ADDR 0xffcd0000
80 #define EFUSE_ADDR 0xffcc0000
83 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
85 static const uint64_t gem_addr
[XLNX_ZYNQMP_NUM_GEMS
] = {
86 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
89 static const int gem_intr
[XLNX_ZYNQMP_NUM_GEMS
] = {
93 static const uint64_t uart_addr
[XLNX_ZYNQMP_NUM_UARTS
] = {
94 0xFF000000, 0xFF010000,
97 static const int uart_intr
[XLNX_ZYNQMP_NUM_UARTS
] = {
101 static const uint64_t can_addr
[XLNX_ZYNQMP_NUM_CAN
] = {
102 0xFF060000, 0xFF070000,
105 static const int can_intr
[XLNX_ZYNQMP_NUM_CAN
] = {
109 static const uint64_t sdhci_addr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
110 0xFF160000, 0xFF170000,
113 static const int sdhci_intr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
117 static const uint64_t spi_addr
[XLNX_ZYNQMP_NUM_SPIS
] = {
118 0xFF040000, 0xFF050000,
121 static const int spi_intr
[XLNX_ZYNQMP_NUM_SPIS
] = {
125 static const uint64_t gdma_ch_addr
[XLNX_ZYNQMP_NUM_GDMA_CH
] = {
126 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
127 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
130 static const int gdma_ch_intr
[XLNX_ZYNQMP_NUM_GDMA_CH
] = {
131 124, 125, 126, 127, 128, 129, 130, 131
134 static const uint64_t adma_ch_addr
[XLNX_ZYNQMP_NUM_ADMA_CH
] = {
135 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
136 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
139 static const int adma_ch_intr
[XLNX_ZYNQMP_NUM_ADMA_CH
] = {
140 77, 78, 79, 80, 81, 82, 83, 84
143 typedef struct XlnxZynqMPGICRegion
{
148 } XlnxZynqMPGICRegion
;
150 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions
[] = {
154 .address
= GIC_DIST_ADDR
,
162 .address
= GIC_CPU_ADDR
,
168 .address
= GIC_CPU_ADDR
+ 0x10000,
173 /* Virtual interface */
176 .address
= GIC_VIFACE_ADDR
,
181 /* Virtual CPU interface */
184 .address
= GIC_VCPU_ADDR
,
190 .address
= GIC_VCPU_ADDR
+ 0x10000,
196 static inline int arm_gic_ppi_index(int cpu_nr
, int ppi_index
)
198 return GIC_NUM_SPI_INTR
+ cpu_nr
* GIC_INTERNAL
+ ppi_index
;
201 static void xlnx_zynqmp_create_rpu(MachineState
*ms
, XlnxZynqMPState
*s
,
202 const char *boot_cpu
, Error
**errp
)
205 int num_rpus
= MIN(ms
->smp
.cpus
- XLNX_ZYNQMP_NUM_APU_CPUS
,
206 XLNX_ZYNQMP_NUM_RPU_CPUS
);
209 /* Don't create rpu-cluster object if there's nothing to put in it */
213 object_initialize_child(OBJECT(s
), "rpu-cluster", &s
->rpu_cluster
,
215 qdev_prop_set_uint32(DEVICE(&s
->rpu_cluster
), "cluster-id", 1);
217 for (i
= 0; i
< num_rpus
; i
++) {
220 object_initialize_child(OBJECT(&s
->rpu_cluster
), "rpu-cpu[*]",
222 ARM_CPU_TYPE_NAME("cortex-r5f"));
224 name
= object_get_canonical_path_component(OBJECT(&s
->rpu_cpu
[i
]));
225 if (strcmp(name
, boot_cpu
)) {
227 * Secondary CPUs start in powered-down state.
229 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]),
230 "start-powered-off", true, &error_abort
);
232 s
->boot_cpu_ptr
= &s
->rpu_cpu
[i
];
235 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), "reset-hivecs", true,
237 if (!qdev_realize(DEVICE(&s
->rpu_cpu
[i
]), NULL
, errp
)) {
242 qdev_realize(DEVICE(&s
->rpu_cluster
), NULL
, &error_fatal
);
245 static void xlnx_zynqmp_create_bbram(XlnxZynqMPState
*s
, qemu_irq
*gic
)
249 object_initialize_child_with_props(OBJECT(s
), "bbram", &s
->bbram
,
250 sizeof(s
->bbram
), TYPE_XLNX_BBRAM
,
254 sbd
= SYS_BUS_DEVICE(&s
->bbram
);
256 sysbus_realize(sbd
, &error_fatal
);
257 sysbus_mmio_map(sbd
, 0, BBRAM_ADDR
);
258 sysbus_connect_irq(sbd
, 0, gic
[BBRAM_IRQ
]);
261 static void xlnx_zynqmp_create_efuse(XlnxZynqMPState
*s
, qemu_irq
*gic
)
263 Object
*bits
= OBJECT(&s
->efuse
);
264 Object
*ctrl
= OBJECT(&s
->efuse_ctrl
);
267 object_initialize_child(OBJECT(s
), "efuse-ctrl", &s
->efuse_ctrl
,
268 TYPE_XLNX_ZYNQMP_EFUSE
);
270 object_initialize_child_with_props(ctrl
, "xlnx-efuse@0", bits
,
272 TYPE_XLNX_EFUSE
, &error_abort
,
274 "efuse-size", "2048",
277 qdev_realize(DEVICE(bits
), NULL
, &error_abort
);
278 object_property_set_link(ctrl
, "efuse", bits
, &error_abort
);
280 sbd
= SYS_BUS_DEVICE(ctrl
);
281 sysbus_realize(sbd
, &error_abort
);
282 sysbus_mmio_map(sbd
, 0, EFUSE_ADDR
);
283 sysbus_connect_irq(sbd
, 0, gic
[EFUSE_IRQ
]);
286 static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState
*s
, qemu_irq
*gic
)
291 object_initialize_child(OBJECT(s
), "apu-ctrl", &s
->apu_ctrl
,
292 TYPE_XLNX_ZYNQMP_APU_CTRL
);
293 sbd
= SYS_BUS_DEVICE(&s
->apu_ctrl
);
295 for (i
= 0; i
< XLNX_ZYNQMP_NUM_APU_CPUS
; i
++) {
296 g_autofree gchar
*name
= g_strdup_printf("cpu%d", i
);
298 object_property_set_link(OBJECT(&s
->apu_ctrl
), name
,
299 OBJECT(&s
->apu_cpu
[i
]), &error_abort
);
302 sysbus_realize(sbd
, &error_fatal
);
303 sysbus_mmio_map(sbd
, 0, APU_ADDR
);
304 sysbus_connect_irq(sbd
, 0, gic
[APU_IRQ
]);
307 static void xlnx_zynqmp_create_crf(XlnxZynqMPState
*s
, qemu_irq
*gic
)
311 object_initialize_child(OBJECT(s
), "crf", &s
->crf
, TYPE_XLNX_ZYNQMP_CRF
);
312 sbd
= SYS_BUS_DEVICE(&s
->crf
);
314 sysbus_realize(sbd
, &error_fatal
);
315 sysbus_mmio_map(sbd
, 0, CRF_ADDR
);
316 sysbus_connect_irq(sbd
, 0, gic
[CRF_IRQ
]);
319 static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState
*s
)
321 static const struct UnimpInfo
{
325 } unimp_areas
[ARRAY_SIZE(s
->mr_unimp
)] = {
326 { .name
= "serdes", SERDES_ADDR
, SERDES_SIZE
},
330 for (nr
= 0; nr
< ARRAY_SIZE(unimp_areas
); nr
++) {
331 const struct UnimpInfo
*info
= &unimp_areas
[nr
];
332 DeviceState
*dev
= qdev_new(TYPE_UNIMPLEMENTED_DEVICE
);
333 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
335 assert(info
->name
&& info
->base
&& info
->size
> 0);
336 qdev_prop_set_string(dev
, "name", info
->name
);
337 qdev_prop_set_uint64(dev
, "size", info
->size
);
338 object_property_add_child(OBJECT(s
), info
->name
, OBJECT(dev
));
340 sysbus_realize_and_unref(sbd
, &error_fatal
);
341 sysbus_mmio_map(sbd
, 0, info
->base
);
345 static void xlnx_zynqmp_init(Object
*obj
)
347 MachineState
*ms
= MACHINE(qdev_get_machine());
348 XlnxZynqMPState
*s
= XLNX_ZYNQMP(obj
);
350 int num_apus
= MIN(ms
->smp
.cpus
, XLNX_ZYNQMP_NUM_APU_CPUS
);
352 object_initialize_child(obj
, "apu-cluster", &s
->apu_cluster
,
354 qdev_prop_set_uint32(DEVICE(&s
->apu_cluster
), "cluster-id", 0);
356 for (i
= 0; i
< num_apus
; i
++) {
357 object_initialize_child(OBJECT(&s
->apu_cluster
), "apu-cpu[*]",
359 ARM_CPU_TYPE_NAME("cortex-a53"));
362 object_initialize_child(obj
, "gic", &s
->gic
, gic_class_name());
364 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
365 object_initialize_child(obj
, "gem[*]", &s
->gem
[i
], TYPE_CADENCE_GEM
);
368 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
369 object_initialize_child(obj
, "uart[*]", &s
->uart
[i
],
373 for (i
= 0; i
< XLNX_ZYNQMP_NUM_CAN
; i
++) {
374 object_initialize_child(obj
, "can[*]", &s
->can
[i
],
375 TYPE_XLNX_ZYNQMP_CAN
);
378 object_initialize_child(obj
, "sata", &s
->sata
, TYPE_SYSBUS_AHCI
);
380 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
381 object_initialize_child(obj
, "sdhci[*]", &s
->sdhci
[i
],
385 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SPIS
; i
++) {
386 object_initialize_child(obj
, "spi[*]", &s
->spi
[i
], TYPE_XILINX_SPIPS
);
389 object_initialize_child(obj
, "qspi", &s
->qspi
, TYPE_XLNX_ZYNQMP_QSPIPS
);
391 object_initialize_child(obj
, "xxxdp", &s
->dp
, TYPE_XLNX_DP
);
393 object_initialize_child(obj
, "dp-dma", &s
->dpdma
, TYPE_XLNX_DPDMA
);
395 object_initialize_child(obj
, "ipi", &s
->ipi
, TYPE_XLNX_ZYNQMP_IPI
);
397 object_initialize_child(obj
, "rtc", &s
->rtc
, TYPE_XLNX_ZYNQMP_RTC
);
399 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GDMA_CH
; i
++) {
400 object_initialize_child(obj
, "gdma[*]", &s
->gdma
[i
], TYPE_XLNX_ZDMA
);
403 for (i
= 0; i
< XLNX_ZYNQMP_NUM_ADMA_CH
; i
++) {
404 object_initialize_child(obj
, "adma[*]", &s
->adma
[i
], TYPE_XLNX_ZDMA
);
407 object_initialize_child(obj
, "qspi-dma", &s
->qspi_dma
, TYPE_XLNX_CSU_DMA
);
408 object_initialize_child(obj
, "qspi-irq-orgate",
409 &s
->qspi_irq_orgate
, TYPE_OR_IRQ
);
412 static void xlnx_zynqmp_realize(DeviceState
*dev
, Error
**errp
)
414 MachineState
*ms
= MACHINE(qdev_get_machine());
415 XlnxZynqMPState
*s
= XLNX_ZYNQMP(dev
);
416 MemoryRegion
*system_memory
= get_system_memory();
419 int num_apus
= MIN(ms
->smp
.cpus
, XLNX_ZYNQMP_NUM_APU_CPUS
);
420 const char *boot_cpu
= s
->boot_cpu
? s
->boot_cpu
: "apu-cpu[0]";
421 ram_addr_t ddr_low_size
, ddr_high_size
;
422 qemu_irq gic_spi
[GIC_NUM_SPI_INTR
];
425 ram_size
= memory_region_size(s
->ddr_ram
);
428 * Create the DDR Memory Regions. User friendly checks should happen at
431 if (ram_size
> XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
) {
433 * The RAM size is above the maximum available for the low DDR.
434 * Create the high DDR memory region as well.
436 assert(ram_size
<= XLNX_ZYNQMP_MAX_RAM_SIZE
);
437 ddr_low_size
= XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
438 ddr_high_size
= ram_size
- XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
440 memory_region_init_alias(&s
->ddr_ram_high
, OBJECT(dev
),
441 "ddr-ram-high", s
->ddr_ram
, ddr_low_size
,
443 memory_region_add_subregion(get_system_memory(),
444 XLNX_ZYNQMP_HIGH_RAM_START
,
447 /* RAM must be non-zero */
449 ddr_low_size
= ram_size
;
452 memory_region_init_alias(&s
->ddr_ram_low
, OBJECT(dev
), "ddr-ram-low",
453 s
->ddr_ram
, 0, ddr_low_size
);
454 memory_region_add_subregion(get_system_memory(), 0, &s
->ddr_ram_low
);
456 /* Create the four OCM banks */
457 for (i
= 0; i
< XLNX_ZYNQMP_NUM_OCM_BANKS
; i
++) {
458 char *ocm_name
= g_strdup_printf("zynqmp.ocm_ram_bank_%d", i
);
460 memory_region_init_ram(&s
->ocm_ram
[i
], NULL
, ocm_name
,
461 XLNX_ZYNQMP_OCM_RAM_SIZE
, &error_fatal
);
462 memory_region_add_subregion(get_system_memory(),
463 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS
+
464 i
* XLNX_ZYNQMP_OCM_RAM_SIZE
,
470 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-irq", GIC_NUM_SPI_INTR
+ 32);
471 qdev_prop_set_uint32(DEVICE(&s
->gic
), "revision", 2);
472 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-cpu", num_apus
);
473 qdev_prop_set_bit(DEVICE(&s
->gic
), "has-security-extensions", s
->secure
);
474 qdev_prop_set_bit(DEVICE(&s
->gic
),
475 "has-virtualization-extensions", s
->virt
);
477 qdev_realize(DEVICE(&s
->apu_cluster
), NULL
, &error_fatal
);
479 /* Realize APUs before realizing the GIC. KVM requires this. */
480 for (i
= 0; i
< num_apus
; i
++) {
483 name
= object_get_canonical_path_component(OBJECT(&s
->apu_cpu
[i
]));
484 if (strcmp(name
, boot_cpu
)) {
486 * Secondary CPUs start in powered-down state.
488 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]),
489 "start-powered-off", true, &error_abort
);
491 s
->boot_cpu_ptr
= &s
->apu_cpu
[i
];
494 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), "has_el3", s
->secure
,
496 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), "has_el2", s
->virt
,
498 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), "reset-cbar",
499 GIC_BASE_ADDR
, &error_abort
);
500 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), "core-count",
501 num_apus
, &error_abort
);
502 if (!qdev_realize(DEVICE(&s
->apu_cpu
[i
]), NULL
, errp
)) {
507 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gic
), errp
)) {
511 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions
) == XLNX_ZYNQMP_GIC_REGIONS
);
512 for (i
= 0; i
< XLNX_ZYNQMP_GIC_REGIONS
; i
++) {
513 SysBusDevice
*gic
= SYS_BUS_DEVICE(&s
->gic
);
514 const XlnxZynqMPGICRegion
*r
= &xlnx_zynqmp_gic_regions
[i
];
516 uint32_t addr
= r
->address
;
519 if (r
->virt
&& !s
->virt
) {
523 mr
= sysbus_mmio_get_region(gic
, r
->region_index
);
524 for (j
= 0; j
< XLNX_ZYNQMP_GIC_ALIASES
; j
++) {
525 MemoryRegion
*alias
= &s
->gic_mr
[i
][j
];
527 memory_region_init_alias(alias
, OBJECT(s
), "zynqmp-gic-alias", mr
,
528 r
->offset
, XLNX_ZYNQMP_GIC_REGION_SIZE
);
529 memory_region_add_subregion(system_memory
, addr
, alias
);
531 addr
+= XLNX_ZYNQMP_GIC_REGION_SIZE
;
535 for (i
= 0; i
< num_apus
; i
++) {
538 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
,
539 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
541 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
+ num_apus
,
542 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
544 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
+ num_apus
* 2,
545 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
547 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
+ num_apus
* 3,
548 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
550 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
551 arm_gic_ppi_index(i
, ARM_PHYS_TIMER_PPI
));
552 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), GTIMER_PHYS
, irq
);
553 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
554 arm_gic_ppi_index(i
, ARM_VIRT_TIMER_PPI
));
555 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), GTIMER_VIRT
, irq
);
556 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
557 arm_gic_ppi_index(i
, ARM_HYP_TIMER_PPI
));
558 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), GTIMER_HYP
, irq
);
559 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
560 arm_gic_ppi_index(i
, ARM_SEC_TIMER_PPI
));
561 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), GTIMER_SEC
, irq
);
564 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
565 arm_gic_ppi_index(i
, GIC_MAINTENANCE_PPI
));
566 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
+ num_apus
* 4, irq
);
570 xlnx_zynqmp_create_rpu(ms
, s
, boot_cpu
, &err
);
572 error_propagate(errp
, err
);
576 if (!s
->boot_cpu_ptr
) {
577 error_setg(errp
, "ZynqMP Boot cpu %s not found", boot_cpu
);
581 for (i
= 0; i
< GIC_NUM_SPI_INTR
; i
++) {
582 gic_spi
[i
] = qdev_get_gpio_in(DEVICE(&s
->gic
), i
);
585 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
586 NICInfo
*nd
= &nd_table
[i
];
588 /* FIXME use qdev NIC properties instead of nd_table[] */
590 qemu_check_nic_model(nd
, TYPE_CADENCE_GEM
);
591 qdev_set_nic_properties(DEVICE(&s
->gem
[i
]), nd
);
593 object_property_set_int(OBJECT(&s
->gem
[i
]), "revision", GEM_REVISION
,
595 object_property_set_int(OBJECT(&s
->gem
[i
]), "phy-addr", 23,
597 object_property_set_int(OBJECT(&s
->gem
[i
]), "num-priority-queues", 2,
599 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gem
[i
]), errp
)) {
602 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gem
[i
]), 0, gem_addr
[i
]);
603 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gem
[i
]), 0,
604 gic_spi
[gem_intr
[i
]]);
607 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
608 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hd(i
));
609 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->uart
[i
]), errp
)) {
612 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, uart_addr
[i
]);
613 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
614 gic_spi
[uart_intr
[i
]]);
617 for (i
= 0; i
< XLNX_ZYNQMP_NUM_CAN
; i
++) {
618 object_property_set_int(OBJECT(&s
->can
[i
]), "ext_clk_freq",
619 XLNX_ZYNQMP_CAN_REF_CLK
, &error_abort
);
621 object_property_set_link(OBJECT(&s
->can
[i
]), "canbus",
622 OBJECT(s
->canbus
[i
]), &error_fatal
);
624 sysbus_realize(SYS_BUS_DEVICE(&s
->can
[i
]), &err
);
626 error_propagate(errp
, err
);
629 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->can
[i
]), 0, can_addr
[i
]);
630 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->can
[i
]), 0,
631 gic_spi
[can_intr
[i
]]);
634 object_property_set_int(OBJECT(&s
->sata
), "num-ports", SATA_NUM_PORTS
,
636 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sata
), errp
)) {
640 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sata
), 0, SATA_ADDR
);
641 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sata
), 0, gic_spi
[SATA_INTR
]);
643 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
645 SysBusDevice
*sbd
= SYS_BUS_DEVICE(&s
->sdhci
[i
]);
646 Object
*sdhci
= OBJECT(&s
->sdhci
[i
]);
650 * - SD Host Controller Specification Version 3.00
651 * - SDIO Specification Version 3.0
652 * - eMMC Specification Version 4.51
654 if (!object_property_set_uint(sdhci
, "sd-spec-version", 3, errp
)) {
657 if (!object_property_set_uint(sdhci
, "capareg", SDHCI_CAPABILITIES
,
661 if (!object_property_set_uint(sdhci
, "uhs", UHS_I
, errp
)) {
664 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci
), errp
)) {
667 sysbus_mmio_map(sbd
, 0, sdhci_addr
[i
]);
668 sysbus_connect_irq(sbd
, 0, gic_spi
[sdhci_intr
[i
]]);
670 /* Alias controller SD bus to the SoC itself */
671 bus_name
= g_strdup_printf("sd-bus%d", i
);
672 object_property_add_alias(OBJECT(s
), bus_name
, sdhci
, "sd-bus");
676 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SPIS
; i
++) {
679 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->spi
[i
]), errp
)) {
683 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0, spi_addr
[i
]);
684 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
685 gic_spi
[spi_intr
[i
]]);
687 /* Alias controller SPI bus to the SoC itself */
688 bus_name
= g_strdup_printf("spi%d", i
);
689 object_property_add_alias(OBJECT(s
), bus_name
,
690 OBJECT(&s
->spi
[i
]), "spi0");
694 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->dp
), errp
)) {
697 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->dp
), 0, DP_ADDR
);
698 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dp
), 0, gic_spi
[DP_IRQ
]);
700 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->dpdma
), errp
)) {
703 object_property_set_link(OBJECT(&s
->dp
), "dpdma", OBJECT(&s
->dpdma
),
705 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->dpdma
), 0, DPDMA_ADDR
);
706 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dpdma
), 0, gic_spi
[DPDMA_IRQ
]);
708 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ipi
), errp
)) {
711 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ipi
), 0, IPI_ADDR
);
712 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ipi
), 0, gic_spi
[IPI_IRQ
]);
714 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->rtc
), errp
)) {
717 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->rtc
), 0, RTC_ADDR
);
718 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->rtc
), 0, gic_spi
[RTC_IRQ
]);
720 xlnx_zynqmp_create_bbram(s
, gic_spi
);
721 xlnx_zynqmp_create_efuse(s
, gic_spi
);
722 xlnx_zynqmp_create_apu_ctrl(s
, gic_spi
);
723 xlnx_zynqmp_create_crf(s
, gic_spi
);
724 xlnx_zynqmp_create_unimp_mmio(s
);
726 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GDMA_CH
; i
++) {
727 if (!object_property_set_uint(OBJECT(&s
->gdma
[i
]), "bus-width", 128,
731 if (!object_property_set_link(OBJECT(&s
->gdma
[i
]), "dma",
732 OBJECT(system_memory
), errp
)) {
735 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gdma
[i
]), errp
)) {
739 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gdma
[i
]), 0, gdma_ch_addr
[i
]);
740 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gdma
[i
]), 0,
741 gic_spi
[gdma_ch_intr
[i
]]);
744 for (i
= 0; i
< XLNX_ZYNQMP_NUM_ADMA_CH
; i
++) {
745 if (!object_property_set_link(OBJECT(&s
->adma
[i
]), "dma",
746 OBJECT(system_memory
), errp
)) {
749 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->adma
[i
]), errp
)) {
753 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->adma
[i
]), 0, adma_ch_addr
[i
]);
754 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->adma
[i
]), 0,
755 gic_spi
[adma_ch_intr
[i
]]);
758 object_property_set_int(OBJECT(&s
->qspi_irq_orgate
),
759 "num-lines", NUM_QSPI_IRQ_LINES
, &error_fatal
);
760 qdev_realize(DEVICE(&s
->qspi_irq_orgate
), NULL
, &error_fatal
);
761 qdev_connect_gpio_out(DEVICE(&s
->qspi_irq_orgate
), 0, gic_spi
[QSPI_IRQ
]);
763 if (!object_property_set_link(OBJECT(&s
->qspi_dma
), "dma",
764 OBJECT(system_memory
), errp
)) {
767 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->qspi_dma
), errp
)) {
771 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->qspi_dma
), 0, QSPI_DMA_ADDR
);
772 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->qspi_dma
), 0,
773 qdev_get_gpio_in(DEVICE(&s
->qspi_irq_orgate
), 0));
775 if (!object_property_set_link(OBJECT(&s
->qspi
), "stream-connected-dma",
776 OBJECT(&s
->qspi_dma
), errp
)) {
779 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->qspi
), errp
)) {
782 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->qspi
), 0, QSPI_ADDR
);
783 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->qspi
), 1, LQSPI_ADDR
);
784 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->qspi
), 0,
785 qdev_get_gpio_in(DEVICE(&s
->qspi_irq_orgate
), 1));
787 for (i
= 0; i
< XLNX_ZYNQMP_NUM_QSPI_BUS
; i
++) {
788 g_autofree gchar
*bus_name
= g_strdup_printf("qspi%d", i
);
789 g_autofree gchar
*target_bus
= g_strdup_printf("spi%d", i
);
791 /* Alias controller SPI bus to the SoC itself */
792 object_property_add_alias(OBJECT(s
), bus_name
,
793 OBJECT(&s
->qspi
), target_bus
);
797 static Property xlnx_zynqmp_props
[] = {
798 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState
, boot_cpu
),
799 DEFINE_PROP_BOOL("secure", XlnxZynqMPState
, secure
, false),
800 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState
, virt
, false),
801 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState
, ddr_ram
, TYPE_MEMORY_REGION
,
803 DEFINE_PROP_LINK("canbus0", XlnxZynqMPState
, canbus
[0], TYPE_CAN_BUS
,
805 DEFINE_PROP_LINK("canbus1", XlnxZynqMPState
, canbus
[1], TYPE_CAN_BUS
,
807 DEFINE_PROP_END_OF_LIST()
810 static void xlnx_zynqmp_class_init(ObjectClass
*oc
, void *data
)
812 DeviceClass
*dc
= DEVICE_CLASS(oc
);
814 device_class_set_props(dc
, xlnx_zynqmp_props
);
815 dc
->realize
= xlnx_zynqmp_realize
;
816 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
817 dc
->user_creatable
= false;
820 static const TypeInfo xlnx_zynqmp_type_info
= {
821 .name
= TYPE_XLNX_ZYNQMP
,
822 .parent
= TYPE_DEVICE
,
823 .instance_size
= sizeof(XlnxZynqMPState
),
824 .instance_init
= xlnx_zynqmp_init
,
825 .class_init
= xlnx_zynqmp_class_init
,
828 static void xlnx_zynqmp_register_types(void)
830 type_register_static(&xlnx_zynqmp_type_info
);
833 type_init(xlnx_zynqmp_register_types
)