hw/arm_gic.c

   1 /*
   2  * ARM Generic/Distributed Interrupt Controller
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 /* This file contains implementation code for the RealView EB interrupt
  11    controller, MPCore distributed interrupt controller and ARMv7-M
  12    Nested Vectored Interrupt Controller.  */
  13
  14 //#define DEBUG_GIC
  15
  16 #ifdef DEBUG_GIC
  17 #define DPRINTF(fmt, ...) \
  18 do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
  19 #else
  20 #define DPRINTF(fmt, ...) do {} while(0)
  21 #endif
  22
  23 #ifdef NVIC
  24 static const uint8_t gic_id[] =
  25 { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
  26 /* The NVIC has 16 internal vectors.  However these are not exposed
  27    through the normal GIC interface.  */
  28 #define GIC_BASE_IRQ    32
  29 #else
  30 static const uint8_t gic_id[] =
  31 { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  32 #define GIC_BASE_IRQ    0
  33 #endif
  34
  35 #define FROM_SYSBUSGIC(type, dev) \
  36     DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev))
  37
  38 typedef struct gic_irq_state
  39 {
  40     /* The enable bits are only banked for per-cpu interrupts.  */
  41     unsigned enabled:NCPU;
  42     unsigned pending:NCPU;
  43     unsigned active:NCPU;
  44     unsigned level:NCPU;
  45     unsigned model:1; /* 0 = N:N, 1 = 1:N */
  46     unsigned trigger:1; /* nonzero = edge triggered.  */
  47 } gic_irq_state;
  48
  49 #define ALL_CPU_MASK ((1 << NCPU) - 1)
  50 #if NCPU > 1
  51 #define NUM_CPU(s) ((s)->num_cpu)
  52 #else
  53 #define NUM_CPU(s) 1
  54 #endif
  55
  56 #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
  57 #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
  58 #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
  59 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
  60 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
  61 #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
  62 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
  63 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
  64 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
  65 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
  66 #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
  67 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
  68 #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
  69 #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
  70 #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
  71 #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
  72 #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
  73 #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
  74 #define GIC_GET_PRIORITY(irq, cpu) \
  75   (((irq) < 32) ? s->priority1[irq][cpu] : s->priority2[(irq) - 32])
  76 #ifdef NVIC
  77 #define GIC_TARGET(irq) 1
  78 #else
  79 #define GIC_TARGET(irq) s->irq_target[irq]
  80 #endif
  81
  82 typedef struct gic_state
  83 {
  84     SysBusDevice busdev;
  85     qemu_irq parent_irq[NCPU];
  86     int enabled;
  87     int cpu_enabled[NCPU];
  88
  89     gic_irq_state irq_state[GIC_NIRQ];
  90 #ifndef NVIC
  91     int irq_target[GIC_NIRQ];
  92 #endif
  93     int priority1[32][NCPU];
  94     int priority2[GIC_NIRQ - 32];
  95     int last_active[GIC_NIRQ][NCPU];
  96
  97     int priority_mask[NCPU];
  98     int running_irq[NCPU];
  99     int running_priority[NCPU];
 100     int current_pending[NCPU];
 101
 102 #if NCPU > 1
 103     int num_cpu;
 104 #endif
 105
 106     MemoryRegion iomem; /* Distributor */
 107 #ifndef NVIC
 108     /* This is just so we can have an opaque pointer which identifies
 109      * both this GIC and which CPU interface we should be accessing.
 110      */
 111     struct gic_state *backref[NCPU];
 112     MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */
 113 #endif
 114 } gic_state;
 115
 116 /* TODO: Many places that call this routine could be optimized.  */
 117 /* Update interrupt status after enabled or pending bits have been changed.  */
 118 static void gic_update(gic_state *s)
 119 {
 120     int best_irq;
 121     int best_prio;
 122     int irq;
 123     int level;
 124     int cpu;
 125     int cm;
 126
 127     for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
 128         cm = 1 << cpu;
 129         s->current_pending[cpu] = 1023;
 130         if (!s->enabled || !s->cpu_enabled[cpu]) {
 131             qemu_irq_lower(s->parent_irq[cpu]);
 132             return;
 133         }
 134         best_prio = 0x100;
 135         best_irq = 1023;
 136         for (irq = 0; irq < GIC_NIRQ; irq++) {
 137             if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) {
 138                 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
 139                     best_prio = GIC_GET_PRIORITY(irq, cpu);
 140                     best_irq = irq;
 141                 }
 142             }
 143         }
 144         level = 0;
 145         if (best_prio <= s->priority_mask[cpu]) {
 146             s->current_pending[cpu] = best_irq;
 147             if (best_prio < s->running_priority[cpu]) {
 148                 DPRINTF("Raised pending IRQ %d\n", best_irq);
 149                 level = 1;
 150             }
 151         }
 152         qemu_set_irq(s->parent_irq[cpu], level);
 153     }
 154 }
 155
 156 static void __attribute__((unused))
 157 gic_set_pending_private(gic_state *s, int cpu, int irq)
 158 {
 159     int cm = 1 << cpu;
 160
 161     if (GIC_TEST_PENDING(irq, cm))
 162         return;
 163
 164     DPRINTF("Set %d pending cpu %d\n", irq, cpu);
 165     GIC_SET_PENDING(irq, cm);
 166     gic_update(s);
 167 }
 168
 169 /* Process a change in an external IRQ input.  */
 170 static void gic_set_irq(void *opaque, int irq, int level)
 171 {
 172     gic_state *s = (gic_state *)opaque;
 173     /* The first external input line is internal interrupt 32.  */
 174     irq += 32;
 175     if (level == GIC_TEST_LEVEL(irq, ALL_CPU_MASK))
 176         return;
 177
 178     if (level) {
 179         GIC_SET_LEVEL(irq, ALL_CPU_MASK);
 180         if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, ALL_CPU_MASK)) {
 181             DPRINTF("Set %d pending mask %x\n", irq, GIC_TARGET(irq));
 182             GIC_SET_PENDING(irq, GIC_TARGET(irq));
 183         }
 184     } else {
 185         GIC_CLEAR_LEVEL(irq, ALL_CPU_MASK);
 186     }
 187     gic_update(s);
 188 }
 189
 190 static void gic_set_running_irq(gic_state *s, int cpu, int irq)
 191 {
 192     s->running_irq[cpu] = irq;
 193     if (irq == 1023) {
 194         s->running_priority[cpu] = 0x100;
 195     } else {
 196         s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu);
 197     }
 198     gic_update(s);
 199 }
 200
 201 static uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
 202 {
 203     int new_irq;
 204     int cm = 1 << cpu;
 205     new_irq = s->current_pending[cpu];
 206     if (new_irq == 1023
 207             || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) {
 208         DPRINTF("ACK no pending IRQ\n");
 209         return 1023;
 210     }
 211     s->last_active[new_irq][cpu] = s->running_irq[cpu];
 212     /* Clear pending flags for both level and edge triggered interrupts.
 213        Level triggered IRQs will be reasserted once they become inactive.  */
 214     GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm);
 215     gic_set_running_irq(s, cpu, new_irq);
 216     DPRINTF("ACK %d\n", new_irq);
 217     return new_irq;
 218 }
 219
 220 static void gic_complete_irq(gic_state * s, int cpu, int irq)
 221 {
 222     int update = 0;
 223     int cm = 1 << cpu;
 224     DPRINTF("EOI %d\n", irq);
 225     if (irq >= GIC_NIRQ) {
 226         /* This handles two cases:
 227          * 1. If software writes the ID of a spurious interrupt [ie 1023]
 228          * to the GICC_EOIR, the GIC ignores that write.
 229          * 2. If software writes the number of a non-existent interrupt
 230          * this must be a subcase of "value written does not match the last
 231          * valid interrupt value read from the Interrupt Acknowledge
 232          * register" and so this is UNPREDICTABLE. We choose to ignore it.
 233          */
 234         return;
 235     }
 236     if (s->running_irq[cpu] == 1023)
 237         return; /* No active IRQ.  */
 238     /* Mark level triggered interrupts as pending if they are still
 239        raised.  */
 240     if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
 241         && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
 242         DPRINTF("Set %d pending mask %x\n", irq, cm);
 243         GIC_SET_PENDING(irq, cm);
 244         update = 1;
 245     }
 246     if (irq != s->running_irq[cpu]) {
 247         /* Complete an IRQ that is not currently running.  */
 248         int tmp = s->running_irq[cpu];
 249         while (s->last_active[tmp][cpu] != 1023) {
 250             if (s->last_active[tmp][cpu] == irq) {
 251                 s->last_active[tmp][cpu] = s->last_active[irq][cpu];
 252                 break;
 253             }
 254             tmp = s->last_active[tmp][cpu];
 255         }
 256         if (update) {
 257             gic_update(s);
 258         }
 259     } else {
 260         /* Complete the current running IRQ.  */
 261         gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]);
 262     }
 263 }
 264
 265 static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
 266 {
 267     gic_state *s = (gic_state *)opaque;
 268     uint32_t res;
 269     int irq;
 270     int i;
 271     int cpu;
 272     int cm;
 273     int mask;
 274
 275     cpu = gic_get_current_cpu();
 276     cm = 1 << cpu;
 277     if (offset < 0x100) {
 278 #ifndef NVIC
 279         if (offset == 0)
 280             return s->enabled;
 281         if (offset == 4)
 282             return ((GIC_NIRQ / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
 283         if (offset < 0x08)
 284             return 0;
 285 #endif
 286         goto bad_reg;
 287     } else if (offset < 0x200) {
 288         /* Interrupt Set/Clear Enable.  */
 289         if (offset < 0x180)
 290             irq = (offset - 0x100) * 8;
 291         else
 292             irq = (offset - 0x180) * 8;
 293         irq += GIC_BASE_IRQ;
 294         if (irq >= GIC_NIRQ)
 295             goto bad_reg;
 296         res = 0;
 297         for (i = 0; i < 8; i++) {
 298             if (GIC_TEST_ENABLED(irq + i, cm)) {
 299                 res |= (1 << i);
 300             }
 301         }
 302     } else if (offset < 0x300) {
 303         /* Interrupt Set/Clear Pending.  */
 304         if (offset < 0x280)
 305             irq = (offset - 0x200) * 8;
 306         else
 307             irq = (offset - 0x280) * 8;
 308         irq += GIC_BASE_IRQ;
 309         if (irq >= GIC_NIRQ)
 310             goto bad_reg;
 311         res = 0;
 312         mask = (irq < 32) ?  cm : ALL_CPU_MASK;
 313         for (i = 0; i < 8; i++) {
 314             if (GIC_TEST_PENDING(irq + i, mask)) {
 315                 res |= (1 << i);
 316             }
 317         }
 318     } else if (offset < 0x400) {
 319         /* Interrupt Active.  */
 320         irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
 321         if (irq >= GIC_NIRQ)
 322             goto bad_reg;
 323         res = 0;
 324         mask = (irq < 32) ?  cm : ALL_CPU_MASK;
 325         for (i = 0; i < 8; i++) {
 326             if (GIC_TEST_ACTIVE(irq + i, mask)) {
 327                 res |= (1 << i);
 328             }
 329         }
 330     } else if (offset < 0x800) {
 331         /* Interrupt Priority.  */
 332         irq = (offset - 0x400) + GIC_BASE_IRQ;
 333         if (irq >= GIC_NIRQ)
 334             goto bad_reg;
 335         res = GIC_GET_PRIORITY(irq, cpu);
 336 #ifndef NVIC
 337     } else if (offset < 0xc00) {
 338         /* Interrupt CPU Target.  */
 339         irq = (offset - 0x800) + GIC_BASE_IRQ;
 340         if (irq >= GIC_NIRQ)
 341             goto bad_reg;
 342         if (irq >= 29 && irq <= 31) {
 343             res = cm;
 344         } else {
 345             res = GIC_TARGET(irq);
 346         }
 347     } else if (offset < 0xf00) {
 348         /* Interrupt Configuration.  */
 349         irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
 350         if (irq >= GIC_NIRQ)
 351             goto bad_reg;
 352         res = 0;
 353         for (i = 0; i < 4; i++) {
 354             if (GIC_TEST_MODEL(irq + i))
 355                 res |= (1 << (i * 2));
 356             if (GIC_TEST_TRIGGER(irq + i))
 357                 res |= (2 << (i * 2));
 358         }
 359 #endif
 360     } else if (offset < 0xfe0) {
 361         goto bad_reg;
 362     } else /* offset >= 0xfe0 */ {
 363         if (offset & 3) {
 364             res = 0;
 365         } else {
 366             res = gic_id[(offset - 0xfe0) >> 2];
 367         }
 368     }
 369     return res;
 370 bad_reg:
 371     hw_error("gic_dist_readb: Bad offset %x\n", (int)offset);
 372     return 0;
 373 }
 374
 375 static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
 376 {
 377     uint32_t val;
 378     val = gic_dist_readb(opaque, offset);
 379     val |= gic_dist_readb(opaque, offset + 1) << 8;
 380     return val;
 381 }
 382
 383 static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
 384 {
 385     uint32_t val;
 386 #ifdef NVIC
 387     gic_state *s = (gic_state *)opaque;
 388     uint32_t addr;
 389     addr = offset;
 390     if (addr < 0x100 || addr > 0xd00)
 391         return nvic_readl(s, addr);
 392 #endif
 393     val = gic_dist_readw(opaque, offset);
 394     val |= gic_dist_readw(opaque, offset + 2) << 16;
 395     return val;
 396 }
 397
 398 static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
 399                             uint32_t value)
 400 {
 401     gic_state *s = (gic_state *)opaque;
 402     int irq;
 403     int i;
 404     int cpu;
 405
 406     cpu = gic_get_current_cpu();
 407     if (offset < 0x100) {
 408 #ifdef NVIC
 409         goto bad_reg;
 410 #else
 411         if (offset == 0) {
 412             s->enabled = (value & 1);
 413             DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
 414         } else if (offset < 4) {
 415             /* ignored.  */
 416         } else {
 417             goto bad_reg;
 418         }
 419 #endif
 420     } else if (offset < 0x180) {
 421         /* Interrupt Set Enable.  */
 422         irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
 423         if (irq >= GIC_NIRQ)
 424             goto bad_reg;
 425         if (irq < 16)
 426           value = 0xff;
 427         for (i = 0; i < 8; i++) {
 428             if (value & (1 << i)) {
 429                 int mask = (irq < 32) ? (1 << cpu) : GIC_TARGET(irq);
 430                 int cm = (irq < 32) ? (1 << cpu) : ALL_CPU_MASK;
 431
 432                 if (!GIC_TEST_ENABLED(irq + i, cm)) {
 433                     DPRINTF("Enabled IRQ %d\n", irq + i);
 434                 }
 435                 GIC_SET_ENABLED(irq + i, cm);
 436                 /* If a raised level triggered IRQ enabled then mark
 437                    is as pending.  */
 438                 if (GIC_TEST_LEVEL(irq + i, mask)
 439                         && !GIC_TEST_TRIGGER(irq + i)) {
 440                     DPRINTF("Set %d pending mask %x\n", irq + i, mask);
 441                     GIC_SET_PENDING(irq + i, mask);
 442                 }
 443             }
 444         }
 445     } else if (offset < 0x200) {
 446         /* Interrupt Clear Enable.  */
 447         irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
 448         if (irq >= GIC_NIRQ)
 449             goto bad_reg;
 450         if (irq < 16)
 451           value = 0;
 452         for (i = 0; i < 8; i++) {
 453             if (value & (1 << i)) {
 454                 int cm = (irq < 32) ? (1 << cpu) : ALL_CPU_MASK;
 455
 456                 if (GIC_TEST_ENABLED(irq + i, cm)) {
 457                     DPRINTF("Disabled IRQ %d\n", irq + i);
 458                 }
 459                 GIC_CLEAR_ENABLED(irq + i, cm);
 460             }
 461         }
 462     } else if (offset < 0x280) {
 463         /* Interrupt Set Pending.  */
 464         irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
 465         if (irq >= GIC_NIRQ)
 466             goto bad_reg;
 467         if (irq < 16)
 468           irq = 0;
 469
 470         for (i = 0; i < 8; i++) {
 471             if (value & (1 << i)) {
 472                 GIC_SET_PENDING(irq + i, GIC_TARGET(irq));
 473             }
 474         }
 475     } else if (offset < 0x300) {
 476         /* Interrupt Clear Pending.  */
 477         irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
 478         if (irq >= GIC_NIRQ)
 479             goto bad_reg;
 480         for (i = 0; i < 8; i++) {
 481             /* ??? This currently clears the pending bit for all CPUs, even
 482                for per-CPU interrupts.  It's unclear whether this is the
 483                corect behavior.  */
 484             if (value & (1 << i)) {
 485                 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
 486             }
 487         }
 488     } else if (offset < 0x400) {
 489         /* Interrupt Active.  */
 490         goto bad_reg;
 491     } else if (offset < 0x800) {
 492         /* Interrupt Priority.  */
 493         irq = (offset - 0x400) + GIC_BASE_IRQ;
 494         if (irq >= GIC_NIRQ)
 495             goto bad_reg;
 496         if (irq < 32) {
 497             s->priority1[irq][cpu] = value;
 498         } else {
 499             s->priority2[irq - 32] = value;
 500         }
 501 #ifndef NVIC
 502     } else if (offset < 0xc00) {
 503         /* Interrupt CPU Target.  */
 504         irq = (offset - 0x800) + GIC_BASE_IRQ;
 505         if (irq >= GIC_NIRQ)
 506             goto bad_reg;
 507         if (irq < 29)
 508             value = 0;
 509         else if (irq < 32)
 510             value = ALL_CPU_MASK;
 511         s->irq_target[irq] = value & ALL_CPU_MASK;
 512     } else if (offset < 0xf00) {
 513         /* Interrupt Configuration.  */
 514         irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
 515         if (irq >= GIC_NIRQ)
 516             goto bad_reg;
 517         if (irq < 32)
 518             value |= 0xaa;
 519         for (i = 0; i < 4; i++) {
 520             if (value & (1 << (i * 2))) {
 521                 GIC_SET_MODEL(irq + i);
 522             } else {
 523                 GIC_CLEAR_MODEL(irq + i);
 524             }
 525             if (value & (2 << (i * 2))) {
 526                 GIC_SET_TRIGGER(irq + i);
 527             } else {
 528                 GIC_CLEAR_TRIGGER(irq + i);
 529             }
 530         }
 531 #endif
 532     } else {
 533         /* 0xf00 is only handled for 32-bit writes.  */
 534         goto bad_reg;
 535     }
 536     gic_update(s);
 537     return;
 538 bad_reg:
 539     hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
 540 }
 541
 542 static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
 543                             uint32_t value)
 544 {
 545     gic_dist_writeb(opaque, offset, value & 0xff);
 546     gic_dist_writeb(opaque, offset + 1, value >> 8);
 547 }
 548
 549 static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
 550                             uint32_t value)
 551 {
 552     gic_state *s = (gic_state *)opaque;
 553 #ifdef NVIC
 554     uint32_t addr;
 555     addr = offset;
 556     if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
 557         nvic_writel(s, addr, value);
 558         return;
 559     }
 560 #endif
 561     if (offset == 0xf00) {
 562         int cpu;
 563         int irq;
 564         int mask;
 565
 566         cpu = gic_get_current_cpu();
 567         irq = value & 0x3ff;
 568         switch ((value >> 24) & 3) {
 569         case 0:
 570             mask = (value >> 16) & ALL_CPU_MASK;
 571             break;
 572         case 1:
 573             mask = ALL_CPU_MASK ^ (1 << cpu);
 574             break;
 575         case 2:
 576             mask = 1 << cpu;
 577             break;
 578         default:
 579             DPRINTF("Bad Soft Int target filter\n");
 580             mask = ALL_CPU_MASK;
 581             break;
 582         }
 583         GIC_SET_PENDING(irq, mask);
 584         gic_update(s);
 585         return;
 586     }
 587     gic_dist_writew(opaque, offset, value & 0xffff);
 588     gic_dist_writew(opaque, offset + 2, value >> 16);
 589 }
 590
 591 static const MemoryRegionOps gic_dist_ops = {
 592     .old_mmio = {
 593         .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, },
 594         .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, },
 595     },
 596     .endianness = DEVICE_NATIVE_ENDIAN,
 597 };
 598
 599 #ifndef NVIC
 600 static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset)
 601 {
 602     switch (offset) {
 603     case 0x00: /* Control */
 604         return s->cpu_enabled[cpu];
 605     case 0x04: /* Priority mask */
 606         return s->priority_mask[cpu];
 607     case 0x08: /* Binary Point */
 608         /* ??? Not implemented.  */
 609         return 0;
 610     case 0x0c: /* Acknowledge */
 611         return gic_acknowledge_irq(s, cpu);
 612     case 0x14: /* Runing Priority */
 613         return s->running_priority[cpu];
 614     case 0x18: /* Highest Pending Interrupt */
 615         return s->current_pending[cpu];
 616     default:
 617         hw_error("gic_cpu_read: Bad offset %x\n", (int)offset);
 618         return 0;
 619     }
 620 }
 621
 622 static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)
 623 {
 624     switch (offset) {
 625     case 0x00: /* Control */
 626         s->cpu_enabled[cpu] = (value & 1);
 627         DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis");
 628         break;
 629     case 0x04: /* Priority mask */
 630         s->priority_mask[cpu] = (value & 0xff);
 631         break;
 632     case 0x08: /* Binary Point */
 633         /* ??? Not implemented.  */
 634         break;
 635     case 0x10: /* End Of Interrupt */
 636         return gic_complete_irq(s, cpu, value & 0x3ff);
 637     default:
 638         hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);
 639         return;
 640     }
 641     gic_update(s);
 642 }
 643
 644 /* Wrappers to read/write the GIC CPU interface for the current CPU */
 645 static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
 646                                  unsigned size)
 647 {
 648     gic_state *s = (gic_state *)opaque;
 649     return gic_cpu_read(s, gic_get_current_cpu(), addr & 0xff);
 650 }
 651
 652 static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
 653                               uint64_t value, unsigned size)
 654 {
 655     gic_state *s = (gic_state *)opaque;
 656     gic_cpu_write(s, gic_get_current_cpu(), addr & 0xff, value);
 657 }
 658
 659 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
 660  * These just decode the opaque pointer into gic_state* + cpu id.
 661  */
 662 static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
 663                                 unsigned size)
 664 {
 665     gic_state **backref = (gic_state **)opaque;
 666     gic_state *s = *backref;
 667     int id = (backref - s->backref);
 668     return gic_cpu_read(s, id, addr & 0xff);
 669 }
 670
 671 static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
 672                              uint64_t value, unsigned size)
 673 {
 674     gic_state **backref = (gic_state **)opaque;
 675     gic_state *s = *backref;
 676     int id = (backref - s->backref);
 677     gic_cpu_write(s, id, addr & 0xff, value);
 678 }
 679
 680 static const MemoryRegionOps gic_thiscpu_ops = {
 681     .read = gic_thiscpu_read,
 682     .write = gic_thiscpu_write,
 683     .endianness = DEVICE_NATIVE_ENDIAN,
 684 };
 685
 686 static const MemoryRegionOps gic_cpu_ops = {
 687     .read = gic_do_cpu_read,
 688     .write = gic_do_cpu_write,
 689     .endianness = DEVICE_NATIVE_ENDIAN,
 690 };
 691 #endif
 692
 693 static void gic_reset(gic_state *s)
 694 {
 695     int i;
 696     memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
 697     for (i = 0 ; i < NUM_CPU(s); i++) {
 698         s->priority_mask[i] = 0xf0;
 699         s->current_pending[i] = 1023;
 700         s->running_irq[i] = 1023;
 701         s->running_priority[i] = 0x100;
 702 #ifdef NVIC
 703         /* The NVIC doesn't have per-cpu interfaces, so enable by default.  */
 704         s->cpu_enabled[i] = 1;
 705 #else
 706         s->cpu_enabled[i] = 0;
 707 #endif
 708     }
 709     for (i = 0; i < 16; i++) {
 710         GIC_SET_ENABLED(i, ALL_CPU_MASK);
 711         GIC_SET_TRIGGER(i);
 712     }
 713 #ifdef NVIC
 714     /* The NVIC is always enabled.  */
 715     s->enabled = 1;
 716 #else
 717     s->enabled = 0;
 718 #endif
 719 }
 720
 721 static void gic_save(QEMUFile *f, void *opaque)
 722 {
 723     gic_state *s = (gic_state *)opaque;
 724     int i;
 725     int j;
 726
 727     qemu_put_be32(f, s->enabled);
 728     for (i = 0; i < NUM_CPU(s); i++) {
 729         qemu_put_be32(f, s->cpu_enabled[i]);
 730         for (j = 0; j < 32; j++)
 731             qemu_put_be32(f, s->priority1[j][i]);
 732         for (j = 0; j < GIC_NIRQ; j++)
 733             qemu_put_be32(f, s->last_active[j][i]);
 734         qemu_put_be32(f, s->priority_mask[i]);
 735         qemu_put_be32(f, s->running_irq[i]);
 736         qemu_put_be32(f, s->running_priority[i]);
 737         qemu_put_be32(f, s->current_pending[i]);
 738     }
 739     for (i = 0; i < GIC_NIRQ - 32; i++) {
 740         qemu_put_be32(f, s->priority2[i]);
 741     }
 742     for (i = 0; i < GIC_NIRQ; i++) {
 743 #ifndef NVIC
 744         qemu_put_be32(f, s->irq_target[i]);
 745 #endif
 746         qemu_put_byte(f, s->irq_state[i].enabled);
 747         qemu_put_byte(f, s->irq_state[i].pending);
 748         qemu_put_byte(f, s->irq_state[i].active);
 749         qemu_put_byte(f, s->irq_state[i].level);
 750         qemu_put_byte(f, s->irq_state[i].model);
 751         qemu_put_byte(f, s->irq_state[i].trigger);
 752     }
 753 }
 754
 755 static int gic_load(QEMUFile *f, void *opaque, int version_id)
 756 {
 757     gic_state *s = (gic_state *)opaque;
 758     int i;
 759     int j;
 760
 761     if (version_id != 2)
 762         return -EINVAL;
 763
 764     s->enabled = qemu_get_be32(f);
 765     for (i = 0; i < NUM_CPU(s); i++) {
 766         s->cpu_enabled[i] = qemu_get_be32(f);
 767         for (j = 0; j < 32; j++)
 768             s->priority1[j][i] = qemu_get_be32(f);
 769         for (j = 0; j < GIC_NIRQ; j++)
 770             s->last_active[j][i] = qemu_get_be32(f);
 771         s->priority_mask[i] = qemu_get_be32(f);
 772         s->running_irq[i] = qemu_get_be32(f);
 773         s->running_priority[i] = qemu_get_be32(f);
 774         s->current_pending[i] = qemu_get_be32(f);
 775     }
 776     for (i = 0; i < GIC_NIRQ - 32; i++) {
 777         s->priority2[i] = qemu_get_be32(f);
 778     }
 779     for (i = 0; i < GIC_NIRQ; i++) {
 780 #ifndef NVIC
 781         s->irq_target[i] = qemu_get_be32(f);
 782 #endif
 783         s->irq_state[i].enabled = qemu_get_byte(f);
 784         s->irq_state[i].pending = qemu_get_byte(f);
 785         s->irq_state[i].active = qemu_get_byte(f);
 786         s->irq_state[i].level = qemu_get_byte(f);
 787         s->irq_state[i].model = qemu_get_byte(f);
 788         s->irq_state[i].trigger = qemu_get_byte(f);
 789     }
 790
 791     return 0;
 792 }
 793
 794 #if NCPU > 1
 795 static void gic_init(gic_state *s, int num_cpu)
 796 #else
 797 static void gic_init(gic_state *s)
 798 #endif
 799 {
 800     int i;
 801
 802 #if NCPU > 1
 803     s->num_cpu = num_cpu;
 804 #endif
 805     qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, GIC_NIRQ - 32);
 806     for (i = 0; i < NUM_CPU(s); i++) {
 807         sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
 808     }
 809     memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
 810 #ifndef NVIC
 811     /* Memory regions for the CPU interfaces (NVIC doesn't have these):
 812      * a region for "CPU interface for this core", then a region for
 813      * "CPU interface for core 0", "for core 1", ...
 814      * NB that the memory region size of 0x100 applies for the 11MPCore
 815      * and also cores following the GIC v1 spec (ie A9).
 816      * GIC v2 defines a larger memory region (0x1000) so this will need
 817      * to be extended when we implement A15.
 818      */
 819     memory_region_init_io(&s->cpuiomem[0], &gic_thiscpu_ops, s,
 820                           "gic_cpu", 0x100);
 821     for (i = 0; i < NUM_CPU(s); i++) {
 822         s->backref[i] = s;
 823         memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i],
 824                               "gic_cpu", 0x100);
 825     }
 826 #endif
 827
 828     gic_reset(s);
 829     register_savevm(NULL, "arm_gic", -1, 2, gic_save, gic_load, s);
 830 }