hw/arm_timer.c

   1 /*
   2  * ARM PrimeCell Timer modules.
   3  *
   4  * Copyright (c) 2005-2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "qemu/timer.h"
  12 #include "qemu-common.h"
  13 #include "hw/qdev.h"
  14 #include "hw/ptimer.h"
  15
  16 /* Common timer implementation.  */
  17
  18 #define TIMER_CTRL_ONESHOT      (1 << 0)
  19 #define TIMER_CTRL_32BIT        (1 << 1)
  20 #define TIMER_CTRL_DIV1         (0 << 2)
  21 #define TIMER_CTRL_DIV16        (1 << 2)
  22 #define TIMER_CTRL_DIV256       (2 << 2)
  23 #define TIMER_CTRL_IE           (1 << 5)
  24 #define TIMER_CTRL_PERIODIC     (1 << 6)
  25 #define TIMER_CTRL_ENABLE       (1 << 7)
  26
  27 typedef struct {
  28     ptimer_state *timer;
  29     uint32_t control;
  30     uint32_t limit;
  31     int freq;
  32     int int_level;
  33     qemu_irq irq;
  34 } arm_timer_state;
  35
  36 /* Check all active timers, and schedule the next timer interrupt.  */
  37
  38 static void arm_timer_update(arm_timer_state *s)
  39 {
  40     /* Update interrupts.  */
  41     if (s->int_level && (s->control & TIMER_CTRL_IE)) {
  42         qemu_irq_raise(s->irq);
  43     } else {
  44         qemu_irq_lower(s->irq);
  45     }
  46 }
  47
  48 static uint32_t arm_timer_read(void *opaque, hwaddr offset)
  49 {
  50     arm_timer_state *s = (arm_timer_state *)opaque;
  51
  52     switch (offset >> 2) {
  53     case 0: /* TimerLoad */
  54     case 6: /* TimerBGLoad */
  55         return s->limit;
  56     case 1: /* TimerValue */
  57         return ptimer_get_count(s->timer);
  58     case 2: /* TimerControl */
  59         return s->control;
  60     case 4: /* TimerRIS */
  61         return s->int_level;
  62     case 5: /* TimerMIS */
  63         if ((s->control & TIMER_CTRL_IE) == 0)
  64             return 0;
  65         return s->int_level;
  66     default:
  67         qemu_log_mask(LOG_GUEST_ERROR,
  68                       "%s: Bad offset %x\n", __func__, (int)offset);
  69         return 0;
  70     }
  71 }
  72
  73 /* Reset the timer limit after settings have changed.  */
  74 static void arm_timer_recalibrate(arm_timer_state *s, int reload)
  75 {
  76     uint32_t limit;
  77
  78     if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
  79         /* Free running.  */
  80         if (s->control & TIMER_CTRL_32BIT)
  81             limit = 0xffffffff;
  82         else
  83             limit = 0xffff;
  84     } else {
  85           /* Periodic.  */
  86           limit = s->limit;
  87     }
  88     ptimer_set_limit(s->timer, limit, reload);
  89 }
  90
  91 static void arm_timer_write(void *opaque, hwaddr offset,
  92                             uint32_t value)
  93 {
  94     arm_timer_state *s = (arm_timer_state *)opaque;
  95     int freq;
  96
  97     switch (offset >> 2) {
  98     case 0: /* TimerLoad */
  99         s->limit = value;
 100         arm_timer_recalibrate(s, 1);
 101         break;
 102     case 1: /* TimerValue */
 103         /* ??? Linux seems to want to write to this readonly register.
 104            Ignore it.  */
 105         break;
 106     case 2: /* TimerControl */
 107         if (s->control & TIMER_CTRL_ENABLE) {
 108             /* Pause the timer if it is running.  This may cause some
 109                inaccuracy dure to rounding, but avoids a whole lot of other
 110                messyness.  */
 111             ptimer_stop(s->timer);
 112         }
 113         s->control = value;
 114         freq = s->freq;
 115         /* ??? Need to recalculate expiry time after changing divisor.  */
 116         switch ((value >> 2) & 3) {
 117         case 1: freq >>= 4; break;
 118         case 2: freq >>= 8; break;
 119         }
 120         arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
 121         ptimer_set_freq(s->timer, freq);
 122         if (s->control & TIMER_CTRL_ENABLE) {
 123             /* Restart the timer if still enabled.  */
 124             ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
 125         }
 126         break;
 127     case 3: /* TimerIntClr */
 128         s->int_level = 0;
 129         break;
 130     case 6: /* TimerBGLoad */
 131         s->limit = value;
 132         arm_timer_recalibrate(s, 0);
 133         break;
 134     default:
 135         qemu_log_mask(LOG_GUEST_ERROR,
 136                       "%s: Bad offset %x\n", __func__, (int)offset);
 137     }
 138     arm_timer_update(s);
 139 }
 140
 141 static void arm_timer_tick(void *opaque)
 142 {
 143     arm_timer_state *s = (arm_timer_state *)opaque;
 144     s->int_level = 1;
 145     arm_timer_update(s);
 146 }
 147
 148 static const VMStateDescription vmstate_arm_timer = {
 149     .name = "arm_timer",
 150     .version_id = 1,
 151     .minimum_version_id = 1,
 152     .minimum_version_id_old = 1,
 153     .fields      = (VMStateField[]) {
 154         VMSTATE_UINT32(control, arm_timer_state),
 155         VMSTATE_UINT32(limit, arm_timer_state),
 156         VMSTATE_INT32(int_level, arm_timer_state),
 157         VMSTATE_PTIMER(timer, arm_timer_state),
 158         VMSTATE_END_OF_LIST()
 159     }
 160 };
 161
 162 static arm_timer_state *arm_timer_init(uint32_t freq)
 163 {
 164     arm_timer_state *s;
 165     QEMUBH *bh;
 166
 167     s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
 168     s->freq = freq;
 169     s->control = TIMER_CTRL_IE;
 170
 171     bh = qemu_bh_new(arm_timer_tick, s);
 172     s->timer = ptimer_init(bh);
 173     vmstate_register(NULL, -1, &vmstate_arm_timer, s);
 174     return s;
 175 }
 176
 177 /* ARM PrimeCell SP804 dual timer module.
 178  * Docs at
 179  * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
 180 */
 181
 182 typedef struct {
 183     SysBusDevice busdev;
 184     MemoryRegion iomem;
 185     arm_timer_state *timer[2];
 186     uint32_t freq0, freq1;
 187     int level[2];
 188     qemu_irq irq;
 189 } sp804_state;
 190
 191 static const uint8_t sp804_ids[] = {
 192     /* Timer ID */
 193     0x04, 0x18, 0x14, 0,
 194     /* PrimeCell ID */
 195     0xd, 0xf0, 0x05, 0xb1
 196 };
 197
 198 /* Merge the IRQs from the two component devices.  */
 199 static void sp804_set_irq(void *opaque, int irq, int level)
 200 {
 201     sp804_state *s = (sp804_state *)opaque;
 202
 203     s->level[irq] = level;
 204     qemu_set_irq(s->irq, s->level[0] || s->level[1]);
 205 }
 206
 207 static uint64_t sp804_read(void *opaque, hwaddr offset,
 208                            unsigned size)
 209 {
 210     sp804_state *s = (sp804_state *)opaque;
 211
 212     if (offset < 0x20) {
 213         return arm_timer_read(s->timer[0], offset);
 214     }
 215     if (offset < 0x40) {
 216         return arm_timer_read(s->timer[1], offset - 0x20);
 217     }
 218
 219     /* TimerPeriphID */
 220     if (offset >= 0xfe0 && offset <= 0xffc) {
 221         return sp804_ids[(offset - 0xfe0) >> 2];
 222     }
 223
 224     switch (offset) {
 225     /* Integration Test control registers, which we won't support */
 226     case 0xf00: /* TimerITCR */
 227     case 0xf04: /* TimerITOP (strictly write only but..) */
 228         qemu_log_mask(LOG_UNIMP,
 229                       "%s: integration test registers unimplemented\n",
 230                       __func__);
 231         return 0;
 232     }
 233
 234     qemu_log_mask(LOG_GUEST_ERROR,
 235                   "%s: Bad offset %x\n", __func__, (int)offset);
 236     return 0;
 237 }
 238
 239 static void sp804_write(void *opaque, hwaddr offset,
 240                         uint64_t value, unsigned size)
 241 {
 242     sp804_state *s = (sp804_state *)opaque;
 243
 244     if (offset < 0x20) {
 245         arm_timer_write(s->timer[0], offset, value);
 246         return;
 247     }
 248
 249     if (offset < 0x40) {
 250         arm_timer_write(s->timer[1], offset - 0x20, value);
 251         return;
 252     }
 253
 254     /* Technically we could be writing to the Test Registers, but not likely */
 255     qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n",
 256                   __func__, (int)offset);
 257 }
 258
 259 static const MemoryRegionOps sp804_ops = {
 260     .read = sp804_read,
 261     .write = sp804_write,
 262     .endianness = DEVICE_NATIVE_ENDIAN,
 263 };
 264
 265 static const VMStateDescription vmstate_sp804 = {
 266     .name = "sp804",
 267     .version_id = 1,
 268     .minimum_version_id = 1,
 269     .minimum_version_id_old = 1,
 270     .fields      = (VMStateField[]) {
 271         VMSTATE_INT32_ARRAY(level, sp804_state, 2),
 272         VMSTATE_END_OF_LIST()
 273     }
 274 };
 275
 276 static int sp804_init(SysBusDevice *dev)
 277 {
 278     sp804_state *s = FROM_SYSBUS(sp804_state, dev);
 279     qemu_irq *qi;
 280
 281     qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
 282     sysbus_init_irq(dev, &s->irq);
 283     s->timer[0] = arm_timer_init(s->freq0);
 284     s->timer[1] = arm_timer_init(s->freq1);
 285     s->timer[0]->irq = qi[0];
 286     s->timer[1]->irq = qi[1];
 287     memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
 288     sysbus_init_mmio(dev, &s->iomem);
 289     vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
 290     return 0;
 291 }
 292
 293 /* Integrator/CP timer module.  */
 294
 295 typedef struct {
 296     SysBusDevice busdev;
 297     MemoryRegion iomem;
 298     arm_timer_state *timer[3];
 299 } icp_pit_state;
 300
 301 static uint64_t icp_pit_read(void *opaque, hwaddr offset,
 302                              unsigned size)
 303 {
 304     icp_pit_state *s = (icp_pit_state *)opaque;
 305     int n;
 306
 307     /* ??? Don't know the PrimeCell ID for this device.  */
 308     n = offset >> 8;
 309     if (n > 2) {
 310         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
 311     }
 312
 313     return arm_timer_read(s->timer[n], offset & 0xff);
 314 }
 315
 316 static void icp_pit_write(void *opaque, hwaddr offset,
 317                           uint64_t value, unsigned size)
 318 {
 319     icp_pit_state *s = (icp_pit_state *)opaque;
 320     int n;
 321
 322     n = offset >> 8;
 323     if (n > 2) {
 324         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
 325     }
 326
 327     arm_timer_write(s->timer[n], offset & 0xff, value);
 328 }
 329
 330 static const MemoryRegionOps icp_pit_ops = {
 331     .read = icp_pit_read,
 332     .write = icp_pit_write,
 333     .endianness = DEVICE_NATIVE_ENDIAN,
 334 };
 335
 336 static int icp_pit_init(SysBusDevice *dev)
 337 {
 338     icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
 339
 340     /* Timer 0 runs at the system clock speed (40MHz).  */
 341     s->timer[0] = arm_timer_init(40000000);
 342     /* The other two timers run at 1MHz.  */
 343     s->timer[1] = arm_timer_init(1000000);
 344     s->timer[2] = arm_timer_init(1000000);
 345
 346     sysbus_init_irq(dev, &s->timer[0]->irq);
 347     sysbus_init_irq(dev, &s->timer[1]->irq);
 348     sysbus_init_irq(dev, &s->timer[2]->irq);
 349
 350     memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000);
 351     sysbus_init_mmio(dev, &s->iomem);
 352     /* This device has no state to save/restore.  The component timers will
 353        save themselves.  */
 354     return 0;
 355 }
 356
 357 static void icp_pit_class_init(ObjectClass *klass, void *data)
 358 {
 359     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 360
 361     sdc->init = icp_pit_init;
 362 }
 363
 364 static const TypeInfo icp_pit_info = {
 365     .name          = "integrator_pit",
 366     .parent        = TYPE_SYS_BUS_DEVICE,
 367     .instance_size = sizeof(icp_pit_state),
 368     .class_init    = icp_pit_class_init,
 369 };
 370
 371 static Property sp804_properties[] = {
 372     DEFINE_PROP_UINT32("freq0", sp804_state, freq0, 1000000),
 373     DEFINE_PROP_UINT32("freq1", sp804_state, freq1, 1000000),
 374     DEFINE_PROP_END_OF_LIST(),
 375 };
 376
 377 static void sp804_class_init(ObjectClass *klass, void *data)
 378 {
 379     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 380     DeviceClass *k = DEVICE_CLASS(klass);
 381
 382     sdc->init = sp804_init;
 383     k->props = sp804_properties;
 384 }
 385
 386 static const TypeInfo sp804_info = {
 387     .name          = "sp804",
 388     .parent        = TYPE_SYS_BUS_DEVICE,
 389     .instance_size = sizeof(sp804_state),
 390     .class_init    = sp804_class_init,
 391 };
 392
 393 static void arm_timer_register_types(void)
 394 {
 395     type_register_static(&icp_pit_info);
 396     type_register_static(&sp804_info);
 397 }
 398
 399 type_init(arm_timer_register_types)