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1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <kraxel@redhat.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/pci/pci.h"
22 #include "hw/qdev-properties.h"
23 #include "hw/pci/msi.h"
24 #include "qemu/timer.h"
25 #include "qemu/bitops.h"
26 #include "qemu/log.h"
27 #include "qemu/module.h"
28 #include "qemu/error-report.h"
29 #include "hw/audio/soundhw.h"
30 #include "intel-hda.h"
31 #include "migration/vmstate.h"
32 #include "intel-hda-defs.h"
33 #include "sysemu/dma.h"
34 #include "qapi/error.h"
35 #include "qom/object.h"
36
37 /* --------------------------------------------------------------------- */
38 /* hda bus */
39
40 static Property hda_props[] = {
41 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
42 DEFINE_PROP_END_OF_LIST()
43 };
44
45 static const TypeInfo hda_codec_bus_info = {
46 .name = TYPE_HDA_BUS,
47 .parent = TYPE_BUS,
48 .instance_size = sizeof(HDACodecBus),
49 };
50
51 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
52 hda_codec_response_func response,
53 hda_codec_xfer_func xfer)
54 {
55 qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
56 bus->response = response;
57 bus->xfer = xfer;
58 }
59
60 static void hda_codec_dev_realize(DeviceState *qdev, Error **errp)
61 {
62 HDACodecBus *bus = HDA_BUS(qdev->parent_bus);
63 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
64 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
65
66 if (dev->cad == -1) {
67 dev->cad = bus->next_cad;
68 }
69 if (dev->cad >= 15) {
70 error_setg(errp, "HDA audio codec address is full");
71 return;
72 }
73 bus->next_cad = dev->cad + 1;
74 if (cdc->init(dev) != 0) {
75 error_setg(errp, "HDA audio init failed");
76 }
77 }
78
79 static void hda_codec_dev_unrealize(DeviceState *qdev)
80 {
81 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
82 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
83
84 if (cdc->exit) {
85 cdc->exit(dev);
86 }
87 }
88
89 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
90 {
91 BusChild *kid;
92 HDACodecDevice *cdev;
93
94 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
95 DeviceState *qdev = kid->child;
96 cdev = HDA_CODEC_DEVICE(qdev);
97 if (cdev->cad == cad) {
98 return cdev;
99 }
100 }
101 return NULL;
102 }
103
104 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
105 {
106 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
107 bus->response(dev, solicited, response);
108 }
109
110 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
111 uint8_t *buf, uint32_t len)
112 {
113 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
114 return bus->xfer(dev, stnr, output, buf, len);
115 }
116
117 /* --------------------------------------------------------------------- */
118 /* intel hda emulation */
119
120 typedef struct IntelHDAStream IntelHDAStream;
121 typedef struct IntelHDAState IntelHDAState;
122 typedef struct IntelHDAReg IntelHDAReg;
123
124 typedef struct bpl {
125 uint64_t addr;
126 uint32_t len;
127 uint32_t flags;
128 } bpl;
129
130 struct IntelHDAStream {
131 /* registers */
132 uint32_t ctl;
133 uint32_t lpib;
134 uint32_t cbl;
135 uint32_t lvi;
136 uint32_t fmt;
137 uint32_t bdlp_lbase;
138 uint32_t bdlp_ubase;
139
140 /* state */
141 bpl *bpl;
142 uint32_t bentries;
143 uint32_t bsize, be, bp;
144 };
145
146 struct IntelHDAState {
147 PCIDevice pci;
148 const char *name;
149 HDACodecBus codecs;
150
151 /* registers */
152 uint32_t g_ctl;
153 uint32_t wake_en;
154 uint32_t state_sts;
155 uint32_t int_ctl;
156 uint32_t int_sts;
157 uint32_t wall_clk;
158
159 uint32_t corb_lbase;
160 uint32_t corb_ubase;
161 uint32_t corb_rp;
162 uint32_t corb_wp;
163 uint32_t corb_ctl;
164 uint32_t corb_sts;
165 uint32_t corb_size;
166
167 uint32_t rirb_lbase;
168 uint32_t rirb_ubase;
169 uint32_t rirb_wp;
170 uint32_t rirb_cnt;
171 uint32_t rirb_ctl;
172 uint32_t rirb_sts;
173 uint32_t rirb_size;
174
175 uint32_t dp_lbase;
176 uint32_t dp_ubase;
177
178 uint32_t icw;
179 uint32_t irr;
180 uint32_t ics;
181
182 /* streams */
183 IntelHDAStream st[8];
184
185 /* state */
186 MemoryRegion container;
187 MemoryRegion mmio;
188 MemoryRegion alias;
189 uint32_t rirb_count;
190 int64_t wall_base_ns;
191
192 /* debug logging */
193 const IntelHDAReg *last_reg;
194 uint32_t last_val;
195 uint32_t last_write;
196 uint32_t last_sec;
197 uint32_t repeat_count;
198
199 /* properties */
200 uint32_t debug;
201 OnOffAuto msi;
202 bool old_msi_addr;
203 };
204
205 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
206
207 DECLARE_INSTANCE_CHECKER(IntelHDAState, INTEL_HDA,
208 TYPE_INTEL_HDA_GENERIC)
209
210 struct IntelHDAReg {
211 const char *name; /* register name */
212 uint32_t size; /* size in bytes */
213 uint32_t reset; /* reset value */
214 uint32_t wmask; /* write mask */
215 uint32_t wclear; /* write 1 to clear bits */
216 uint32_t offset; /* location in IntelHDAState */
217 uint32_t shift; /* byte access entries for dwords */
218 uint32_t stream;
219 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
220 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
221 };
222
223 static void intel_hda_reset(DeviceState *dev);
224
225 /* --------------------------------------------------------------------- */
226
227 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
228 {
229 return ((uint64_t)ubase << 32) | lbase;
230 }
231
232 static void intel_hda_update_int_sts(IntelHDAState *d)
233 {
234 uint32_t sts = 0;
235 uint32_t i;
236
237 /* update controller status */
238 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
239 sts |= (1 << 30);
240 }
241 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
242 sts |= (1 << 30);
243 }
244 if (d->state_sts & d->wake_en) {
245 sts |= (1 << 30);
246 }
247
248 /* update stream status */
249 for (i = 0; i < 8; i++) {
250 /* buffer completion interrupt */
251 if (d->st[i].ctl & (1 << 26)) {
252 sts |= (1 << i);
253 }
254 }
255
256 /* update global status */
257 if (sts & d->int_ctl) {
258 sts |= (1U << 31);
259 }
260
261 d->int_sts = sts;
262 }
263
264 static void intel_hda_update_irq(IntelHDAState *d)
265 {
266 bool msi = msi_enabled(&d->pci);
267 int level;
268
269 intel_hda_update_int_sts(d);
270 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) {
271 level = 1;
272 } else {
273 level = 0;
274 }
275 dprint(d, 2, "%s: level %d [%s]\n", __func__,
276 level, msi ? "msi" : "intx");
277 if (msi) {
278 if (level) {
279 msi_notify(&d->pci, 0);
280 }
281 } else {
282 pci_set_irq(&d->pci, level);
283 }
284 }
285
286 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
287 {
288 uint32_t cad, nid, data;
289 HDACodecDevice *codec;
290 HDACodecDeviceClass *cdc;
291
292 cad = (verb >> 28) & 0x0f;
293 if (verb & (1 << 27)) {
294 /* indirect node addressing, not specified in HDA 1.0 */
295 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__);
296 return -1;
297 }
298 nid = (verb >> 20) & 0x7f;
299 data = verb & 0xfffff;
300
301 codec = hda_codec_find(&d->codecs, cad);
302 if (codec == NULL) {
303 dprint(d, 1, "%s: addressed non-existing codec\n", __func__);
304 return -1;
305 }
306 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
307 cdc->command(codec, nid, data);
308 return 0;
309 }
310
311 static void intel_hda_corb_run(IntelHDAState *d)
312 {
313 hwaddr addr;
314 uint32_t rp, verb;
315
316 if (d->ics & ICH6_IRS_BUSY) {
317 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw);
318 intel_hda_send_command(d, d->icw);
319 return;
320 }
321
322 for (;;) {
323 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
324 dprint(d, 2, "%s: !run\n", __func__);
325 return;
326 }
327 if ((d->corb_rp & 0xff) == d->corb_wp) {
328 dprint(d, 2, "%s: corb ring empty\n", __func__);
329 return;
330 }
331 if (d->rirb_count == d->rirb_cnt) {
332 dprint(d, 2, "%s: rirb count reached\n", __func__);
333 return;
334 }
335
336 rp = (d->corb_rp + 1) & 0xff;
337 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
338 ldl_le_pci_dma(&d->pci, addr + 4 * rp, &verb, MEMTXATTRS_UNSPECIFIED);
339 d->corb_rp = rp;
340
341 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb);
342 intel_hda_send_command(d, verb);
343 }
344 }
345
346 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
347 {
348 const MemTxAttrs attrs = { .memory = true };
349 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
350 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
351 hwaddr addr;
352 uint32_t wp, ex;
353 MemTxResult res = MEMTX_OK;
354
355 if (d->ics & ICH6_IRS_BUSY) {
356 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
357 __func__, response, dev->cad);
358 d->irr = response;
359 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
360 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
361 return;
362 }
363
364 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
365 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__);
366 return;
367 }
368
369 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
370 wp = (d->rirb_wp + 1) & 0xff;
371 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
372 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp, response, attrs);
373 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp + 4, ex, attrs);
374 if (res != MEMTX_OK && (d->rirb_ctl & ICH6_RBCTL_OVERRUN_EN)) {
375 d->rirb_sts |= ICH6_RBSTS_OVERRUN;
376 intel_hda_update_irq(d);
377 }
378 d->rirb_wp = wp;
379
380 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
381 __func__, wp, response, ex);
382
383 d->rirb_count++;
384 if (d->rirb_count == d->rirb_cnt) {
385 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count);
386 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
387 d->rirb_sts |= ICH6_RBSTS_IRQ;
388 intel_hda_update_irq(d);
389 }
390 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
391 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__,
392 d->rirb_count, d->rirb_cnt);
393 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
394 d->rirb_sts |= ICH6_RBSTS_IRQ;
395 intel_hda_update_irq(d);
396 }
397 }
398 }
399
400 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
401 uint8_t *buf, uint32_t len)
402 {
403 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
404 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
405 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
406 hwaddr addr;
407 uint32_t s, copy, left;
408 IntelHDAStream *st;
409 bool irq = false;
410
411 st = output ? d->st + 4 : d->st;
412 for (s = 0; s < 4; s++) {
413 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
414 st = st + s;
415 break;
416 }
417 }
418 if (s == 4) {
419 return false;
420 }
421 if (st->bpl == NULL) {
422 return false;
423 }
424
425 left = len;
426 s = st->bentries;
427 while (left > 0 && s-- > 0) {
428 copy = left;
429 if (copy > st->bsize - st->lpib)
430 copy = st->bsize - st->lpib;
431 if (copy > st->bpl[st->be].len - st->bp)
432 copy = st->bpl[st->be].len - st->bp;
433
434 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
435 st->be, st->bp, st->bpl[st->be].len, copy);
436
437 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output,
438 attrs);
439 st->lpib += copy;
440 st->bp += copy;
441 buf += copy;
442 left -= copy;
443
444 if (st->bpl[st->be].len == st->bp) {
445 /* bpl entry filled */
446 if (st->bpl[st->be].flags & 0x01) {
447 irq = true;
448 }
449 st->bp = 0;
450 st->be++;
451 if (st->be == st->bentries) {
452 /* bpl wrap around */
453 st->be = 0;
454 st->lpib = 0;
455 }
456 }
457 }
458 if (d->dp_lbase & 0x01) {
459 s = st - d->st;
460 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
461 stl_le_pci_dma(&d->pci, addr + 8 * s, st->lpib, attrs);
462 }
463 dprint(d, 3, "dma: --\n");
464
465 if (irq) {
466 st->ctl |= (1 << 26); /* buffer completion interrupt */
467 intel_hda_update_irq(d);
468 }
469 return true;
470 }
471
472 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
473 {
474 hwaddr addr;
475 uint8_t buf[16];
476 uint32_t i;
477
478 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
479 st->bentries = st->lvi +1;
480 g_free(st->bpl);
481 st->bpl = g_new(bpl, st->bentries);
482 for (i = 0; i < st->bentries; i++, addr += 16) {
483 pci_dma_read(&d->pci, addr, buf, 16);
484 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
485 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
486 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
487 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
488 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
489 }
490
491 st->bsize = st->cbl;
492 st->lpib = 0;
493 st->be = 0;
494 st->bp = 0;
495 }
496
497 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
498 {
499 BusChild *kid;
500 HDACodecDevice *cdev;
501
502 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
503 DeviceState *qdev = kid->child;
504 HDACodecDeviceClass *cdc;
505
506 cdev = HDA_CODEC_DEVICE(qdev);
507 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
508 if (cdc->stream) {
509 cdc->stream(cdev, stream, running, output);
510 }
511 }
512 }
513
514 /* --------------------------------------------------------------------- */
515
516 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
517 {
518 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
519 device_cold_reset(DEVICE(d));
520 }
521 }
522
523 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
524 {
525 intel_hda_update_irq(d);
526 }
527
528 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
529 {
530 intel_hda_update_irq(d);
531 }
532
533 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
534 {
535 intel_hda_update_irq(d);
536 }
537
538 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
539 {
540 int64_t ns;
541
542 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns;
543 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
544 }
545
546 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
547 {
548 intel_hda_corb_run(d);
549 }
550
551 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
552 {
553 intel_hda_corb_run(d);
554 }
555
556 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
557 {
558 if (d->rirb_wp & ICH6_RIRBWP_RST) {
559 d->rirb_wp = 0;
560 }
561 }
562
563 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
564 {
565 intel_hda_update_irq(d);
566
567 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
568 /* cleared ICH6_RBSTS_IRQ */
569 d->rirb_count = 0;
570 intel_hda_corb_run(d);
571 }
572 }
573
574 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
575 {
576 if (d->ics & ICH6_IRS_BUSY) {
577 intel_hda_corb_run(d);
578 }
579 }
580
581 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
582 {
583 bool output = reg->stream >= 4;
584 IntelHDAStream *st = d->st + reg->stream;
585
586 if (st->ctl & 0x01) {
587 /* reset */
588 dprint(d, 1, "st #%d: reset\n", reg->stream);
589 st->ctl = SD_STS_FIFO_READY << 24 | SD_CTL_STREAM_RESET;
590 }
591 if ((st->ctl & 0x02) != (old & 0x02)) {
592 uint32_t stnr = (st->ctl >> 20) & 0x0f;
593 /* run bit flipped */
594 if (st->ctl & 0x02) {
595 /* start */
596 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
597 reg->stream, stnr, st->cbl);
598 intel_hda_parse_bdl(d, st);
599 intel_hda_notify_codecs(d, stnr, true, output);
600 } else {
601 /* stop */
602 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
603 intel_hda_notify_codecs(d, stnr, false, output);
604 }
605 }
606 intel_hda_update_irq(d);
607 }
608
609 /* --------------------------------------------------------------------- */
610
611 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
612
613 static const struct IntelHDAReg regtab[] = {
614 /* global */
615 [ ICH6_REG_GCAP ] = {
616 .name = "GCAP",
617 .size = 2,
618 .reset = 0x4401,
619 },
620 [ ICH6_REG_VMIN ] = {
621 .name = "VMIN",
622 .size = 1,
623 },
624 [ ICH6_REG_VMAJ ] = {
625 .name = "VMAJ",
626 .size = 1,
627 .reset = 1,
628 },
629 [ ICH6_REG_OUTPAY ] = {
630 .name = "OUTPAY",
631 .size = 2,
632 .reset = 0x3c,
633 },
634 [ ICH6_REG_INPAY ] = {
635 .name = "INPAY",
636 .size = 2,
637 .reset = 0x1d,
638 },
639 [ ICH6_REG_GCTL ] = {
640 .name = "GCTL",
641 .size = 4,
642 .wmask = 0x0103,
643 .offset = offsetof(IntelHDAState, g_ctl),
644 .whandler = intel_hda_set_g_ctl,
645 },
646 [ ICH6_REG_WAKEEN ] = {
647 .name = "WAKEEN",
648 .size = 2,
649 .wmask = 0x7fff,
650 .offset = offsetof(IntelHDAState, wake_en),
651 .whandler = intel_hda_set_wake_en,
652 },
653 [ ICH6_REG_STATESTS ] = {
654 .name = "STATESTS",
655 .size = 2,
656 .wmask = 0x7fff,
657 .wclear = 0x7fff,
658 .offset = offsetof(IntelHDAState, state_sts),
659 .whandler = intel_hda_set_state_sts,
660 },
661
662 /* interrupts */
663 [ ICH6_REG_INTCTL ] = {
664 .name = "INTCTL",
665 .size = 4,
666 .wmask = 0xc00000ff,
667 .offset = offsetof(IntelHDAState, int_ctl),
668 .whandler = intel_hda_set_int_ctl,
669 },
670 [ ICH6_REG_INTSTS ] = {
671 .name = "INTSTS",
672 .size = 4,
673 .wmask = 0xc00000ff,
674 .wclear = 0xc00000ff,
675 .offset = offsetof(IntelHDAState, int_sts),
676 },
677
678 /* misc */
679 [ ICH6_REG_WALLCLK ] = {
680 .name = "WALLCLK",
681 .size = 4,
682 .offset = offsetof(IntelHDAState, wall_clk),
683 .rhandler = intel_hda_get_wall_clk,
684 },
685
686 /* dma engine */
687 [ ICH6_REG_CORBLBASE ] = {
688 .name = "CORBLBASE",
689 .size = 4,
690 .wmask = 0xffffff80,
691 .offset = offsetof(IntelHDAState, corb_lbase),
692 },
693 [ ICH6_REG_CORBUBASE ] = {
694 .name = "CORBUBASE",
695 .size = 4,
696 .wmask = 0xffffffff,
697 .offset = offsetof(IntelHDAState, corb_ubase),
698 },
699 [ ICH6_REG_CORBWP ] = {
700 .name = "CORBWP",
701 .size = 2,
702 .wmask = 0xff,
703 .offset = offsetof(IntelHDAState, corb_wp),
704 .whandler = intel_hda_set_corb_wp,
705 },
706 [ ICH6_REG_CORBRP ] = {
707 .name = "CORBRP",
708 .size = 2,
709 .wmask = 0x80ff,
710 .offset = offsetof(IntelHDAState, corb_rp),
711 },
712 [ ICH6_REG_CORBCTL ] = {
713 .name = "CORBCTL",
714 .size = 1,
715 .wmask = 0x03,
716 .offset = offsetof(IntelHDAState, corb_ctl),
717 .whandler = intel_hda_set_corb_ctl,
718 },
719 [ ICH6_REG_CORBSTS ] = {
720 .name = "CORBSTS",
721 .size = 1,
722 .wmask = 0x01,
723 .wclear = 0x01,
724 .offset = offsetof(IntelHDAState, corb_sts),
725 },
726 [ ICH6_REG_CORBSIZE ] = {
727 .name = "CORBSIZE",
728 .size = 1,
729 .reset = 0x42,
730 .offset = offsetof(IntelHDAState, corb_size),
731 },
732 [ ICH6_REG_RIRBLBASE ] = {
733 .name = "RIRBLBASE",
734 .size = 4,
735 .wmask = 0xffffff80,
736 .offset = offsetof(IntelHDAState, rirb_lbase),
737 },
738 [ ICH6_REG_RIRBUBASE ] = {
739 .name = "RIRBUBASE",
740 .size = 4,
741 .wmask = 0xffffffff,
742 .offset = offsetof(IntelHDAState, rirb_ubase),
743 },
744 [ ICH6_REG_RIRBWP ] = {
745 .name = "RIRBWP",
746 .size = 2,
747 .wmask = 0x8000,
748 .offset = offsetof(IntelHDAState, rirb_wp),
749 .whandler = intel_hda_set_rirb_wp,
750 },
751 [ ICH6_REG_RINTCNT ] = {
752 .name = "RINTCNT",
753 .size = 2,
754 .wmask = 0xff,
755 .offset = offsetof(IntelHDAState, rirb_cnt),
756 },
757 [ ICH6_REG_RIRBCTL ] = {
758 .name = "RIRBCTL",
759 .size = 1,
760 .wmask = 0x07,
761 .offset = offsetof(IntelHDAState, rirb_ctl),
762 },
763 [ ICH6_REG_RIRBSTS ] = {
764 .name = "RIRBSTS",
765 .size = 1,
766 .wmask = 0x05,
767 .wclear = 0x05,
768 .offset = offsetof(IntelHDAState, rirb_sts),
769 .whandler = intel_hda_set_rirb_sts,
770 },
771 [ ICH6_REG_RIRBSIZE ] = {
772 .name = "RIRBSIZE",
773 .size = 1,
774 .reset = 0x42,
775 .offset = offsetof(IntelHDAState, rirb_size),
776 },
777
778 [ ICH6_REG_DPLBASE ] = {
779 .name = "DPLBASE",
780 .size = 4,
781 .wmask = 0xffffff81,
782 .offset = offsetof(IntelHDAState, dp_lbase),
783 },
784 [ ICH6_REG_DPUBASE ] = {
785 .name = "DPUBASE",
786 .size = 4,
787 .wmask = 0xffffffff,
788 .offset = offsetof(IntelHDAState, dp_ubase),
789 },
790
791 [ ICH6_REG_IC ] = {
792 .name = "ICW",
793 .size = 4,
794 .wmask = 0xffffffff,
795 .offset = offsetof(IntelHDAState, icw),
796 },
797 [ ICH6_REG_IR ] = {
798 .name = "IRR",
799 .size = 4,
800 .offset = offsetof(IntelHDAState, irr),
801 },
802 [ ICH6_REG_IRS ] = {
803 .name = "ICS",
804 .size = 2,
805 .wmask = 0x0003,
806 .wclear = 0x0002,
807 .offset = offsetof(IntelHDAState, ics),
808 .whandler = intel_hda_set_ics,
809 },
810
811 #define HDA_STREAM(_t, _i) \
812 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
813 .stream = _i, \
814 .name = _t stringify(_i) " CTL", \
815 .size = 4, \
816 .wmask = 0x1cff001f, \
817 .offset = offsetof(IntelHDAState, st[_i].ctl), \
818 .whandler = intel_hda_set_st_ctl, \
819 }, \
820 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
821 .stream = _i, \
822 .name = _t stringify(_i) " CTL(stnr)", \
823 .size = 1, \
824 .shift = 16, \
825 .wmask = 0x00ff0000, \
826 .offset = offsetof(IntelHDAState, st[_i].ctl), \
827 .whandler = intel_hda_set_st_ctl, \
828 }, \
829 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
830 .stream = _i, \
831 .name = _t stringify(_i) " CTL(sts)", \
832 .size = 1, \
833 .shift = 24, \
834 .wmask = 0x1c000000, \
835 .wclear = 0x1c000000, \
836 .offset = offsetof(IntelHDAState, st[_i].ctl), \
837 .whandler = intel_hda_set_st_ctl, \
838 .reset = SD_STS_FIFO_READY << 24 \
839 }, \
840 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
841 .stream = _i, \
842 .name = _t stringify(_i) " LPIB", \
843 .size = 4, \
844 .offset = offsetof(IntelHDAState, st[_i].lpib), \
845 }, \
846 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
847 .stream = _i, \
848 .name = _t stringify(_i) " CBL", \
849 .size = 4, \
850 .wmask = 0xffffffff, \
851 .offset = offsetof(IntelHDAState, st[_i].cbl), \
852 }, \
853 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
854 .stream = _i, \
855 .name = _t stringify(_i) " LVI", \
856 .size = 2, \
857 .wmask = 0x00ff, \
858 .offset = offsetof(IntelHDAState, st[_i].lvi), \
859 }, \
860 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
861 .stream = _i, \
862 .name = _t stringify(_i) " FIFOS", \
863 .size = 2, \
864 .reset = HDA_BUFFER_SIZE, \
865 }, \
866 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
867 .stream = _i, \
868 .name = _t stringify(_i) " FMT", \
869 .size = 2, \
870 .wmask = 0x7f7f, \
871 .offset = offsetof(IntelHDAState, st[_i].fmt), \
872 }, \
873 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
874 .stream = _i, \
875 .name = _t stringify(_i) " BDLPL", \
876 .size = 4, \
877 .wmask = 0xffffff80, \
878 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
879 }, \
880 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
881 .stream = _i, \
882 .name = _t stringify(_i) " BDLPU", \
883 .size = 4, \
884 .wmask = 0xffffffff, \
885 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
886 }, \
887
888 HDA_STREAM("IN", 0)
889 HDA_STREAM("IN", 1)
890 HDA_STREAM("IN", 2)
891 HDA_STREAM("IN", 3)
892
893 HDA_STREAM("OUT", 4)
894 HDA_STREAM("OUT", 5)
895 HDA_STREAM("OUT", 6)
896 HDA_STREAM("OUT", 7)
897
898 };
899
900 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
901 {
902 const IntelHDAReg *reg;
903
904 if (addr >= ARRAY_SIZE(regtab)) {
905 goto noreg;
906 }
907 reg = regtab+addr;
908 if (reg->name == NULL) {
909 goto noreg;
910 }
911 return reg;
912
913 noreg:
914 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
915 return NULL;
916 }
917
918 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
919 {
920 uint8_t *addr = (void*)d;
921
922 addr += reg->offset;
923 return (uint32_t*)addr;
924 }
925
926 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
927 uint32_t wmask)
928 {
929 uint32_t *addr;
930 uint32_t old;
931
932 if (!reg) {
933 return;
934 }
935 if (!reg->wmask) {
936 qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n",
937 reg->name);
938 return;
939 }
940
941 if (d->debug) {
942 time_t now = time(NULL);
943 if (d->last_write && d->last_reg == reg && d->last_val == val) {
944 d->repeat_count++;
945 if (d->last_sec != now) {
946 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
947 d->last_sec = now;
948 d->repeat_count = 0;
949 }
950 } else {
951 if (d->repeat_count) {
952 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
953 }
954 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
955 d->last_write = 1;
956 d->last_reg = reg;
957 d->last_val = val;
958 d->last_sec = now;
959 d->repeat_count = 0;
960 }
961 }
962 assert(reg->offset != 0);
963
964 addr = intel_hda_reg_addr(d, reg);
965 old = *addr;
966
967 if (reg->shift) {
968 val <<= reg->shift;
969 wmask <<= reg->shift;
970 }
971 wmask &= reg->wmask;
972 *addr &= ~wmask;
973 *addr |= wmask & val;
974 *addr &= ~(val & reg->wclear);
975
976 if (reg->whandler) {
977 reg->whandler(d, reg, old);
978 }
979 }
980
981 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
982 uint32_t rmask)
983 {
984 uint32_t *addr, ret;
985
986 if (!reg) {
987 return 0;
988 }
989
990 if (reg->rhandler) {
991 reg->rhandler(d, reg);
992 }
993
994 if (reg->offset == 0) {
995 /* constant read-only register */
996 ret = reg->reset;
997 } else {
998 addr = intel_hda_reg_addr(d, reg);
999 ret = *addr;
1000 if (reg->shift) {
1001 ret >>= reg->shift;
1002 }
1003 ret &= rmask;
1004 }
1005 if (d->debug) {
1006 time_t now = time(NULL);
1007 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1008 d->repeat_count++;
1009 if (d->last_sec != now) {
1010 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1011 d->last_sec = now;
1012 d->repeat_count = 0;
1013 }
1014 } else {
1015 if (d->repeat_count) {
1016 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1017 }
1018 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1019 d->last_write = 0;
1020 d->last_reg = reg;
1021 d->last_val = ret;
1022 d->last_sec = now;
1023 d->repeat_count = 0;
1024 }
1025 }
1026 return ret;
1027 }
1028
1029 static void intel_hda_regs_reset(IntelHDAState *d)
1030 {
1031 uint32_t *addr;
1032 int i;
1033
1034 for (i = 0; i < ARRAY_SIZE(regtab); i++) {
1035 if (regtab[i].name == NULL) {
1036 continue;
1037 }
1038 if (regtab[i].offset == 0) {
1039 continue;
1040 }
1041 addr = intel_hda_reg_addr(d, regtab + i);
1042 *addr = regtab[i].reset;
1043 }
1044 }
1045
1046 /* --------------------------------------------------------------------- */
1047
1048 static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val,
1049 unsigned size)
1050 {
1051 IntelHDAState *d = opaque;
1052 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1053
1054 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8));
1055 }
1056
1057 static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size)
1058 {
1059 IntelHDAState *d = opaque;
1060 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1061
1062 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8));
1063 }
1064
1065 static const MemoryRegionOps intel_hda_mmio_ops = {
1066 .read = intel_hda_mmio_read,
1067 .write = intel_hda_mmio_write,
1068 .impl = {
1069 .min_access_size = 1,
1070 .max_access_size = 4,
1071 },
1072 .endianness = DEVICE_NATIVE_ENDIAN,
1073 };
1074
1075 /* --------------------------------------------------------------------- */
1076
1077 static void intel_hda_reset(DeviceState *dev)
1078 {
1079 BusChild *kid;
1080 IntelHDAState *d = INTEL_HDA(dev);
1081 HDACodecDevice *cdev;
1082
1083 intel_hda_regs_reset(d);
1084 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1085
1086 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
1087 DeviceState *qdev = kid->child;
1088 cdev = HDA_CODEC_DEVICE(qdev);
1089 d->state_sts |= (1 << cdev->cad);
1090 }
1091 intel_hda_update_irq(d);
1092 }
1093
1094 static void intel_hda_realize(PCIDevice *pci, Error **errp)
1095 {
1096 IntelHDAState *d = INTEL_HDA(pci);
1097 uint8_t *conf = d->pci.config;
1098 Error *err = NULL;
1099 int ret;
1100
1101 d->name = object_get_typename(OBJECT(d));
1102
1103 pci_config_set_interrupt_pin(conf, 1);
1104
1105 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1106 conf[0x40] = 0x01;
1107
1108 if (d->msi != ON_OFF_AUTO_OFF) {
1109 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60,
1110 1, true, false, &err);
1111 /* Any error other than -ENOTSUP(board's MSI support is broken)
1112 * is a programming error */
1113 assert(!ret || ret == -ENOTSUP);
1114 if (ret && d->msi == ON_OFF_AUTO_ON) {
1115 /* Can't satisfy user's explicit msi=on request, fail */
1116 error_append_hint(&err, "You have to use msi=auto (default) or "
1117 "msi=off with this machine type.\n");
1118 error_propagate(errp, err);
1119 return;
1120 }
1121 assert(!err || d->msi == ON_OFF_AUTO_AUTO);
1122 /* With msi=auto, we fall back to MSI off silently */
1123 error_free(err);
1124 }
1125
1126 memory_region_init(&d->container, OBJECT(d),
1127 "intel-hda-container", 0x4000);
1128 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
1129 "intel-hda", 0x2000);
1130 memory_region_add_subregion(&d->container, 0x0000, &d->mmio);
1131 memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias",
1132 &d->mmio, 0, 0x2000);
1133 memory_region_add_subregion(&d->container, 0x2000, &d->alias);
1134 pci_register_bar(&d->pci, 0, 0, &d->container);
1135
1136 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
1137 intel_hda_response, intel_hda_xfer);
1138 }
1139
1140 static void intel_hda_exit(PCIDevice *pci)
1141 {
1142 IntelHDAState *d = INTEL_HDA(pci);
1143
1144 msi_uninit(&d->pci);
1145 }
1146
1147 static int intel_hda_post_load(void *opaque, int version)
1148 {
1149 IntelHDAState* d = opaque;
1150 int i;
1151
1152 dprint(d, 1, "%s\n", __func__);
1153 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1154 if (d->st[i].ctl & 0x02) {
1155 intel_hda_parse_bdl(d, &d->st[i]);
1156 }
1157 }
1158 intel_hda_update_irq(d);
1159 return 0;
1160 }
1161
1162 static const VMStateDescription vmstate_intel_hda_stream = {
1163 .name = "intel-hda-stream",
1164 .version_id = 1,
1165 .fields = (VMStateField[]) {
1166 VMSTATE_UINT32(ctl, IntelHDAStream),
1167 VMSTATE_UINT32(lpib, IntelHDAStream),
1168 VMSTATE_UINT32(cbl, IntelHDAStream),
1169 VMSTATE_UINT32(lvi, IntelHDAStream),
1170 VMSTATE_UINT32(fmt, IntelHDAStream),
1171 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1172 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1173 VMSTATE_END_OF_LIST()
1174 }
1175 };
1176
1177 static const VMStateDescription vmstate_intel_hda = {
1178 .name = "intel-hda",
1179 .version_id = 1,
1180 .post_load = intel_hda_post_load,
1181 .fields = (VMStateField[]) {
1182 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1183
1184 /* registers */
1185 VMSTATE_UINT32(g_ctl, IntelHDAState),
1186 VMSTATE_UINT32(wake_en, IntelHDAState),
1187 VMSTATE_UINT32(state_sts, IntelHDAState),
1188 VMSTATE_UINT32(int_ctl, IntelHDAState),
1189 VMSTATE_UINT32(int_sts, IntelHDAState),
1190 VMSTATE_UINT32(wall_clk, IntelHDAState),
1191 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1192 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1193 VMSTATE_UINT32(corb_rp, IntelHDAState),
1194 VMSTATE_UINT32(corb_wp, IntelHDAState),
1195 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1196 VMSTATE_UINT32(corb_sts, IntelHDAState),
1197 VMSTATE_UINT32(corb_size, IntelHDAState),
1198 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1199 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1200 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1201 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1202 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1203 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1204 VMSTATE_UINT32(rirb_size, IntelHDAState),
1205 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1206 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1207 VMSTATE_UINT32(icw, IntelHDAState),
1208 VMSTATE_UINT32(irr, IntelHDAState),
1209 VMSTATE_UINT32(ics, IntelHDAState),
1210 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1211 vmstate_intel_hda_stream,
1212 IntelHDAStream),
1213
1214 /* additional state info */
1215 VMSTATE_UINT32(rirb_count, IntelHDAState),
1216 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1217
1218 VMSTATE_END_OF_LIST()
1219 }
1220 };
1221
1222 static Property intel_hda_properties[] = {
1223 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1224 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO),
1225 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false),
1226 DEFINE_PROP_END_OF_LIST(),
1227 };
1228
1229 static void intel_hda_class_init(ObjectClass *klass, void *data)
1230 {
1231 DeviceClass *dc = DEVICE_CLASS(klass);
1232 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1233
1234 k->realize = intel_hda_realize;
1235 k->exit = intel_hda_exit;
1236 k->vendor_id = PCI_VENDOR_ID_INTEL;
1237 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
1238 dc->reset = intel_hda_reset;
1239 dc->vmsd = &vmstate_intel_hda;
1240 device_class_set_props(dc, intel_hda_properties);
1241 }
1242
1243 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
1244 {
1245 DeviceClass *dc = DEVICE_CLASS(klass);
1246 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1247
1248 k->device_id = 0x2668;
1249 k->revision = 1;
1250 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1251 dc->desc = "Intel HD Audio Controller (ich6)";
1252 }
1253
1254 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data)
1255 {
1256 DeviceClass *dc = DEVICE_CLASS(klass);
1257 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1258
1259 k->device_id = 0x293e;
1260 k->revision = 3;
1261 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1262 dc->desc = "Intel HD Audio Controller (ich9)";
1263 }
1264
1265 static const TypeInfo intel_hda_info = {
1266 .name = TYPE_INTEL_HDA_GENERIC,
1267 .parent = TYPE_PCI_DEVICE,
1268 .instance_size = sizeof(IntelHDAState),
1269 .class_init = intel_hda_class_init,
1270 .abstract = true,
1271 .interfaces = (InterfaceInfo[]) {
1272 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1273 { },
1274 },
1275 };
1276
1277 static const TypeInfo intel_hda_info_ich6 = {
1278 .name = "intel-hda",
1279 .parent = TYPE_INTEL_HDA_GENERIC,
1280 .class_init = intel_hda_class_init_ich6,
1281 };
1282
1283 static const TypeInfo intel_hda_info_ich9 = {
1284 .name = "ich9-intel-hda",
1285 .parent = TYPE_INTEL_HDA_GENERIC,
1286 .class_init = intel_hda_class_init_ich9,
1287 };
1288
1289 static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1290 {
1291 DeviceClass *k = DEVICE_CLASS(klass);
1292 k->realize = hda_codec_dev_realize;
1293 k->unrealize = hda_codec_dev_unrealize;
1294 set_bit(DEVICE_CATEGORY_SOUND, k->categories);
1295 k->bus_type = TYPE_HDA_BUS;
1296 device_class_set_props(k, hda_props);
1297 }
1298
1299 static const TypeInfo hda_codec_device_type_info = {
1300 .name = TYPE_HDA_CODEC_DEVICE,
1301 .parent = TYPE_DEVICE,
1302 .instance_size = sizeof(HDACodecDevice),
1303 .abstract = true,
1304 .class_size = sizeof(HDACodecDeviceClass),
1305 .class_init = hda_codec_device_class_init,
1306 };
1307
1308 /*
1309 * create intel hda controller with codec attached to it,
1310 * so '-soundhw hda' works.
1311 */
1312 static int intel_hda_and_codec_init(PCIBus *bus, const char *audiodev)
1313 {
1314 DeviceState *controller;
1315 BusState *hdabus;
1316 DeviceState *codec;
1317
1318 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
1319 hdabus = QLIST_FIRST(&controller->child_bus);
1320 codec = qdev_new("hda-duplex");
1321 qdev_prop_set_string(codec, "audiodev", audiodev);
1322 qdev_realize_and_unref(codec, hdabus, &error_fatal);
1323 return 0;
1324 }
1325
1326 static void intel_hda_register_types(void)
1327 {
1328 type_register_static(&hda_codec_bus_info);
1329 type_register_static(&intel_hda_info);
1330 type_register_static(&intel_hda_info_ich6);
1331 type_register_static(&intel_hda_info_ich9);
1332 type_register_static(&hda_codec_device_type_info);
1333 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init);
1334 }
1335
1336 type_init(intel_hda_register_types)
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