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1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "qemu/osdep.h"
31 #include "hw/block/fdc.h"
32 #include "qapi/error.h"
33 #include "qemu/error-report.h"
34 #include "qemu/timer.h"
35 #include "hw/irq.h"
36 #include "hw/isa/isa.h"
37 #include "hw/sysbus.h"
38 #include "migration/vmstate.h"
39 #include "hw/block/block.h"
40 #include "sysemu/block-backend.h"
41 #include "sysemu/blockdev.h"
42 #include "sysemu/sysemu.h"
43 #include "qemu/log.h"
44 #include "qemu/module.h"
45 #include "trace.h"
46
47 /********************************************************/
48 /* debug Floppy devices */
49
50 #define DEBUG_FLOPPY 0
51
52 #define FLOPPY_DPRINTF(fmt, ...) \
53 do { \
54 if (DEBUG_FLOPPY) { \
55 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \
56 } \
57 } while (0)
58
59
60 /********************************************************/
61 /* qdev floppy bus */
62
63 #define TYPE_FLOPPY_BUS "floppy-bus"
64 #define FLOPPY_BUS(obj) OBJECT_CHECK(FloppyBus, (obj), TYPE_FLOPPY_BUS)
65
66 typedef struct FDCtrl FDCtrl;
67 typedef struct FDrive FDrive;
68 static FDrive *get_drv(FDCtrl *fdctrl, int unit);
69
70 typedef struct FloppyBus {
71 BusState bus;
72 FDCtrl *fdc;
73 } FloppyBus;
74
75 static const TypeInfo floppy_bus_info = {
76 .name = TYPE_FLOPPY_BUS,
77 .parent = TYPE_BUS,
78 .instance_size = sizeof(FloppyBus),
79 };
80
81 static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev)
82 {
83 qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
84 bus->fdc = fdc;
85 }
86
87
88 /********************************************************/
89 /* Floppy drive emulation */
90
91 typedef enum FDriveRate {
92 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
93 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
94 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
95 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
96 } FDriveRate;
97
98 typedef enum FDriveSize {
99 FDRIVE_SIZE_UNKNOWN,
100 FDRIVE_SIZE_350,
101 FDRIVE_SIZE_525,
102 } FDriveSize;
103
104 typedef struct FDFormat {
105 FloppyDriveType drive;
106 uint8_t last_sect;
107 uint8_t max_track;
108 uint8_t max_head;
109 FDriveRate rate;
110 } FDFormat;
111
112 /* In many cases, the total sector size of a format is enough to uniquely
113 * identify it. However, there are some total sector collisions between
114 * formats of different physical size, and these are noted below by
115 * highlighting the total sector size for entries with collisions. */
116 static const FDFormat fd_formats[] = {
117 /* First entry is default format */
118 /* 1.44 MB 3"1/2 floppy disks */
119 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */
120 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */
121 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
122 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
123 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
124 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
125 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
126 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
127 /* 2.88 MB 3"1/2 floppy disks */
128 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
129 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
130 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
131 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
132 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
133 /* 720 kB 3"1/2 floppy disks */
134 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */
135 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
136 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
137 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
138 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
139 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
140 /* 1.2 MB 5"1/4 floppy disks */
141 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
142 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */
143 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
144 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
145 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */
146 /* 720 kB 5"1/4 floppy disks */
147 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */
148 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
149 /* 360 kB 5"1/4 floppy disks */
150 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */
151 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
152 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
153 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
154 /* 320 kB 5"1/4 floppy disks */
155 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
156 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
157 /* 360 kB must match 5"1/4 better than 3"1/2... */
158 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */
159 /* end */
160 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
161 };
162
163 static FDriveSize drive_size(FloppyDriveType drive)
164 {
165 switch (drive) {
166 case FLOPPY_DRIVE_TYPE_120:
167 return FDRIVE_SIZE_525;
168 case FLOPPY_DRIVE_TYPE_144:
169 case FLOPPY_DRIVE_TYPE_288:
170 return FDRIVE_SIZE_350;
171 default:
172 return FDRIVE_SIZE_UNKNOWN;
173 }
174 }
175
176 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
177 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
178
179 /* Will always be a fixed parameter for us */
180 #define FD_SECTOR_LEN 512
181 #define FD_SECTOR_SC 2 /* Sector size code */
182 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
183
184 /* Floppy disk drive emulation */
185 typedef enum FDiskFlags {
186 FDISK_DBL_SIDES = 0x01,
187 } FDiskFlags;
188
189 struct FDrive {
190 FDCtrl *fdctrl;
191 BlockBackend *blk;
192 BlockConf *conf;
193 /* Drive status */
194 FloppyDriveType drive; /* CMOS drive type */
195 uint8_t perpendicular; /* 2.88 MB access mode */
196 /* Position */
197 uint8_t head;
198 uint8_t track;
199 uint8_t sect;
200 /* Media */
201 FloppyDriveType disk; /* Current disk type */
202 FDiskFlags flags;
203 uint8_t last_sect; /* Nb sector per track */
204 uint8_t max_track; /* Nb of tracks */
205 uint16_t bps; /* Bytes per sector */
206 uint8_t ro; /* Is read-only */
207 uint8_t media_changed; /* Is media changed */
208 uint8_t media_rate; /* Data rate of medium */
209
210 bool media_validated; /* Have we validated the media? */
211 };
212
213
214 static FloppyDriveType get_fallback_drive_type(FDrive *drv);
215
216 /* Hack: FD_SEEK is expected to work on empty drives. However, QEMU
217 * currently goes through some pains to keep seeks within the bounds
218 * established by last_sect and max_track. Correcting this is difficult,
219 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel.
220 *
221 * For now: allow empty drives to have large bounds so we can seek around,
222 * with the understanding that when a diskette is inserted, the bounds will
223 * properly tighten to match the geometry of that inserted medium.
224 */
225 static void fd_empty_seek_hack(FDrive *drv)
226 {
227 drv->last_sect = 0xFF;
228 drv->max_track = 0xFF;
229 }
230
231 static void fd_init(FDrive *drv)
232 {
233 /* Drive */
234 drv->perpendicular = 0;
235 /* Disk */
236 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
237 drv->last_sect = 0;
238 drv->max_track = 0;
239 drv->ro = true;
240 drv->media_changed = 1;
241 }
242
243 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
244
245 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
246 uint8_t last_sect, uint8_t num_sides)
247 {
248 return (((track * num_sides) + head) * last_sect) + sect - 1;
249 }
250
251 /* Returns current position, in sectors, for given drive */
252 static int fd_sector(FDrive *drv)
253 {
254 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
255 NUM_SIDES(drv));
256 }
257
258 /* Returns current position, in bytes, for given drive */
259 static int fd_offset(FDrive *drv)
260 {
261 g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS);
262 return fd_sector(drv) << BDRV_SECTOR_BITS;
263 }
264
265 /* Seek to a new position:
266 * returns 0 if already on right track
267 * returns 1 if track changed
268 * returns 2 if track is invalid
269 * returns 3 if sector is invalid
270 * returns 4 if seek is disabled
271 */
272 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
273 int enable_seek)
274 {
275 uint32_t sector;
276 int ret;
277
278 if (track > drv->max_track ||
279 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
280 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
281 head, track, sect, 1,
282 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
283 drv->max_track, drv->last_sect);
284 return 2;
285 }
286 if (sect > drv->last_sect) {
287 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
288 head, track, sect, 1,
289 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
290 drv->max_track, drv->last_sect);
291 return 3;
292 }
293 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
294 ret = 0;
295 if (sector != fd_sector(drv)) {
296 #if 0
297 if (!enable_seek) {
298 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
299 " (max=%d %02x %02x)\n",
300 head, track, sect, 1, drv->max_track,
301 drv->last_sect);
302 return 4;
303 }
304 #endif
305 drv->head = head;
306 if (drv->track != track) {
307 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
308 drv->media_changed = 0;
309 }
310 ret = 1;
311 }
312 drv->track = track;
313 drv->sect = sect;
314 }
315
316 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
317 ret = 2;
318 }
319
320 return ret;
321 }
322
323 /* Set drive back to track 0 */
324 static void fd_recalibrate(FDrive *drv)
325 {
326 FLOPPY_DPRINTF("recalibrate\n");
327 fd_seek(drv, 0, 0, 1, 1);
328 }
329
330 /**
331 * Determine geometry based on inserted diskette.
332 * Will not operate on an empty drive.
333 *
334 * @return: 0 on success, -1 if the drive is empty.
335 */
336 static int pick_geometry(FDrive *drv)
337 {
338 BlockBackend *blk = drv->blk;
339 const FDFormat *parse;
340 uint64_t nb_sectors, size;
341 int i;
342 int match, size_match, type_match;
343 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO;
344
345 /* We can only pick a geometry if we have a diskette. */
346 if (!drv->blk || !blk_is_inserted(drv->blk) ||
347 drv->drive == FLOPPY_DRIVE_TYPE_NONE)
348 {
349 return -1;
350 }
351
352 /* We need to determine the likely geometry of the inserted medium.
353 * In order of preference, we look for:
354 * (1) The same drive type and number of sectors,
355 * (2) The same diskette size and number of sectors,
356 * (3) The same drive type.
357 *
358 * In all cases, matches that occur higher in the drive table will take
359 * precedence over matches that occur later in the table.
360 */
361 blk_get_geometry(blk, &nb_sectors);
362 match = size_match = type_match = -1;
363 for (i = 0; ; i++) {
364 parse = &fd_formats[i];
365 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
366 break;
367 }
368 size = (parse->max_head + 1) * parse->max_track * parse->last_sect;
369 if (nb_sectors == size) {
370 if (magic || parse->drive == drv->drive) {
371 /* (1) perfect match -- nb_sectors and drive type */
372 goto out;
373 } else if (drive_size(parse->drive) == drive_size(drv->drive)) {
374 /* (2) size match -- nb_sectors and physical medium size */
375 match = (match == -1) ? i : match;
376 } else {
377 /* This is suspicious -- Did the user misconfigure? */
378 size_match = (size_match == -1) ? i : size_match;
379 }
380 } else if (type_match == -1) {
381 if ((parse->drive == drv->drive) ||
382 (magic && (parse->drive == get_fallback_drive_type(drv)))) {
383 /* (3) type match -- nb_sectors mismatch, but matches the type
384 * specified explicitly by the user, or matches the fallback
385 * default type when using the drive autodetect mechanism */
386 type_match = i;
387 }
388 }
389 }
390
391 /* No exact match found */
392 if (match == -1) {
393 if (size_match != -1) {
394 parse = &fd_formats[size_match];
395 FLOPPY_DPRINTF("User requested floppy drive type '%s', "
396 "but inserted medium appears to be a "
397 "%"PRId64" sector '%s' type\n",
398 FloppyDriveType_str(drv->drive),
399 nb_sectors,
400 FloppyDriveType_str(parse->drive));
401 }
402 assert(type_match != -1 && "misconfigured fd_format");
403 match = type_match;
404 }
405 parse = &(fd_formats[match]);
406
407 out:
408 if (parse->max_head == 0) {
409 drv->flags &= ~FDISK_DBL_SIDES;
410 } else {
411 drv->flags |= FDISK_DBL_SIDES;
412 }
413 drv->max_track = parse->max_track;
414 drv->last_sect = parse->last_sect;
415 drv->disk = parse->drive;
416 drv->media_rate = parse->rate;
417 return 0;
418 }
419
420 static void pick_drive_type(FDrive *drv)
421 {
422 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
423 return;
424 }
425
426 if (pick_geometry(drv) == 0) {
427 drv->drive = drv->disk;
428 } else {
429 drv->drive = get_fallback_drive_type(drv);
430 }
431
432 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
433 }
434
435 /* Revalidate a disk drive after a disk change */
436 static void fd_revalidate(FDrive *drv)
437 {
438 int rc;
439
440 FLOPPY_DPRINTF("revalidate\n");
441 if (drv->blk != NULL) {
442 drv->ro = blk_is_read_only(drv->blk);
443 if (!blk_is_inserted(drv->blk)) {
444 FLOPPY_DPRINTF("No disk in drive\n");
445 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
446 fd_empty_seek_hack(drv);
447 } else if (!drv->media_validated) {
448 rc = pick_geometry(drv);
449 if (rc) {
450 FLOPPY_DPRINTF("Could not validate floppy drive media");
451 } else {
452 drv->media_validated = true;
453 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
454 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
455 drv->max_track, drv->last_sect,
456 drv->ro ? "ro" : "rw");
457 }
458 }
459 } else {
460 FLOPPY_DPRINTF("No drive connected\n");
461 drv->last_sect = 0;
462 drv->max_track = 0;
463 drv->flags &= ~FDISK_DBL_SIDES;
464 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
465 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
466 }
467 }
468
469 static void fd_change_cb(void *opaque, bool load, Error **errp)
470 {
471 FDrive *drive = opaque;
472
473 if (!load) {
474 blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort);
475 } else {
476 if (!blkconf_apply_backend_options(drive->conf,
477 blk_is_read_only(drive->blk), false,
478 errp)) {
479 return;
480 }
481 }
482
483 drive->media_changed = 1;
484 drive->media_validated = false;
485 fd_revalidate(drive);
486 }
487
488 static const BlockDevOps fd_block_ops = {
489 .change_media_cb = fd_change_cb,
490 };
491
492
493 #define TYPE_FLOPPY_DRIVE "floppy"
494 #define FLOPPY_DRIVE(obj) \
495 OBJECT_CHECK(FloppyDrive, (obj), TYPE_FLOPPY_DRIVE)
496
497 typedef struct FloppyDrive {
498 DeviceState qdev;
499 uint32_t unit;
500 BlockConf conf;
501 FloppyDriveType type;
502 } FloppyDrive;
503
504 static Property floppy_drive_properties[] = {
505 DEFINE_PROP_UINT32("unit", FloppyDrive, unit, -1),
506 DEFINE_BLOCK_PROPERTIES(FloppyDrive, conf),
507 DEFINE_PROP_SIGNED("drive-type", FloppyDrive, type,
508 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
509 FloppyDriveType),
510 DEFINE_PROP_END_OF_LIST(),
511 };
512
513 static void floppy_drive_realize(DeviceState *qdev, Error **errp)
514 {
515 FloppyDrive *dev = FLOPPY_DRIVE(qdev);
516 FloppyBus *bus = FLOPPY_BUS(qdev->parent_bus);
517 FDrive *drive;
518 bool read_only;
519 int ret;
520
521 if (dev->unit == -1) {
522 for (dev->unit = 0; dev->unit < MAX_FD; dev->unit++) {
523 drive = get_drv(bus->fdc, dev->unit);
524 if (!drive->blk) {
525 break;
526 }
527 }
528 }
529
530 if (dev->unit >= MAX_FD) {
531 error_setg(errp, "Can't create floppy unit %d, bus supports "
532 "only %d units", dev->unit, MAX_FD);
533 return;
534 }
535
536 drive = get_drv(bus->fdc, dev->unit);
537 if (drive->blk) {
538 error_setg(errp, "Floppy unit %d is in use", dev->unit);
539 return;
540 }
541
542 if (!dev->conf.blk) {
543 /* Anonymous BlockBackend for an empty drive */
544 dev->conf.blk = blk_new(qemu_get_aio_context(), 0, BLK_PERM_ALL);
545 ret = blk_attach_dev(dev->conf.blk, qdev);
546 assert(ret == 0);
547
548 /* Don't take write permissions on an empty drive to allow attaching a
549 * read-only node later */
550 read_only = true;
551 } else {
552 read_only = !blk_bs(dev->conf.blk) || blk_is_read_only(dev->conf.blk);
553 }
554
555 blkconf_blocksizes(&dev->conf);
556 if (dev->conf.logical_block_size != 512 ||
557 dev->conf.physical_block_size != 512)
558 {
559 error_setg(errp, "Physical and logical block size must "
560 "be 512 for floppy");
561 return;
562 }
563
564 /* rerror/werror aren't supported by fdc and therefore not even registered
565 * with qdev. So set the defaults manually before they are used in
566 * blkconf_apply_backend_options(). */
567 dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO;
568 dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO;
569
570 if (!blkconf_apply_backend_options(&dev->conf, read_only, false, errp)) {
571 return;
572 }
573
574 /* 'enospc' is the default for -drive, 'report' is what blk_new() gives us
575 * for empty drives. */
576 if (blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC &&
577 blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_REPORT) {
578 error_setg(errp, "fdc doesn't support drive option werror");
579 return;
580 }
581 if (blk_get_on_error(dev->conf.blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
582 error_setg(errp, "fdc doesn't support drive option rerror");
583 return;
584 }
585
586 drive->conf = &dev->conf;
587 drive->blk = dev->conf.blk;
588 drive->fdctrl = bus->fdc;
589
590 fd_init(drive);
591 blk_set_dev_ops(drive->blk, &fd_block_ops, drive);
592
593 /* Keep 'type' qdev property and FDrive->drive in sync */
594 drive->drive = dev->type;
595 pick_drive_type(drive);
596 dev->type = drive->drive;
597
598 fd_revalidate(drive);
599 }
600
601 static void floppy_drive_class_init(ObjectClass *klass, void *data)
602 {
603 DeviceClass *k = DEVICE_CLASS(klass);
604 k->realize = floppy_drive_realize;
605 set_bit(DEVICE_CATEGORY_STORAGE, k->categories);
606 k->bus_type = TYPE_FLOPPY_BUS;
607 k->props = floppy_drive_properties;
608 k->desc = "virtual floppy drive";
609 }
610
611 static const TypeInfo floppy_drive_info = {
612 .name = TYPE_FLOPPY_DRIVE,
613 .parent = TYPE_DEVICE,
614 .instance_size = sizeof(FloppyDrive),
615 .class_init = floppy_drive_class_init,
616 };
617
618 /********************************************************/
619 /* Intel 82078 floppy disk controller emulation */
620
621 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
622 static void fdctrl_to_command_phase(FDCtrl *fdctrl);
623 static int fdctrl_transfer_handler (void *opaque, int nchan,
624 int dma_pos, int dma_len);
625 static void fdctrl_raise_irq(FDCtrl *fdctrl);
626 static FDrive *get_cur_drv(FDCtrl *fdctrl);
627
628 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
629 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
630 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
631 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
632 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
633 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
634 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
635 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
636 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
637 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
638 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
639 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
640
641 enum {
642 FD_DIR_WRITE = 0,
643 FD_DIR_READ = 1,
644 FD_DIR_SCANE = 2,
645 FD_DIR_SCANL = 3,
646 FD_DIR_SCANH = 4,
647 FD_DIR_VERIFY = 5,
648 };
649
650 enum {
651 FD_STATE_MULTI = 0x01, /* multi track flag */
652 FD_STATE_FORMAT = 0x02, /* format flag */
653 };
654
655 enum {
656 FD_REG_SRA = 0x00,
657 FD_REG_SRB = 0x01,
658 FD_REG_DOR = 0x02,
659 FD_REG_TDR = 0x03,
660 FD_REG_MSR = 0x04,
661 FD_REG_DSR = 0x04,
662 FD_REG_FIFO = 0x05,
663 FD_REG_DIR = 0x07,
664 FD_REG_CCR = 0x07,
665 };
666
667 enum {
668 FD_CMD_READ_TRACK = 0x02,
669 FD_CMD_SPECIFY = 0x03,
670 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
671 FD_CMD_WRITE = 0x05,
672 FD_CMD_READ = 0x06,
673 FD_CMD_RECALIBRATE = 0x07,
674 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
675 FD_CMD_WRITE_DELETED = 0x09,
676 FD_CMD_READ_ID = 0x0a,
677 FD_CMD_READ_DELETED = 0x0c,
678 FD_CMD_FORMAT_TRACK = 0x0d,
679 FD_CMD_DUMPREG = 0x0e,
680 FD_CMD_SEEK = 0x0f,
681 FD_CMD_VERSION = 0x10,
682 FD_CMD_SCAN_EQUAL = 0x11,
683 FD_CMD_PERPENDICULAR_MODE = 0x12,
684 FD_CMD_CONFIGURE = 0x13,
685 FD_CMD_LOCK = 0x14,
686 FD_CMD_VERIFY = 0x16,
687 FD_CMD_POWERDOWN_MODE = 0x17,
688 FD_CMD_PART_ID = 0x18,
689 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
690 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
691 FD_CMD_SAVE = 0x2e,
692 FD_CMD_OPTION = 0x33,
693 FD_CMD_RESTORE = 0x4e,
694 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
695 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
696 FD_CMD_FORMAT_AND_WRITE = 0xcd,
697 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
698 };
699
700 enum {
701 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
702 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
703 FD_CONFIG_POLL = 0x10, /* Poll enabled */
704 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
705 FD_CONFIG_EIS = 0x40, /* No implied seeks */
706 };
707
708 enum {
709 FD_SR0_DS0 = 0x01,
710 FD_SR0_DS1 = 0x02,
711 FD_SR0_HEAD = 0x04,
712 FD_SR0_EQPMT = 0x10,
713 FD_SR0_SEEK = 0x20,
714 FD_SR0_ABNTERM = 0x40,
715 FD_SR0_INVCMD = 0x80,
716 FD_SR0_RDYCHG = 0xc0,
717 };
718
719 enum {
720 FD_SR1_MA = 0x01, /* Missing address mark */
721 FD_SR1_NW = 0x02, /* Not writable */
722 FD_SR1_EC = 0x80, /* End of cylinder */
723 };
724
725 enum {
726 FD_SR2_SNS = 0x04, /* Scan not satisfied */
727 FD_SR2_SEH = 0x08, /* Scan equal hit */
728 };
729
730 enum {
731 FD_SRA_DIR = 0x01,
732 FD_SRA_nWP = 0x02,
733 FD_SRA_nINDX = 0x04,
734 FD_SRA_HDSEL = 0x08,
735 FD_SRA_nTRK0 = 0x10,
736 FD_SRA_STEP = 0x20,
737 FD_SRA_nDRV2 = 0x40,
738 FD_SRA_INTPEND = 0x80,
739 };
740
741 enum {
742 FD_SRB_MTR0 = 0x01,
743 FD_SRB_MTR1 = 0x02,
744 FD_SRB_WGATE = 0x04,
745 FD_SRB_RDATA = 0x08,
746 FD_SRB_WDATA = 0x10,
747 FD_SRB_DR0 = 0x20,
748 };
749
750 enum {
751 #if MAX_FD == 4
752 FD_DOR_SELMASK = 0x03,
753 #else
754 FD_DOR_SELMASK = 0x01,
755 #endif
756 FD_DOR_nRESET = 0x04,
757 FD_DOR_DMAEN = 0x08,
758 FD_DOR_MOTEN0 = 0x10,
759 FD_DOR_MOTEN1 = 0x20,
760 FD_DOR_MOTEN2 = 0x40,
761 FD_DOR_MOTEN3 = 0x80,
762 };
763
764 enum {
765 #if MAX_FD == 4
766 FD_TDR_BOOTSEL = 0x0c,
767 #else
768 FD_TDR_BOOTSEL = 0x04,
769 #endif
770 };
771
772 enum {
773 FD_DSR_DRATEMASK= 0x03,
774 FD_DSR_PWRDOWN = 0x40,
775 FD_DSR_SWRESET = 0x80,
776 };
777
778 enum {
779 FD_MSR_DRV0BUSY = 0x01,
780 FD_MSR_DRV1BUSY = 0x02,
781 FD_MSR_DRV2BUSY = 0x04,
782 FD_MSR_DRV3BUSY = 0x08,
783 FD_MSR_CMDBUSY = 0x10,
784 FD_MSR_NONDMA = 0x20,
785 FD_MSR_DIO = 0x40,
786 FD_MSR_RQM = 0x80,
787 };
788
789 enum {
790 FD_DIR_DSKCHG = 0x80,
791 };
792
793 /*
794 * See chapter 5.0 "Controller phases" of the spec:
795 *
796 * Command phase:
797 * The host writes a command and its parameters into the FIFO. The command
798 * phase is completed when all parameters for the command have been supplied,
799 * and execution phase is entered.
800 *
801 * Execution phase:
802 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
803 * contains the payload now, otherwise it's unused. When all bytes of the
804 * required data have been transferred, the state is switched to either result
805 * phase (if the command produces status bytes) or directly back into the
806 * command phase for the next command.
807 *
808 * Result phase:
809 * The host reads out the FIFO, which contains one or more result bytes now.
810 */
811 enum {
812 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
813 FD_PHASE_RECONSTRUCT = 0,
814
815 FD_PHASE_COMMAND = 1,
816 FD_PHASE_EXECUTION = 2,
817 FD_PHASE_RESULT = 3,
818 };
819
820 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
821 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
822
823 struct FDCtrl {
824 MemoryRegion iomem;
825 qemu_irq irq;
826 /* Controller state */
827 QEMUTimer *result_timer;
828 int dma_chann;
829 uint8_t phase;
830 IsaDma *dma;
831 /* Controller's identification */
832 uint8_t version;
833 /* HW */
834 uint8_t sra;
835 uint8_t srb;
836 uint8_t dor;
837 uint8_t dor_vmstate; /* only used as temp during vmstate */
838 uint8_t tdr;
839 uint8_t dsr;
840 uint8_t msr;
841 uint8_t cur_drv;
842 uint8_t status0;
843 uint8_t status1;
844 uint8_t status2;
845 /* Command FIFO */
846 uint8_t *fifo;
847 int32_t fifo_size;
848 uint32_t data_pos;
849 uint32_t data_len;
850 uint8_t data_state;
851 uint8_t data_dir;
852 uint8_t eot; /* last wanted sector */
853 /* States kept only to be returned back */
854 /* precompensation */
855 uint8_t precomp_trk;
856 uint8_t config;
857 uint8_t lock;
858 /* Power down config (also with status regB access mode */
859 uint8_t pwrd;
860 /* Floppy drives */
861 FloppyBus bus;
862 uint8_t num_floppies;
863 FDrive drives[MAX_FD];
864 struct {
865 BlockBackend *blk;
866 FloppyDriveType type;
867 } qdev_for_drives[MAX_FD];
868 int reset_sensei;
869 uint32_t check_media_rate;
870 FloppyDriveType fallback; /* type=auto failure fallback */
871 /* Timers state */
872 uint8_t timer0;
873 uint8_t timer1;
874 PortioList portio_list;
875 };
876
877 static FloppyDriveType get_fallback_drive_type(FDrive *drv)
878 {
879 return drv->fdctrl->fallback;
880 }
881
882 #define TYPE_SYSBUS_FDC "base-sysbus-fdc"
883 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
884
885 typedef struct FDCtrlSysBus {
886 /*< private >*/
887 SysBusDevice parent_obj;
888 /*< public >*/
889
890 struct FDCtrl state;
891 } FDCtrlSysBus;
892
893 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
894
895 typedef struct FDCtrlISABus {
896 ISADevice parent_obj;
897
898 uint32_t iobase;
899 uint32_t irq;
900 uint32_t dma;
901 struct FDCtrl state;
902 int32_t bootindexA;
903 int32_t bootindexB;
904 } FDCtrlISABus;
905
906 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
907 {
908 FDCtrl *fdctrl = opaque;
909 uint32_t retval;
910
911 reg &= 7;
912 switch (reg) {
913 case FD_REG_SRA:
914 retval = fdctrl_read_statusA(fdctrl);
915 break;
916 case FD_REG_SRB:
917 retval = fdctrl_read_statusB(fdctrl);
918 break;
919 case FD_REG_DOR:
920 retval = fdctrl_read_dor(fdctrl);
921 break;
922 case FD_REG_TDR:
923 retval = fdctrl_read_tape(fdctrl);
924 break;
925 case FD_REG_MSR:
926 retval = fdctrl_read_main_status(fdctrl);
927 break;
928 case FD_REG_FIFO:
929 retval = fdctrl_read_data(fdctrl);
930 break;
931 case FD_REG_DIR:
932 retval = fdctrl_read_dir(fdctrl);
933 break;
934 default:
935 retval = (uint32_t)(-1);
936 break;
937 }
938 trace_fdc_ioport_read(reg, retval);
939
940 return retval;
941 }
942
943 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
944 {
945 FDCtrl *fdctrl = opaque;
946
947 reg &= 7;
948 trace_fdc_ioport_write(reg, value);
949 switch (reg) {
950 case FD_REG_DOR:
951 fdctrl_write_dor(fdctrl, value);
952 break;
953 case FD_REG_TDR:
954 fdctrl_write_tape(fdctrl, value);
955 break;
956 case FD_REG_DSR:
957 fdctrl_write_rate(fdctrl, value);
958 break;
959 case FD_REG_FIFO:
960 fdctrl_write_data(fdctrl, value);
961 break;
962 case FD_REG_CCR:
963 fdctrl_write_ccr(fdctrl, value);
964 break;
965 default:
966 break;
967 }
968 }
969
970 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
971 unsigned ize)
972 {
973 return fdctrl_read(opaque, (uint32_t)reg);
974 }
975
976 static void fdctrl_write_mem (void *opaque, hwaddr reg,
977 uint64_t value, unsigned size)
978 {
979 fdctrl_write(opaque, (uint32_t)reg, value);
980 }
981
982 static const MemoryRegionOps fdctrl_mem_ops = {
983 .read = fdctrl_read_mem,
984 .write = fdctrl_write_mem,
985 .endianness = DEVICE_NATIVE_ENDIAN,
986 };
987
988 static const MemoryRegionOps fdctrl_mem_strict_ops = {
989 .read = fdctrl_read_mem,
990 .write = fdctrl_write_mem,
991 .endianness = DEVICE_NATIVE_ENDIAN,
992 .valid = {
993 .min_access_size = 1,
994 .max_access_size = 1,
995 },
996 };
997
998 static bool fdrive_media_changed_needed(void *opaque)
999 {
1000 FDrive *drive = opaque;
1001
1002 return (drive->blk != NULL && drive->media_changed != 1);
1003 }
1004
1005 static const VMStateDescription vmstate_fdrive_media_changed = {
1006 .name = "fdrive/media_changed",
1007 .version_id = 1,
1008 .minimum_version_id = 1,
1009 .needed = fdrive_media_changed_needed,
1010 .fields = (VMStateField[]) {
1011 VMSTATE_UINT8(media_changed, FDrive),
1012 VMSTATE_END_OF_LIST()
1013 }
1014 };
1015
1016 static bool fdrive_media_rate_needed(void *opaque)
1017 {
1018 FDrive *drive = opaque;
1019
1020 return drive->fdctrl->check_media_rate;
1021 }
1022
1023 static const VMStateDescription vmstate_fdrive_media_rate = {
1024 .name = "fdrive/media_rate",
1025 .version_id = 1,
1026 .minimum_version_id = 1,
1027 .needed = fdrive_media_rate_needed,
1028 .fields = (VMStateField[]) {
1029 VMSTATE_UINT8(media_rate, FDrive),
1030 VMSTATE_END_OF_LIST()
1031 }
1032 };
1033
1034 static bool fdrive_perpendicular_needed(void *opaque)
1035 {
1036 FDrive *drive = opaque;
1037
1038 return drive->perpendicular != 0;
1039 }
1040
1041 static const VMStateDescription vmstate_fdrive_perpendicular = {
1042 .name = "fdrive/perpendicular",
1043 .version_id = 1,
1044 .minimum_version_id = 1,
1045 .needed = fdrive_perpendicular_needed,
1046 .fields = (VMStateField[]) {
1047 VMSTATE_UINT8(perpendicular, FDrive),
1048 VMSTATE_END_OF_LIST()
1049 }
1050 };
1051
1052 static int fdrive_post_load(void *opaque, int version_id)
1053 {
1054 fd_revalidate(opaque);
1055 return 0;
1056 }
1057
1058 static const VMStateDescription vmstate_fdrive = {
1059 .name = "fdrive",
1060 .version_id = 1,
1061 .minimum_version_id = 1,
1062 .post_load = fdrive_post_load,
1063 .fields = (VMStateField[]) {
1064 VMSTATE_UINT8(head, FDrive),
1065 VMSTATE_UINT8(track, FDrive),
1066 VMSTATE_UINT8(sect, FDrive),
1067 VMSTATE_END_OF_LIST()
1068 },
1069 .subsections = (const VMStateDescription*[]) {
1070 &vmstate_fdrive_media_changed,
1071 &vmstate_fdrive_media_rate,
1072 &vmstate_fdrive_perpendicular,
1073 NULL
1074 }
1075 };
1076
1077 /*
1078 * Reconstructs the phase from register values according to the logic that was
1079 * implemented in qemu 2.3. This is the default value that is used if the phase
1080 * subsection is not present on migration.
1081 *
1082 * Don't change this function to reflect newer qemu versions, it is part of
1083 * the migration ABI.
1084 */
1085 static int reconstruct_phase(FDCtrl *fdctrl)
1086 {
1087 if (fdctrl->msr & FD_MSR_NONDMA) {
1088 return FD_PHASE_EXECUTION;
1089 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
1090 /* qemu 2.3 disabled RQM only during DMA transfers */
1091 return FD_PHASE_EXECUTION;
1092 } else if (fdctrl->msr & FD_MSR_DIO) {
1093 return FD_PHASE_RESULT;
1094 } else {
1095 return FD_PHASE_COMMAND;
1096 }
1097 }
1098
1099 static int fdc_pre_save(void *opaque)
1100 {
1101 FDCtrl *s = opaque;
1102
1103 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
1104
1105 return 0;
1106 }
1107
1108 static int fdc_pre_load(void *opaque)
1109 {
1110 FDCtrl *s = opaque;
1111 s->phase = FD_PHASE_RECONSTRUCT;
1112 return 0;
1113 }
1114
1115 static int fdc_post_load(void *opaque, int version_id)
1116 {
1117 FDCtrl *s = opaque;
1118
1119 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
1120 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
1121
1122 if (s->phase == FD_PHASE_RECONSTRUCT) {
1123 s->phase = reconstruct_phase(s);
1124 }
1125
1126 return 0;
1127 }
1128
1129 static bool fdc_reset_sensei_needed(void *opaque)
1130 {
1131 FDCtrl *s = opaque;
1132
1133 return s->reset_sensei != 0;
1134 }
1135
1136 static const VMStateDescription vmstate_fdc_reset_sensei = {
1137 .name = "fdc/reset_sensei",
1138 .version_id = 1,
1139 .minimum_version_id = 1,
1140 .needed = fdc_reset_sensei_needed,
1141 .fields = (VMStateField[]) {
1142 VMSTATE_INT32(reset_sensei, FDCtrl),
1143 VMSTATE_END_OF_LIST()
1144 }
1145 };
1146
1147 static bool fdc_result_timer_needed(void *opaque)
1148 {
1149 FDCtrl *s = opaque;
1150
1151 return timer_pending(s->result_timer);
1152 }
1153
1154 static const VMStateDescription vmstate_fdc_result_timer = {
1155 .name = "fdc/result_timer",
1156 .version_id = 1,
1157 .minimum_version_id = 1,
1158 .needed = fdc_result_timer_needed,
1159 .fields = (VMStateField[]) {
1160 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
1161 VMSTATE_END_OF_LIST()
1162 }
1163 };
1164
1165 static bool fdc_phase_needed(void *opaque)
1166 {
1167 FDCtrl *fdctrl = opaque;
1168
1169 return reconstruct_phase(fdctrl) != fdctrl->phase;
1170 }
1171
1172 static const VMStateDescription vmstate_fdc_phase = {
1173 .name = "fdc/phase",
1174 .version_id = 1,
1175 .minimum_version_id = 1,
1176 .needed = fdc_phase_needed,
1177 .fields = (VMStateField[]) {
1178 VMSTATE_UINT8(phase, FDCtrl),
1179 VMSTATE_END_OF_LIST()
1180 }
1181 };
1182
1183 static const VMStateDescription vmstate_fdc = {
1184 .name = "fdc",
1185 .version_id = 2,
1186 .minimum_version_id = 2,
1187 .pre_save = fdc_pre_save,
1188 .pre_load = fdc_pre_load,
1189 .post_load = fdc_post_load,
1190 .fields = (VMStateField[]) {
1191 /* Controller State */
1192 VMSTATE_UINT8(sra, FDCtrl),
1193 VMSTATE_UINT8(srb, FDCtrl),
1194 VMSTATE_UINT8(dor_vmstate, FDCtrl),
1195 VMSTATE_UINT8(tdr, FDCtrl),
1196 VMSTATE_UINT8(dsr, FDCtrl),
1197 VMSTATE_UINT8(msr, FDCtrl),
1198 VMSTATE_UINT8(status0, FDCtrl),
1199 VMSTATE_UINT8(status1, FDCtrl),
1200 VMSTATE_UINT8(status2, FDCtrl),
1201 /* Command FIFO */
1202 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
1203 uint8_t),
1204 VMSTATE_UINT32(data_pos, FDCtrl),
1205 VMSTATE_UINT32(data_len, FDCtrl),
1206 VMSTATE_UINT8(data_state, FDCtrl),
1207 VMSTATE_UINT8(data_dir, FDCtrl),
1208 VMSTATE_UINT8(eot, FDCtrl),
1209 /* States kept only to be returned back */
1210 VMSTATE_UINT8(timer0, FDCtrl),
1211 VMSTATE_UINT8(timer1, FDCtrl),
1212 VMSTATE_UINT8(precomp_trk, FDCtrl),
1213 VMSTATE_UINT8(config, FDCtrl),
1214 VMSTATE_UINT8(lock, FDCtrl),
1215 VMSTATE_UINT8(pwrd, FDCtrl),
1216 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl, NULL),
1217 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
1218 vmstate_fdrive, FDrive),
1219 VMSTATE_END_OF_LIST()
1220 },
1221 .subsections = (const VMStateDescription*[]) {
1222 &vmstate_fdc_reset_sensei,
1223 &vmstate_fdc_result_timer,
1224 &vmstate_fdc_phase,
1225 NULL
1226 }
1227 };
1228
1229 static void fdctrl_external_reset_sysbus(DeviceState *d)
1230 {
1231 FDCtrlSysBus *sys = SYSBUS_FDC(d);
1232 FDCtrl *s = &sys->state;
1233
1234 fdctrl_reset(s, 0);
1235 }
1236
1237 static void fdctrl_external_reset_isa(DeviceState *d)
1238 {
1239 FDCtrlISABus *isa = ISA_FDC(d);
1240 FDCtrl *s = &isa->state;
1241
1242 fdctrl_reset(s, 0);
1243 }
1244
1245 static void fdctrl_handle_tc(void *opaque, int irq, int level)
1246 {
1247 //FDCtrl *s = opaque;
1248
1249 if (level) {
1250 // XXX
1251 FLOPPY_DPRINTF("TC pulsed\n");
1252 }
1253 }
1254
1255 /* Change IRQ state */
1256 static void fdctrl_reset_irq(FDCtrl *fdctrl)
1257 {
1258 fdctrl->status0 = 0;
1259 if (!(fdctrl->sra & FD_SRA_INTPEND))
1260 return;
1261 FLOPPY_DPRINTF("Reset interrupt\n");
1262 qemu_set_irq(fdctrl->irq, 0);
1263 fdctrl->sra &= ~FD_SRA_INTPEND;
1264 }
1265
1266 static void fdctrl_raise_irq(FDCtrl *fdctrl)
1267 {
1268 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1269 qemu_set_irq(fdctrl->irq, 1);
1270 fdctrl->sra |= FD_SRA_INTPEND;
1271 }
1272
1273 fdctrl->reset_sensei = 0;
1274 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
1275 }
1276
1277 /* Reset controller */
1278 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
1279 {
1280 int i;
1281
1282 FLOPPY_DPRINTF("reset controller\n");
1283 fdctrl_reset_irq(fdctrl);
1284 /* Initialise controller */
1285 fdctrl->sra = 0;
1286 fdctrl->srb = 0xc0;
1287 if (!fdctrl->drives[1].blk) {
1288 fdctrl->sra |= FD_SRA_nDRV2;
1289 }
1290 fdctrl->cur_drv = 0;
1291 fdctrl->dor = FD_DOR_nRESET;
1292 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
1293 fdctrl->msr = FD_MSR_RQM;
1294 fdctrl->reset_sensei = 0;
1295 timer_del(fdctrl->result_timer);
1296 /* FIFO state */
1297 fdctrl->data_pos = 0;
1298 fdctrl->data_len = 0;
1299 fdctrl->data_state = 0;
1300 fdctrl->data_dir = FD_DIR_WRITE;
1301 for (i = 0; i < MAX_FD; i++)
1302 fd_recalibrate(&fdctrl->drives[i]);
1303 fdctrl_to_command_phase(fdctrl);
1304 if (do_irq) {
1305 fdctrl->status0 |= FD_SR0_RDYCHG;
1306 fdctrl_raise_irq(fdctrl);
1307 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
1308 }
1309 }
1310
1311 static inline FDrive *drv0(FDCtrl *fdctrl)
1312 {
1313 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
1314 }
1315
1316 static inline FDrive *drv1(FDCtrl *fdctrl)
1317 {
1318 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1319 return &fdctrl->drives[1];
1320 else
1321 return &fdctrl->drives[0];
1322 }
1323
1324 #if MAX_FD == 4
1325 static inline FDrive *drv2(FDCtrl *fdctrl)
1326 {
1327 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1328 return &fdctrl->drives[2];
1329 else
1330 return &fdctrl->drives[1];
1331 }
1332
1333 static inline FDrive *drv3(FDCtrl *fdctrl)
1334 {
1335 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1336 return &fdctrl->drives[3];
1337 else
1338 return &fdctrl->drives[2];
1339 }
1340 #endif
1341
1342 static FDrive *get_drv(FDCtrl *fdctrl, int unit)
1343 {
1344 switch (unit) {
1345 case 0: return drv0(fdctrl);
1346 case 1: return drv1(fdctrl);
1347 #if MAX_FD == 4
1348 case 2: return drv2(fdctrl);
1349 case 3: return drv3(fdctrl);
1350 #endif
1351 default: return NULL;
1352 }
1353 }
1354
1355 static FDrive *get_cur_drv(FDCtrl *fdctrl)
1356 {
1357 return get_drv(fdctrl, fdctrl->cur_drv);
1358 }
1359
1360 /* Status A register : 0x00 (read-only) */
1361 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
1362 {
1363 uint32_t retval = fdctrl->sra;
1364
1365 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1366
1367 return retval;
1368 }
1369
1370 /* Status B register : 0x01 (read-only) */
1371 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
1372 {
1373 uint32_t retval = fdctrl->srb;
1374
1375 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1376
1377 return retval;
1378 }
1379
1380 /* Digital output register : 0x02 */
1381 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
1382 {
1383 uint32_t retval = fdctrl->dor;
1384
1385 /* Selected drive */
1386 retval |= fdctrl->cur_drv;
1387 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1388
1389 return retval;
1390 }
1391
1392 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
1393 {
1394 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
1395
1396 /* Motors */
1397 if (value & FD_DOR_MOTEN0)
1398 fdctrl->srb |= FD_SRB_MTR0;
1399 else
1400 fdctrl->srb &= ~FD_SRB_MTR0;
1401 if (value & FD_DOR_MOTEN1)
1402 fdctrl->srb |= FD_SRB_MTR1;
1403 else
1404 fdctrl->srb &= ~FD_SRB_MTR1;
1405
1406 /* Drive */
1407 if (value & 1)
1408 fdctrl->srb |= FD_SRB_DR0;
1409 else
1410 fdctrl->srb &= ~FD_SRB_DR0;
1411
1412 /* Reset */
1413 if (!(value & FD_DOR_nRESET)) {
1414 if (fdctrl->dor & FD_DOR_nRESET) {
1415 FLOPPY_DPRINTF("controller enter RESET state\n");
1416 }
1417 } else {
1418 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1419 FLOPPY_DPRINTF("controller out of RESET state\n");
1420 fdctrl_reset(fdctrl, 1);
1421 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1422 }
1423 }
1424 /* Selected drive */
1425 fdctrl->cur_drv = value & FD_DOR_SELMASK;
1426
1427 fdctrl->dor = value;
1428 }
1429
1430 /* Tape drive register : 0x03 */
1431 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
1432 {
1433 uint32_t retval = fdctrl->tdr;
1434
1435 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1436
1437 return retval;
1438 }
1439
1440 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
1441 {
1442 /* Reset mode */
1443 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1444 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1445 return;
1446 }
1447 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1448 /* Disk boot selection indicator */
1449 fdctrl->tdr = value & FD_TDR_BOOTSEL;
1450 /* Tape indicators: never allow */
1451 }
1452
1453 /* Main status register : 0x04 (read) */
1454 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
1455 {
1456 uint32_t retval = fdctrl->msr;
1457
1458 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1459 fdctrl->dor |= FD_DOR_nRESET;
1460
1461 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1462
1463 return retval;
1464 }
1465
1466 /* Data select rate register : 0x04 (write) */
1467 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
1468 {
1469 /* Reset mode */
1470 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1471 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1472 return;
1473 }
1474 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1475 /* Reset: autoclear */
1476 if (value & FD_DSR_SWRESET) {
1477 fdctrl->dor &= ~FD_DOR_nRESET;
1478 fdctrl_reset(fdctrl, 1);
1479 fdctrl->dor |= FD_DOR_nRESET;
1480 }
1481 if (value & FD_DSR_PWRDOWN) {
1482 fdctrl_reset(fdctrl, 1);
1483 }
1484 fdctrl->dsr = value;
1485 }
1486
1487 /* Configuration control register: 0x07 (write) */
1488 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1489 {
1490 /* Reset mode */
1491 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1492 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1493 return;
1494 }
1495 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1496
1497 /* Only the rate selection bits used in AT mode, and we
1498 * store those in the DSR.
1499 */
1500 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1501 (value & FD_DSR_DRATEMASK);
1502 }
1503
1504 static int fdctrl_media_changed(FDrive *drv)
1505 {
1506 return drv->media_changed;
1507 }
1508
1509 /* Digital input register : 0x07 (read-only) */
1510 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
1511 {
1512 uint32_t retval = 0;
1513
1514 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
1515 retval |= FD_DIR_DSKCHG;
1516 }
1517 if (retval != 0) {
1518 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1519 }
1520
1521 return retval;
1522 }
1523
1524 /* Clear the FIFO and update the state for receiving the next command */
1525 static void fdctrl_to_command_phase(FDCtrl *fdctrl)
1526 {
1527 fdctrl->phase = FD_PHASE_COMMAND;
1528 fdctrl->data_dir = FD_DIR_WRITE;
1529 fdctrl->data_pos = 0;
1530 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
1531 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1532 fdctrl->msr |= FD_MSR_RQM;
1533 }
1534
1535 /* Update the state to allow the guest to read out the command status.
1536 * @fifo_len is the number of result bytes to be read out. */
1537 static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
1538 {
1539 fdctrl->phase = FD_PHASE_RESULT;
1540 fdctrl->data_dir = FD_DIR_READ;
1541 fdctrl->data_len = fifo_len;
1542 fdctrl->data_pos = 0;
1543 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1544 }
1545
1546 /* Set an error: unimplemented/unknown command */
1547 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1548 {
1549 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1550 fdctrl->fifo[0]);
1551 fdctrl->fifo[0] = FD_SR0_INVCMD;
1552 fdctrl_to_result_phase(fdctrl, 1);
1553 }
1554
1555 /* Seek to next sector
1556 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1557 * otherwise returns 1
1558 */
1559 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1560 {
1561 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1562 cur_drv->head, cur_drv->track, cur_drv->sect,
1563 fd_sector(cur_drv));
1564 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1565 error in fact */
1566 uint8_t new_head = cur_drv->head;
1567 uint8_t new_track = cur_drv->track;
1568 uint8_t new_sect = cur_drv->sect;
1569
1570 int ret = 1;
1571
1572 if (new_sect >= cur_drv->last_sect ||
1573 new_sect == fdctrl->eot) {
1574 new_sect = 1;
1575 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1576 if (new_head == 0 &&
1577 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1578 new_head = 1;
1579 } else {
1580 new_head = 0;
1581 new_track++;
1582 fdctrl->status0 |= FD_SR0_SEEK;
1583 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1584 ret = 0;
1585 }
1586 }
1587 } else {
1588 fdctrl->status0 |= FD_SR0_SEEK;
1589 new_track++;
1590 ret = 0;
1591 }
1592 if (ret == 1) {
1593 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1594 new_head, new_track, new_sect, fd_sector(cur_drv));
1595 }
1596 } else {
1597 new_sect++;
1598 }
1599 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1600 return ret;
1601 }
1602
1603 /* Callback for transfer end (stop or abort) */
1604 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1605 uint8_t status1, uint8_t status2)
1606 {
1607 FDrive *cur_drv;
1608 cur_drv = get_cur_drv(fdctrl);
1609
1610 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1611 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1612 if (cur_drv->head) {
1613 fdctrl->status0 |= FD_SR0_HEAD;
1614 }
1615 fdctrl->status0 |= status0;
1616
1617 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1618 status0, status1, status2, fdctrl->status0);
1619 fdctrl->fifo[0] = fdctrl->status0;
1620 fdctrl->fifo[1] = status1;
1621 fdctrl->fifo[2] = status2;
1622 fdctrl->fifo[3] = cur_drv->track;
1623 fdctrl->fifo[4] = cur_drv->head;
1624 fdctrl->fifo[5] = cur_drv->sect;
1625 fdctrl->fifo[6] = FD_SECTOR_SC;
1626 fdctrl->data_dir = FD_DIR_READ;
1627 if (fdctrl->dma_chann != -1 && !(fdctrl->msr & FD_MSR_NONDMA)) {
1628 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1629 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann);
1630 }
1631 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1632 fdctrl->msr &= ~FD_MSR_NONDMA;
1633
1634 fdctrl_to_result_phase(fdctrl, 7);
1635 fdctrl_raise_irq(fdctrl);
1636 }
1637
1638 /* Prepare a data transfer (either DMA or FIFO) */
1639 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1640 {
1641 FDrive *cur_drv;
1642 uint8_t kh, kt, ks;
1643
1644 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1645 cur_drv = get_cur_drv(fdctrl);
1646 kt = fdctrl->fifo[2];
1647 kh = fdctrl->fifo[3];
1648 ks = fdctrl->fifo[4];
1649 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1650 GET_CUR_DRV(fdctrl), kh, kt, ks,
1651 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1652 NUM_SIDES(cur_drv)));
1653 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1654 case 2:
1655 /* sect too big */
1656 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1657 fdctrl->fifo[3] = kt;
1658 fdctrl->fifo[4] = kh;
1659 fdctrl->fifo[5] = ks;
1660 return;
1661 case 3:
1662 /* track too big */
1663 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1664 fdctrl->fifo[3] = kt;
1665 fdctrl->fifo[4] = kh;
1666 fdctrl->fifo[5] = ks;
1667 return;
1668 case 4:
1669 /* No seek enabled */
1670 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1671 fdctrl->fifo[3] = kt;
1672 fdctrl->fifo[4] = kh;
1673 fdctrl->fifo[5] = ks;
1674 return;
1675 case 1:
1676 fdctrl->status0 |= FD_SR0_SEEK;
1677 break;
1678 default:
1679 break;
1680 }
1681
1682 /* Check the data rate. If the programmed data rate does not match
1683 * the currently inserted medium, the operation has to fail. */
1684 if (fdctrl->check_media_rate &&
1685 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1686 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1687 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1688 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1689 fdctrl->fifo[3] = kt;
1690 fdctrl->fifo[4] = kh;
1691 fdctrl->fifo[5] = ks;
1692 return;
1693 }
1694
1695 /* Set the FIFO state */
1696 fdctrl->data_dir = direction;
1697 fdctrl->data_pos = 0;
1698 assert(fdctrl->msr & FD_MSR_CMDBUSY);
1699 if (fdctrl->fifo[0] & 0x80)
1700 fdctrl->data_state |= FD_STATE_MULTI;
1701 else
1702 fdctrl->data_state &= ~FD_STATE_MULTI;
1703 if (fdctrl->fifo[5] == 0) {
1704 fdctrl->data_len = fdctrl->fifo[8];
1705 } else {
1706 int tmp;
1707 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1708 tmp = (fdctrl->fifo[6] - ks + 1);
1709 if (fdctrl->fifo[0] & 0x80)
1710 tmp += fdctrl->fifo[6];
1711 fdctrl->data_len *= tmp;
1712 }
1713 fdctrl->eot = fdctrl->fifo[6];
1714 if (fdctrl->dor & FD_DOR_DMAEN) {
1715 IsaDmaTransferMode dma_mode;
1716 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1717 bool dma_mode_ok;
1718 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1719 dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann);
1720 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1721 dma_mode, direction,
1722 (128 << fdctrl->fifo[5]) *
1723 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1724 switch (direction) {
1725 case FD_DIR_SCANE:
1726 case FD_DIR_SCANL:
1727 case FD_DIR_SCANH:
1728 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY);
1729 break;
1730 case FD_DIR_WRITE:
1731 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE);
1732 break;
1733 case FD_DIR_READ:
1734 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ);
1735 break;
1736 case FD_DIR_VERIFY:
1737 dma_mode_ok = true;
1738 break;
1739 default:
1740 dma_mode_ok = false;
1741 break;
1742 }
1743 if (dma_mode_ok) {
1744 /* No access is allowed until DMA transfer has completed */
1745 fdctrl->msr &= ~FD_MSR_RQM;
1746 if (direction != FD_DIR_VERIFY) {
1747 /* Now, we just have to wait for the DMA controller to
1748 * recall us...
1749 */
1750 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann);
1751 k->schedule(fdctrl->dma);
1752 } else {
1753 /* Start transfer */
1754 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1755 fdctrl->data_len);
1756 }
1757 return;
1758 } else {
1759 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1760 direction);
1761 }
1762 }
1763 FLOPPY_DPRINTF("start non-DMA transfer\n");
1764 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
1765 if (direction != FD_DIR_WRITE)
1766 fdctrl->msr |= FD_MSR_DIO;
1767 /* IO based transfer: calculate len */
1768 fdctrl_raise_irq(fdctrl);
1769 }
1770
1771 /* Prepare a transfer of deleted data */
1772 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1773 {
1774 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1775
1776 /* We don't handle deleted data,
1777 * so we don't return *ANYTHING*
1778 */
1779 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1780 }
1781
1782 /* handlers for DMA transfers */
1783 static int fdctrl_transfer_handler (void *opaque, int nchan,
1784 int dma_pos, int dma_len)
1785 {
1786 FDCtrl *fdctrl;
1787 FDrive *cur_drv;
1788 int len, start_pos, rel_pos;
1789 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1790 IsaDmaClass *k;
1791
1792 fdctrl = opaque;
1793 if (fdctrl->msr & FD_MSR_RQM) {
1794 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1795 return 0;
1796 }
1797 k = ISADMA_GET_CLASS(fdctrl->dma);
1798 cur_drv = get_cur_drv(fdctrl);
1799 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1800 fdctrl->data_dir == FD_DIR_SCANH)
1801 status2 = FD_SR2_SNS;
1802 if (dma_len > fdctrl->data_len)
1803 dma_len = fdctrl->data_len;
1804 if (cur_drv->blk == NULL) {
1805 if (fdctrl->data_dir == FD_DIR_WRITE)
1806 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1807 else
1808 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1809 len = 0;
1810 goto transfer_error;
1811 }
1812 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1813 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1814 len = dma_len - fdctrl->data_pos;
1815 if (len + rel_pos > FD_SECTOR_LEN)
1816 len = FD_SECTOR_LEN - rel_pos;
1817 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1818 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1819 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1820 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1821 fd_sector(cur_drv) * FD_SECTOR_LEN);
1822 if (fdctrl->data_dir != FD_DIR_WRITE ||
1823 len < FD_SECTOR_LEN || rel_pos != 0) {
1824 /* READ & SCAN commands and realign to a sector for WRITE */
1825 if (blk_pread(cur_drv->blk, fd_offset(cur_drv),
1826 fdctrl->fifo, BDRV_SECTOR_SIZE) < 0) {
1827 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1828 fd_sector(cur_drv));
1829 /* Sure, image size is too small... */
1830 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1831 }
1832 }
1833 switch (fdctrl->data_dir) {
1834 case FD_DIR_READ:
1835 /* READ commands */
1836 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1837 fdctrl->data_pos, len);
1838 break;
1839 case FD_DIR_WRITE:
1840 /* WRITE commands */
1841 if (cur_drv->ro) {
1842 /* Handle readonly medium early, no need to do DMA, touch the
1843 * LED or attempt any writes. A real floppy doesn't attempt
1844 * to write to readonly media either. */
1845 fdctrl_stop_transfer(fdctrl,
1846 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1847 0x00);
1848 goto transfer_error;
1849 }
1850
1851 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1852 fdctrl->data_pos, len);
1853 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv),
1854 fdctrl->fifo, BDRV_SECTOR_SIZE, 0) < 0) {
1855 FLOPPY_DPRINTF("error writing sector %d\n",
1856 fd_sector(cur_drv));
1857 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1858 goto transfer_error;
1859 }
1860 break;
1861 case FD_DIR_VERIFY:
1862 /* VERIFY commands */
1863 break;
1864 default:
1865 /* SCAN commands */
1866 {
1867 uint8_t tmpbuf[FD_SECTOR_LEN];
1868 int ret;
1869 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos,
1870 len);
1871 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1872 if (ret == 0) {
1873 status2 = FD_SR2_SEH;
1874 goto end_transfer;
1875 }
1876 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1877 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1878 status2 = 0x00;
1879 goto end_transfer;
1880 }
1881 }
1882 break;
1883 }
1884 fdctrl->data_pos += len;
1885 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1886 if (rel_pos == 0) {
1887 /* Seek to next sector */
1888 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1889 break;
1890 }
1891 }
1892 end_transfer:
1893 len = fdctrl->data_pos - start_pos;
1894 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1895 fdctrl->data_pos, len, fdctrl->data_len);
1896 if (fdctrl->data_dir == FD_DIR_SCANE ||
1897 fdctrl->data_dir == FD_DIR_SCANL ||
1898 fdctrl->data_dir == FD_DIR_SCANH)
1899 status2 = FD_SR2_SEH;
1900 fdctrl->data_len -= len;
1901 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1902 transfer_error:
1903
1904 return len;
1905 }
1906
1907 /* Data register : 0x05 */
1908 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1909 {
1910 FDrive *cur_drv;
1911 uint32_t retval = 0;
1912 uint32_t pos;
1913
1914 cur_drv = get_cur_drv(fdctrl);
1915 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1916 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1917 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1918 return 0;
1919 }
1920
1921 /* If data_len spans multiple sectors, the current position in the FIFO
1922 * wraps around while fdctrl->data_pos is the real position in the whole
1923 * request. */
1924 pos = fdctrl->data_pos;
1925 pos %= FD_SECTOR_LEN;
1926
1927 switch (fdctrl->phase) {
1928 case FD_PHASE_EXECUTION:
1929 assert(fdctrl->msr & FD_MSR_NONDMA);
1930 if (pos == 0) {
1931 if (fdctrl->data_pos != 0)
1932 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1933 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1934 fd_sector(cur_drv));
1935 return 0;
1936 }
1937 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1938 BDRV_SECTOR_SIZE)
1939 < 0) {
1940 FLOPPY_DPRINTF("error getting sector %d\n",
1941 fd_sector(cur_drv));
1942 /* Sure, image size is too small... */
1943 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1944 }
1945 }
1946
1947 if (++fdctrl->data_pos == fdctrl->data_len) {
1948 fdctrl->msr &= ~FD_MSR_RQM;
1949 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1950 }
1951 break;
1952
1953 case FD_PHASE_RESULT:
1954 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1955 if (++fdctrl->data_pos == fdctrl->data_len) {
1956 fdctrl->msr &= ~FD_MSR_RQM;
1957 fdctrl_to_command_phase(fdctrl);
1958 fdctrl_reset_irq(fdctrl);
1959 }
1960 break;
1961
1962 case FD_PHASE_COMMAND:
1963 default:
1964 abort();
1965 }
1966
1967 retval = fdctrl->fifo[pos];
1968 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1969
1970 return retval;
1971 }
1972
1973 static void fdctrl_format_sector(FDCtrl *fdctrl)
1974 {
1975 FDrive *cur_drv;
1976 uint8_t kh, kt, ks;
1977
1978 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1979 cur_drv = get_cur_drv(fdctrl);
1980 kt = fdctrl->fifo[6];
1981 kh = fdctrl->fifo[7];
1982 ks = fdctrl->fifo[8];
1983 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1984 GET_CUR_DRV(fdctrl), kh, kt, ks,
1985 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1986 NUM_SIDES(cur_drv)));
1987 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1988 case 2:
1989 /* sect too big */
1990 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1991 fdctrl->fifo[3] = kt;
1992 fdctrl->fifo[4] = kh;
1993 fdctrl->fifo[5] = ks;
1994 return;
1995 case 3:
1996 /* track too big */
1997 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1998 fdctrl->fifo[3] = kt;
1999 fdctrl->fifo[4] = kh;
2000 fdctrl->fifo[5] = ks;
2001 return;
2002 case 4:
2003 /* No seek enabled */
2004 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
2005 fdctrl->fifo[3] = kt;
2006 fdctrl->fifo[4] = kh;
2007 fdctrl->fifo[5] = ks;
2008 return;
2009 case 1:
2010 fdctrl->status0 |= FD_SR0_SEEK;
2011 break;
2012 default:
2013 break;
2014 }
2015 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
2016 if (cur_drv->blk == NULL ||
2017 blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2018 BDRV_SECTOR_SIZE, 0) < 0) {
2019 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
2020 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
2021 } else {
2022 if (cur_drv->sect == cur_drv->last_sect) {
2023 fdctrl->data_state &= ~FD_STATE_FORMAT;
2024 /* Last sector done */
2025 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2026 } else {
2027 /* More to do */
2028 fdctrl->data_pos = 0;
2029 fdctrl->data_len = 4;
2030 }
2031 }
2032 }
2033
2034 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
2035 {
2036 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
2037 fdctrl->fifo[0] = fdctrl->lock << 4;
2038 fdctrl_to_result_phase(fdctrl, 1);
2039 }
2040
2041 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
2042 {
2043 FDrive *cur_drv = get_cur_drv(fdctrl);
2044
2045 /* Drives position */
2046 fdctrl->fifo[0] = drv0(fdctrl)->track;
2047 fdctrl->fifo[1] = drv1(fdctrl)->track;
2048 #if MAX_FD == 4
2049 fdctrl->fifo[2] = drv2(fdctrl)->track;
2050 fdctrl->fifo[3] = drv3(fdctrl)->track;
2051 #else
2052 fdctrl->fifo[2] = 0;
2053 fdctrl->fifo[3] = 0;
2054 #endif
2055 /* timers */
2056 fdctrl->fifo[4] = fdctrl->timer0;
2057 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
2058 fdctrl->fifo[6] = cur_drv->last_sect;
2059 fdctrl->fifo[7] = (fdctrl->lock << 7) |
2060 (cur_drv->perpendicular << 2);
2061 fdctrl->fifo[8] = fdctrl->config;
2062 fdctrl->fifo[9] = fdctrl->precomp_trk;
2063 fdctrl_to_result_phase(fdctrl, 10);
2064 }
2065
2066 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
2067 {
2068 /* Controller's version */
2069 fdctrl->fifo[0] = fdctrl->version;
2070 fdctrl_to_result_phase(fdctrl, 1);
2071 }
2072
2073 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
2074 {
2075 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
2076 fdctrl_to_result_phase(fdctrl, 1);
2077 }
2078
2079 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
2080 {
2081 FDrive *cur_drv = get_cur_drv(fdctrl);
2082
2083 /* Drives position */
2084 drv0(fdctrl)->track = fdctrl->fifo[3];
2085 drv1(fdctrl)->track = fdctrl->fifo[4];
2086 #if MAX_FD == 4
2087 drv2(fdctrl)->track = fdctrl->fifo[5];
2088 drv3(fdctrl)->track = fdctrl->fifo[6];
2089 #endif
2090 /* timers */
2091 fdctrl->timer0 = fdctrl->fifo[7];
2092 fdctrl->timer1 = fdctrl->fifo[8];
2093 cur_drv->last_sect = fdctrl->fifo[9];
2094 fdctrl->lock = fdctrl->fifo[10] >> 7;
2095 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
2096 fdctrl->config = fdctrl->fifo[11];
2097 fdctrl->precomp_trk = fdctrl->fifo[12];
2098 fdctrl->pwrd = fdctrl->fifo[13];
2099 fdctrl_to_command_phase(fdctrl);
2100 }
2101
2102 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
2103 {
2104 FDrive *cur_drv = get_cur_drv(fdctrl);
2105
2106 fdctrl->fifo[0] = 0;
2107 fdctrl->fifo[1] = 0;
2108 /* Drives position */
2109 fdctrl->fifo[2] = drv0(fdctrl)->track;
2110 fdctrl->fifo[3] = drv1(fdctrl)->track;
2111 #if MAX_FD == 4
2112 fdctrl->fifo[4] = drv2(fdctrl)->track;
2113 fdctrl->fifo[5] = drv3(fdctrl)->track;
2114 #else
2115 fdctrl->fifo[4] = 0;
2116 fdctrl->fifo[5] = 0;
2117 #endif
2118 /* timers */
2119 fdctrl->fifo[6] = fdctrl->timer0;
2120 fdctrl->fifo[7] = fdctrl->timer1;
2121 fdctrl->fifo[8] = cur_drv->last_sect;
2122 fdctrl->fifo[9] = (fdctrl->lock << 7) |
2123 (cur_drv->perpendicular << 2);
2124 fdctrl->fifo[10] = fdctrl->config;
2125 fdctrl->fifo[11] = fdctrl->precomp_trk;
2126 fdctrl->fifo[12] = fdctrl->pwrd;
2127 fdctrl->fifo[13] = 0;
2128 fdctrl->fifo[14] = 0;
2129 fdctrl_to_result_phase(fdctrl, 15);
2130 }
2131
2132 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
2133 {
2134 FDrive *cur_drv = get_cur_drv(fdctrl);
2135
2136 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2137 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2138 (NANOSECONDS_PER_SECOND / 50));
2139 }
2140
2141 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
2142 {
2143 FDrive *cur_drv;
2144
2145 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2146 cur_drv = get_cur_drv(fdctrl);
2147 fdctrl->data_state |= FD_STATE_FORMAT;
2148 if (fdctrl->fifo[0] & 0x80)
2149 fdctrl->data_state |= FD_STATE_MULTI;
2150 else
2151 fdctrl->data_state &= ~FD_STATE_MULTI;
2152 cur_drv->bps =
2153 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
2154 #if 0
2155 cur_drv->last_sect =
2156 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
2157 fdctrl->fifo[3] / 2;
2158 #else
2159 cur_drv->last_sect = fdctrl->fifo[3];
2160 #endif
2161 /* TODO: implement format using DMA expected by the Bochs BIOS
2162 * and Linux fdformat (read 3 bytes per sector via DMA and fill
2163 * the sector with the specified fill byte
2164 */
2165 fdctrl->data_state &= ~FD_STATE_FORMAT;
2166 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2167 }
2168
2169 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
2170 {
2171 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
2172 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
2173 if (fdctrl->fifo[2] & 1)
2174 fdctrl->dor &= ~FD_DOR_DMAEN;
2175 else
2176 fdctrl->dor |= FD_DOR_DMAEN;
2177 /* No result back */
2178 fdctrl_to_command_phase(fdctrl);
2179 }
2180
2181 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
2182 {
2183 FDrive *cur_drv;
2184
2185 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2186 cur_drv = get_cur_drv(fdctrl);
2187 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2188 /* 1 Byte status back */
2189 fdctrl->fifo[0] = (cur_drv->ro << 6) |
2190 (cur_drv->track == 0 ? 0x10 : 0x00) |
2191 (cur_drv->head << 2) |
2192 GET_CUR_DRV(fdctrl) |
2193 0x28;
2194 fdctrl_to_result_phase(fdctrl, 1);
2195 }
2196
2197 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
2198 {
2199 FDrive *cur_drv;
2200
2201 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2202 cur_drv = get_cur_drv(fdctrl);
2203 fd_recalibrate(cur_drv);
2204 fdctrl_to_command_phase(fdctrl);
2205 /* Raise Interrupt */
2206 fdctrl->status0 |= FD_SR0_SEEK;
2207 fdctrl_raise_irq(fdctrl);
2208 }
2209
2210 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
2211 {
2212 FDrive *cur_drv = get_cur_drv(fdctrl);
2213
2214 if (fdctrl->reset_sensei > 0) {
2215 fdctrl->fifo[0] =
2216 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
2217 fdctrl->reset_sensei--;
2218 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
2219 fdctrl->fifo[0] = FD_SR0_INVCMD;
2220 fdctrl_to_result_phase(fdctrl, 1);
2221 return;
2222 } else {
2223 fdctrl->fifo[0] =
2224 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
2225 | GET_CUR_DRV(fdctrl);
2226 }
2227
2228 fdctrl->fifo[1] = cur_drv->track;
2229 fdctrl_to_result_phase(fdctrl, 2);
2230 fdctrl_reset_irq(fdctrl);
2231 fdctrl->status0 = FD_SR0_RDYCHG;
2232 }
2233
2234 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
2235 {
2236 FDrive *cur_drv;
2237
2238 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2239 cur_drv = get_cur_drv(fdctrl);
2240 fdctrl_to_command_phase(fdctrl);
2241 /* The seek command just sends step pulses to the drive and doesn't care if
2242 * there is a medium inserted of if it's banging the head against the drive.
2243 */
2244 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
2245 /* Raise Interrupt */
2246 fdctrl->status0 |= FD_SR0_SEEK;
2247 fdctrl_raise_irq(fdctrl);
2248 }
2249
2250 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
2251 {
2252 FDrive *cur_drv = get_cur_drv(fdctrl);
2253
2254 if (fdctrl->fifo[1] & 0x80)
2255 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
2256 /* No result back */
2257 fdctrl_to_command_phase(fdctrl);
2258 }
2259
2260 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
2261 {
2262 fdctrl->config = fdctrl->fifo[2];
2263 fdctrl->precomp_trk = fdctrl->fifo[3];
2264 /* No result back */
2265 fdctrl_to_command_phase(fdctrl);
2266 }
2267
2268 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
2269 {
2270 fdctrl->pwrd = fdctrl->fifo[1];
2271 fdctrl->fifo[0] = fdctrl->fifo[1];
2272 fdctrl_to_result_phase(fdctrl, 1);
2273 }
2274
2275 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
2276 {
2277 /* No result back */
2278 fdctrl_to_command_phase(fdctrl);
2279 }
2280
2281 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
2282 {
2283 FDrive *cur_drv = get_cur_drv(fdctrl);
2284 uint32_t pos;
2285
2286 pos = fdctrl->data_pos - 1;
2287 pos %= FD_SECTOR_LEN;
2288 if (fdctrl->fifo[pos] & 0x80) {
2289 /* Command parameters done */
2290 if (fdctrl->fifo[pos] & 0x40) {
2291 fdctrl->fifo[0] = fdctrl->fifo[1];
2292 fdctrl->fifo[2] = 0;
2293 fdctrl->fifo[3] = 0;
2294 fdctrl_to_result_phase(fdctrl, 4);
2295 } else {
2296 fdctrl_to_command_phase(fdctrl);
2297 }
2298 } else if (fdctrl->data_len > 7) {
2299 /* ERROR */
2300 fdctrl->fifo[0] = 0x80 |
2301 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
2302 fdctrl_to_result_phase(fdctrl, 1);
2303 }
2304 }
2305
2306 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
2307 {
2308 FDrive *cur_drv;
2309
2310 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2311 cur_drv = get_cur_drv(fdctrl);
2312 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
2313 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2314 cur_drv->sect, 1);
2315 } else {
2316 fd_seek(cur_drv, cur_drv->head,
2317 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
2318 }
2319 fdctrl_to_command_phase(fdctrl);
2320 /* Raise Interrupt */
2321 fdctrl->status0 |= FD_SR0_SEEK;
2322 fdctrl_raise_irq(fdctrl);
2323 }
2324
2325 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
2326 {
2327 FDrive *cur_drv;
2328
2329 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2330 cur_drv = get_cur_drv(fdctrl);
2331 if (fdctrl->fifo[2] > cur_drv->track) {
2332 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
2333 } else {
2334 fd_seek(cur_drv, cur_drv->head,
2335 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
2336 }
2337 fdctrl_to_command_phase(fdctrl);
2338 /* Raise Interrupt */
2339 fdctrl->status0 |= FD_SR0_SEEK;
2340 fdctrl_raise_irq(fdctrl);
2341 }
2342
2343 /*
2344 * Handlers for the execution phase of each command
2345 */
2346 typedef struct FDCtrlCommand {
2347 uint8_t value;
2348 uint8_t mask;
2349 const char* name;
2350 int parameters;
2351 void (*handler)(FDCtrl *fdctrl, int direction);
2352 int direction;
2353 } FDCtrlCommand;
2354
2355 static const FDCtrlCommand handlers[] = {
2356 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2357 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2358 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2359 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2360 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2361 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2362 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2363 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2364 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2365 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2366 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
2367 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
2368 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2369 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2370 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2371 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2372 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2373 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2374 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2375 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2376 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2377 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2378 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2379 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2380 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2381 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2382 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2383 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2384 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2385 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2386 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2387 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2388 };
2389 /* Associate command to an index in the 'handlers' array */
2390 static uint8_t command_to_handler[256];
2391
2392 static const FDCtrlCommand *get_command(uint8_t cmd)
2393 {
2394 int idx;
2395
2396 idx = command_to_handler[cmd];
2397 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2398 return &handlers[idx];
2399 }
2400
2401 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
2402 {
2403 FDrive *cur_drv;
2404 const FDCtrlCommand *cmd;
2405 uint32_t pos;
2406
2407 /* Reset mode */
2408 if (!(fdctrl->dor & FD_DOR_nRESET)) {
2409 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
2410 return;
2411 }
2412 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
2413 FLOPPY_DPRINTF("error: controller not ready for writing\n");
2414 return;
2415 }
2416 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
2417
2418 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2419
2420 /* If data_len spans multiple sectors, the current position in the FIFO
2421 * wraps around while fdctrl->data_pos is the real position in the whole
2422 * request. */
2423 pos = fdctrl->data_pos++;
2424 pos %= FD_SECTOR_LEN;
2425 fdctrl->fifo[pos] = value;
2426
2427 if (fdctrl->data_pos == fdctrl->data_len) {
2428 fdctrl->msr &= ~FD_MSR_RQM;
2429 }
2430
2431 switch (fdctrl->phase) {
2432 case FD_PHASE_EXECUTION:
2433 /* For DMA requests, RQM should be cleared during execution phase, so
2434 * we would have errored out above. */
2435 assert(fdctrl->msr & FD_MSR_NONDMA);
2436
2437 /* FIFO data write */
2438 if (pos == FD_SECTOR_LEN - 1 ||
2439 fdctrl->data_pos == fdctrl->data_len) {
2440 cur_drv = get_cur_drv(fdctrl);
2441 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2442 BDRV_SECTOR_SIZE, 0) < 0) {
2443 FLOPPY_DPRINTF("error writing sector %d\n",
2444 fd_sector(cur_drv));
2445 break;
2446 }
2447 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2448 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2449 fd_sector(cur_drv));
2450 break;
2451 }
2452 }
2453
2454 /* Switch to result phase when done with the transfer */
2455 if (fdctrl->data_pos == fdctrl->data_len) {
2456 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2457 }
2458 break;
2459
2460 case FD_PHASE_COMMAND:
2461 assert(!(fdctrl->msr & FD_MSR_NONDMA));
2462 assert(fdctrl->data_pos < FD_SECTOR_LEN);
2463
2464 if (pos == 0) {
2465 /* The first byte specifies the command. Now we start reading
2466 * as many parameters as this command requires. */
2467 cmd = get_command(value);
2468 fdctrl->data_len = cmd->parameters + 1;
2469 if (cmd->parameters) {
2470 fdctrl->msr |= FD_MSR_RQM;
2471 }
2472 fdctrl->msr |= FD_MSR_CMDBUSY;
2473 }
2474
2475 if (fdctrl->data_pos == fdctrl->data_len) {
2476 /* We have all parameters now, execute the command */
2477 fdctrl->phase = FD_PHASE_EXECUTION;
2478
2479 if (fdctrl->data_state & FD_STATE_FORMAT) {
2480 fdctrl_format_sector(fdctrl);
2481 break;
2482 }
2483
2484 cmd = get_command(fdctrl->fifo[0]);
2485 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2486 cmd->handler(fdctrl, cmd->direction);
2487 }
2488 break;
2489
2490 case FD_PHASE_RESULT:
2491 default:
2492 abort();
2493 }
2494 }
2495
2496 static void fdctrl_result_timer(void *opaque)
2497 {
2498 FDCtrl *fdctrl = opaque;
2499 FDrive *cur_drv = get_cur_drv(fdctrl);
2500
2501 /* Pretend we are spinning.
2502 * This is needed for Coherent, which uses READ ID to check for
2503 * sector interleaving.
2504 */
2505 if (cur_drv->last_sect != 0) {
2506 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2507 }
2508 /* READ_ID can't automatically succeed! */
2509 if (fdctrl->check_media_rate &&
2510 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2511 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2512 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2513 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2514 } else {
2515 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2516 }
2517 }
2518
2519 /* Init functions */
2520 static void fdctrl_connect_drives(FDCtrl *fdctrl, DeviceState *fdc_dev,
2521 Error **errp)
2522 {
2523 unsigned int i;
2524 FDrive *drive;
2525 DeviceState *dev;
2526 BlockBackend *blk;
2527 Error *local_err = NULL;
2528
2529 for (i = 0; i < MAX_FD; i++) {
2530 drive = &fdctrl->drives[i];
2531 drive->fdctrl = fdctrl;
2532
2533 /* If the drive is not present, we skip creating the qdev device, but
2534 * still have to initialise the controller. */
2535 blk = fdctrl->qdev_for_drives[i].blk;
2536 if (!blk) {
2537 fd_init(drive);
2538 fd_revalidate(drive);
2539 continue;
2540 }
2541
2542 dev = qdev_create(&fdctrl->bus.bus, "floppy");
2543 qdev_prop_set_uint32(dev, "unit", i);
2544 qdev_prop_set_enum(dev, "drive-type", fdctrl->qdev_for_drives[i].type);
2545
2546 blk_ref(blk);
2547 blk_detach_dev(blk, fdc_dev);
2548 fdctrl->qdev_for_drives[i].blk = NULL;
2549 qdev_prop_set_drive(dev, "drive", blk, &local_err);
2550 blk_unref(blk);
2551
2552 if (local_err) {
2553 error_propagate(errp, local_err);
2554 return;
2555 }
2556
2557 object_property_set_bool(OBJECT(dev), true, "realized", &local_err);
2558 if (local_err) {
2559 error_propagate(errp, local_err);
2560 return;
2561 }
2562 }
2563 }
2564
2565 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2566 {
2567 DeviceState *dev;
2568 ISADevice *isadev;
2569
2570 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2571 if (!isadev) {
2572 return NULL;
2573 }
2574 dev = DEVICE(isadev);
2575
2576 if (fds[0]) {
2577 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2578 &error_fatal);
2579 }
2580 if (fds[1]) {
2581 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2582 &error_fatal);
2583 }
2584 qdev_init_nofail(dev);
2585
2586 return isadev;
2587 }
2588
2589 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
2590 hwaddr mmio_base, DriveInfo **fds)
2591 {
2592 FDCtrl *fdctrl;
2593 DeviceState *dev;
2594 SysBusDevice *sbd;
2595 FDCtrlSysBus *sys;
2596
2597 dev = qdev_create(NULL, "sysbus-fdc");
2598 sys = SYSBUS_FDC(dev);
2599 fdctrl = &sys->state;
2600 fdctrl->dma_chann = dma_chann; /* FIXME */
2601 if (fds[0]) {
2602 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2603 &error_fatal);
2604 }
2605 if (fds[1]) {
2606 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2607 &error_fatal);
2608 }
2609 qdev_init_nofail(dev);
2610 sbd = SYS_BUS_DEVICE(dev);
2611 sysbus_connect_irq(sbd, 0, irq);
2612 sysbus_mmio_map(sbd, 0, mmio_base);
2613 }
2614
2615 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
2616 DriveInfo **fds, qemu_irq *fdc_tc)
2617 {
2618 DeviceState *dev;
2619 FDCtrlSysBus *sys;
2620
2621 dev = qdev_create(NULL, "SUNW,fdtwo");
2622 if (fds[0]) {
2623 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
2624 &error_fatal);
2625 }
2626 qdev_init_nofail(dev);
2627 sys = SYSBUS_FDC(dev);
2628 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2629 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
2630 *fdc_tc = qdev_get_gpio_in(dev, 0);
2631 }
2632
2633 static void fdctrl_realize_common(DeviceState *dev, FDCtrl *fdctrl,
2634 Error **errp)
2635 {
2636 int i, j;
2637 static int command_tables_inited = 0;
2638
2639 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2640 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
2641 }
2642
2643 /* Fill 'command_to_handler' lookup table */
2644 if (!command_tables_inited) {
2645 command_tables_inited = 1;
2646 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2647 for (j = 0; j < sizeof(command_to_handler); j++) {
2648 if ((j & handlers[i].mask) == handlers[i].value) {
2649 command_to_handler[j] = i;
2650 }
2651 }
2652 }
2653 }
2654
2655 FLOPPY_DPRINTF("init controller\n");
2656 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
2657 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
2658 fdctrl->fifo_size = 512;
2659 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2660 fdctrl_result_timer, fdctrl);
2661
2662 fdctrl->version = 0x90; /* Intel 82078 controller */
2663 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
2664 fdctrl->num_floppies = MAX_FD;
2665
2666 if (fdctrl->dma_chann != -1) {
2667 IsaDmaClass *k;
2668 assert(fdctrl->dma);
2669 k = ISADMA_GET_CLASS(fdctrl->dma);
2670 k->register_channel(fdctrl->dma, fdctrl->dma_chann,
2671 &fdctrl_transfer_handler, fdctrl);
2672 }
2673
2674 floppy_bus_create(fdctrl, &fdctrl->bus, dev);
2675 fdctrl_connect_drives(fdctrl, dev, errp);
2676 }
2677
2678 static const MemoryRegionPortio fdc_portio_list[] = {
2679 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2680 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2681 PORTIO_END_OF_LIST(),
2682 };
2683
2684 static void isabus_fdc_realize(DeviceState *dev, Error **errp)
2685 {
2686 ISADevice *isadev = ISA_DEVICE(dev);
2687 FDCtrlISABus *isa = ISA_FDC(dev);
2688 FDCtrl *fdctrl = &isa->state;
2689 Error *err = NULL;
2690
2691 isa_register_portio_list(isadev, &fdctrl->portio_list,
2692 isa->iobase, fdc_portio_list, fdctrl,
2693 "fdc");
2694
2695 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
2696 fdctrl->dma_chann = isa->dma;
2697 if (fdctrl->dma_chann != -1) {
2698 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
2699 if (!fdctrl->dma) {
2700 error_setg(errp, "ISA controller does not support DMA");
2701 return;
2702 }
2703 }
2704
2705 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
2706 fdctrl_realize_common(dev, fdctrl, &err);
2707 if (err != NULL) {
2708 error_propagate(errp, err);
2709 return;
2710 }
2711 }
2712
2713 static void sysbus_fdc_initfn(Object *obj)
2714 {
2715 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2716 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2717 FDCtrl *fdctrl = &sys->state;
2718
2719 fdctrl->dma_chann = -1;
2720
2721 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2722 "fdc", 0x08);
2723 sysbus_init_mmio(sbd, &fdctrl->iomem);
2724 }
2725
2726 static void sun4m_fdc_initfn(Object *obj)
2727 {
2728 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2729 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2730 FDCtrl *fdctrl = &sys->state;
2731
2732 fdctrl->dma_chann = -1;
2733
2734 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2735 fdctrl, "fdctrl", 0x08);
2736 sysbus_init_mmio(sbd, &fdctrl->iomem);
2737 }
2738
2739 static void sysbus_fdc_common_initfn(Object *obj)
2740 {
2741 DeviceState *dev = DEVICE(obj);
2742 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
2743 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2744 FDCtrl *fdctrl = &sys->state;
2745
2746 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2747
2748 sysbus_init_irq(sbd, &fdctrl->irq);
2749 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
2750 }
2751
2752 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
2753 {
2754 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2755 FDCtrl *fdctrl = &sys->state;
2756
2757 fdctrl_realize_common(dev, fdctrl, errp);
2758 }
2759
2760 FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
2761 {
2762 FDCtrlISABus *isa = ISA_FDC(fdc);
2763
2764 return isa->state.drives[i].drive;
2765 }
2766
2767 void isa_fdc_get_drive_max_chs(FloppyDriveType type,
2768 uint8_t *maxc, uint8_t *maxh, uint8_t *maxs)
2769 {
2770 const FDFormat *fdf;
2771
2772 *maxc = *maxh = *maxs = 0;
2773 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) {
2774 if (fdf->drive != type) {
2775 continue;
2776 }
2777 if (*maxc < fdf->max_track) {
2778 *maxc = fdf->max_track;
2779 }
2780 if (*maxh < fdf->max_head) {
2781 *maxh = fdf->max_head;
2782 }
2783 if (*maxs < fdf->last_sect) {
2784 *maxs = fdf->last_sect;
2785 }
2786 }
2787 (*maxc)--;
2788 }
2789
2790 static const VMStateDescription vmstate_isa_fdc ={
2791 .name = "fdc",
2792 .version_id = 2,
2793 .minimum_version_id = 2,
2794 .fields = (VMStateField[]) {
2795 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2796 VMSTATE_END_OF_LIST()
2797 }
2798 };
2799
2800 static Property isa_fdc_properties[] = {
2801 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
2802 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2803 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2804 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.qdev_for_drives[0].blk),
2805 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.qdev_for_drives[1].blk),
2806 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2807 0, true),
2808 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlISABus, state.qdev_for_drives[0].type,
2809 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2810 FloppyDriveType),
2811 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlISABus, state.qdev_for_drives[1].type,
2812 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2813 FloppyDriveType),
2814 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
2815 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type,
2816 FloppyDriveType),
2817 DEFINE_PROP_END_OF_LIST(),
2818 };
2819
2820 static void isabus_fdc_class_init(ObjectClass *klass, void *data)
2821 {
2822 DeviceClass *dc = DEVICE_CLASS(klass);
2823
2824 dc->realize = isabus_fdc_realize;
2825 dc->fw_name = "fdc";
2826 dc->reset = fdctrl_external_reset_isa;
2827 dc->vmsd = &vmstate_isa_fdc;
2828 dc->props = isa_fdc_properties;
2829 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2830 }
2831
2832 static void isabus_fdc_instance_init(Object *obj)
2833 {
2834 FDCtrlISABus *isa = ISA_FDC(obj);
2835
2836 device_add_bootindex_property(obj, &isa->bootindexA,
2837 "bootindexA", "/floppy@0",
2838 DEVICE(obj), NULL);
2839 device_add_bootindex_property(obj, &isa->bootindexB,
2840 "bootindexB", "/floppy@1",
2841 DEVICE(obj), NULL);
2842 }
2843
2844 static const TypeInfo isa_fdc_info = {
2845 .name = TYPE_ISA_FDC,
2846 .parent = TYPE_ISA_DEVICE,
2847 .instance_size = sizeof(FDCtrlISABus),
2848 .class_init = isabus_fdc_class_init,
2849 .instance_init = isabus_fdc_instance_init,
2850 };
2851
2852 static const VMStateDescription vmstate_sysbus_fdc ={
2853 .name = "fdc",
2854 .version_id = 2,
2855 .minimum_version_id = 2,
2856 .fields = (VMStateField[]) {
2857 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2858 VMSTATE_END_OF_LIST()
2859 }
2860 };
2861
2862 static Property sysbus_fdc_properties[] = {
2863 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.qdev_for_drives[0].blk),
2864 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.qdev_for_drives[1].blk),
2865 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlSysBus, state.qdev_for_drives[0].type,
2866 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2867 FloppyDriveType),
2868 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlSysBus, state.qdev_for_drives[1].type,
2869 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2870 FloppyDriveType),
2871 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
2872 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2873 FloppyDriveType),
2874 DEFINE_PROP_END_OF_LIST(),
2875 };
2876
2877 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2878 {
2879 DeviceClass *dc = DEVICE_CLASS(klass);
2880
2881 dc->props = sysbus_fdc_properties;
2882 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2883 }
2884
2885 static const TypeInfo sysbus_fdc_info = {
2886 .name = "sysbus-fdc",
2887 .parent = TYPE_SYSBUS_FDC,
2888 .instance_init = sysbus_fdc_initfn,
2889 .class_init = sysbus_fdc_class_init,
2890 };
2891
2892 static Property sun4m_fdc_properties[] = {
2893 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.qdev_for_drives[0].blk),
2894 DEFINE_PROP_SIGNED("fdtype", FDCtrlSysBus, state.qdev_for_drives[0].type,
2895 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2896 FloppyDriveType),
2897 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
2898 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2899 FloppyDriveType),
2900 DEFINE_PROP_END_OF_LIST(),
2901 };
2902
2903 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2904 {
2905 DeviceClass *dc = DEVICE_CLASS(klass);
2906
2907 dc->props = sun4m_fdc_properties;
2908 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2909 }
2910
2911 static const TypeInfo sun4m_fdc_info = {
2912 .name = "SUNW,fdtwo",
2913 .parent = TYPE_SYSBUS_FDC,
2914 .instance_init = sun4m_fdc_initfn,
2915 .class_init = sun4m_fdc_class_init,
2916 };
2917
2918 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2919 {
2920 DeviceClass *dc = DEVICE_CLASS(klass);
2921
2922 dc->realize = sysbus_fdc_common_realize;
2923 dc->reset = fdctrl_external_reset_sysbus;
2924 dc->vmsd = &vmstate_sysbus_fdc;
2925 }
2926
2927 static const TypeInfo sysbus_fdc_type_info = {
2928 .name = TYPE_SYSBUS_FDC,
2929 .parent = TYPE_SYS_BUS_DEVICE,
2930 .instance_size = sizeof(FDCtrlSysBus),
2931 .instance_init = sysbus_fdc_common_initfn,
2932 .abstract = true,
2933 .class_init = sysbus_fdc_common_class_init,
2934 };
2935
2936 static void fdc_register_types(void)
2937 {
2938 type_register_static(&isa_fdc_info);
2939 type_register_static(&sysbus_fdc_type_info);
2940 type_register_static(&sysbus_fdc_info);
2941 type_register_static(&sun4m_fdc_info);
2942 type_register_static(&floppy_bus_info);
2943 type_register_static(&floppy_drive_info);
2944 }
2945
2946 type_init(fdc_register_types)
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