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block: m25p80: Introduce die erase command
[mirror_qemu.git] / hw / block / m25p80.c
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "sysemu/block-backend.h"
27 #include "sysemu/blockdev.h"
28 #include "hw/ssi/ssi.h"
29 #include "qemu/bitops.h"
30 #include "qemu/log.h"
31 #include "qemu/error-report.h"
32 #include "qapi/error.h"
33
34 #ifndef M25P80_ERR_DEBUG
35 #define M25P80_ERR_DEBUG 0
36 #endif
37
38 #define DB_PRINT_L(level, ...) do { \
39 if (M25P80_ERR_DEBUG > (level)) { \
40 fprintf(stderr, ": %s: ", __func__); \
41 fprintf(stderr, ## __VA_ARGS__); \
42 } \
43 } while (0);
44
45 /* Fields for FlashPartInfo->flags */
46
47 /* erase capabilities */
48 #define ER_4K 1
49 #define ER_32K 2
50 /* set to allow the page program command to write 0s back to 1. Useful for
51 * modelling EEPROM with SPI flash command set
52 */
53 #define EEPROM 0x100
54
55 /* 16 MiB max in 3 byte address mode */
56 #define MAX_3BYTES_SIZE 0x1000000
57
58 #define SPI_NOR_MAX_ID_LEN 6
59
60 typedef struct FlashPartInfo {
61 const char *part_name;
62 /*
63 * This array stores the ID bytes.
64 * The first three bytes are the JEDIC ID.
65 * JEDEC ID zero means "no ID" (mostly older chips).
66 */
67 uint8_t id[SPI_NOR_MAX_ID_LEN];
68 uint8_t id_len;
69 /* there is confusion between manufacturers as to what a sector is. In this
70 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
71 * command (opcode 0xd8).
72 */
73 uint32_t sector_size;
74 uint32_t n_sectors;
75 uint32_t page_size;
76 uint16_t flags;
77 /*
78 * Big sized spi nor are often stacked devices, thus sometime
79 * replace chip erase with die erase.
80 * This field inform how many die is in the chip.
81 */
82 uint8_t die_cnt;
83 } FlashPartInfo;
84
85 /* adapted from linux */
86 /* Used when the "_ext_id" is two bytes at most */
87 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
88 .part_name = _part_name,\
89 .id = {\
90 ((_jedec_id) >> 16) & 0xff,\
91 ((_jedec_id) >> 8) & 0xff,\
92 (_jedec_id) & 0xff,\
93 ((_ext_id) >> 8) & 0xff,\
94 (_ext_id) & 0xff,\
95 },\
96 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
97 .sector_size = (_sector_size),\
98 .n_sectors = (_n_sectors),\
99 .page_size = 256,\
100 .flags = (_flags),\
101 .die_cnt = 0
102
103 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
104 .part_name = _part_name,\
105 .id = {\
106 ((_jedec_id) >> 16) & 0xff,\
107 ((_jedec_id) >> 8) & 0xff,\
108 (_jedec_id) & 0xff,\
109 ((_ext_id) >> 16) & 0xff,\
110 ((_ext_id) >> 8) & 0xff,\
111 (_ext_id) & 0xff,\
112 },\
113 .id_len = 6,\
114 .sector_size = (_sector_size),\
115 .n_sectors = (_n_sectors),\
116 .page_size = 256,\
117 .flags = (_flags),\
118 .die_cnt = 0
119
120 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
121 _flags, _die_cnt)\
122 .part_name = _part_name,\
123 .id = {\
124 ((_jedec_id) >> 16) & 0xff,\
125 ((_jedec_id) >> 8) & 0xff,\
126 (_jedec_id) & 0xff,\
127 ((_ext_id) >> 8) & 0xff,\
128 (_ext_id) & 0xff,\
129 },\
130 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
131 .sector_size = (_sector_size),\
132 .n_sectors = (_n_sectors),\
133 .page_size = 256,\
134 .flags = (_flags),\
135 .die_cnt = _die_cnt
136
137 #define JEDEC_NUMONYX 0x20
138 #define JEDEC_WINBOND 0xEF
139 #define JEDEC_SPANSION 0x01
140
141 /* Numonyx (Micron) Configuration register macros */
142 #define VCFG_DUMMY 0x1
143 #define VCFG_WRAP_SEQUENTIAL 0x2
144 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
145 #define NVCFG_XIP_MODE_MASK (7 << 9)
146 #define VCFG_XIP_MODE_ENABLED (1 << 3)
147 #define CFG_DUMMY_CLK_LEN 4
148 #define NVCFG_DUMMY_CLK_POS 12
149 #define VCFG_DUMMY_CLK_POS 4
150 #define EVCFG_OUT_DRIVER_STRENGHT_DEF 7
151 #define EVCFG_VPP_ACCELERATOR (1 << 3)
152 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
153 #define NVCFG_DUAL_IO_MASK (1 << 2)
154 #define EVCFG_DUAL_IO_ENABLED (1 << 6)
155 #define NVCFG_QUAD_IO_MASK (1 << 3)
156 #define EVCFG_QUAD_IO_ENABLED (1 << 7)
157 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
158 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
159
160 /* Numonyx (Micron) Flag Status Register macros */
161 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
162 #define FSR_FLASH_READY (1 << 7)
163
164 /* Spansion configuration registers macros. */
165 #define SPANSION_QUAD_CFG_POS 0
166 #define SPANSION_QUAD_CFG_LEN 1
167 #define SPANSION_DUMMY_CLK_POS 0
168 #define SPANSION_DUMMY_CLK_LEN 4
169 #define SPANSION_ADDR_LEN_POS 7
170 #define SPANSION_ADDR_LEN_LEN 1
171
172 /*
173 * Spansion read mode command length in bytes,
174 * the mode is currently not supported.
175 */
176
177 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
178 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
179
180 static const FlashPartInfo known_devices[] = {
181 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
182 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
183 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
184
185 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
186 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
187 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
188
189 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
190 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
191 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
192 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
193
194 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
195
196 /* Atmel EEPROMS - it is assumed, that don't care bit in command
197 * is set to 0. Block protection is not supported.
198 */
199 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
200 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
201
202 /* EON -- en25xxx */
203 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
204 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
205 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
206 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
207 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
208
209 /* GigaDevice */
210 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
211 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
212
213 /* Intel/Numonyx -- xxxs33b */
214 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
215 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
216 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
217 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
218
219 /* Macronix */
220 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
221 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
222 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
223 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
224 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
225 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
226 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
227 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
228 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
229 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
230 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
231 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
232 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
233
234 /* Micron */
235 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
236 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
237 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
238 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
239 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
240 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
241 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
242 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
243 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
244 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
245 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
246 { INFO("mt25ql01g", 0x20ba21, 0, 64 << 10, 2048, ER_4K) },
247 { INFO("mt25qu01g", 0x20bb21, 0, 64 << 10, 2048, ER_4K) },
248
249 /* Spansion -- single (large) sector size only, at least
250 * for the chips listed here (without boot sectors).
251 */
252 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
253 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
254 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
255 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
256 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
257 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
258 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
259 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
260 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
261 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
262 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
263 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
264 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
265 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
266 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
267 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
268 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
269
270 /* Spansion -- boot sectors support */
271 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
272 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
273
274 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
275 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
276 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
277 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
278 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
279 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
280 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
281 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
282 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
283 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
284
285 /* ST Microelectronics -- newer production may have feature updates */
286 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
287 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
288 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
289 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
290 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
291 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
292 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
293 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
294 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
295 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
296
297 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
298 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
299 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
300
301 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
302 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
303 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
304
305 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
306 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
307 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
308 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
309
310 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
311 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
312 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
313 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
314 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
315 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
316 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
317 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
318 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
319 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
320 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
321 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
322 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
323 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
324 };
325
326 typedef enum {
327 NOP = 0,
328 WRSR = 0x1,
329 WRDI = 0x4,
330 RDSR = 0x5,
331 WREN = 0x6,
332 JEDEC_READ = 0x9f,
333 BULK_ERASE = 0xc7,
334 READ_FSR = 0x70,
335 RDCR = 0x15,
336
337 READ = 0x03,
338 READ4 = 0x13,
339 FAST_READ = 0x0b,
340 FAST_READ4 = 0x0c,
341 DOR = 0x3b,
342 DOR4 = 0x3c,
343 QOR = 0x6b,
344 QOR4 = 0x6c,
345 DIOR = 0xbb,
346 DIOR4 = 0xbc,
347 QIOR = 0xeb,
348 QIOR4 = 0xec,
349
350 PP = 0x02,
351 PP4 = 0x12,
352 PP4_4 = 0x3e,
353 DPP = 0xa2,
354 QPP = 0x32,
355 QPP_4 = 0x34,
356
357 ERASE_4K = 0x20,
358 ERASE4_4K = 0x21,
359 ERASE_32K = 0x52,
360 ERASE4_32K = 0x5c,
361 ERASE_SECTOR = 0xd8,
362 ERASE4_SECTOR = 0xdc,
363
364 EN_4BYTE_ADDR = 0xB7,
365 EX_4BYTE_ADDR = 0xE9,
366
367 EXTEND_ADDR_READ = 0xC8,
368 EXTEND_ADDR_WRITE = 0xC5,
369
370 RESET_ENABLE = 0x66,
371 RESET_MEMORY = 0x99,
372
373 /*
374 * Micron: 0x35 - enable QPI
375 * Spansion: 0x35 - read control register
376 */
377 RDCR_EQIO = 0x35,
378 RSTQIO = 0xf5,
379
380 RNVCR = 0xB5,
381 WNVCR = 0xB1,
382
383 RVCR = 0x85,
384 WVCR = 0x81,
385
386 REVCR = 0x65,
387 WEVCR = 0x61,
388
389 DIE_ERASE = 0xC4,
390 } FlashCMD;
391
392 typedef enum {
393 STATE_IDLE,
394 STATE_PAGE_PROGRAM,
395 STATE_READ,
396 STATE_COLLECTING_DATA,
397 STATE_COLLECTING_VAR_LEN_DATA,
398 STATE_READING_DATA,
399 } CMDState;
400
401 typedef enum {
402 MAN_SPANSION,
403 MAN_MACRONIX,
404 MAN_NUMONYX,
405 MAN_WINBOND,
406 MAN_GENERIC,
407 } Manufacturer;
408
409 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
410
411 typedef struct Flash {
412 SSISlave parent_obj;
413
414 BlockBackend *blk;
415
416 uint8_t *storage;
417 uint32_t size;
418 int page_size;
419
420 uint8_t state;
421 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ];
422 uint32_t len;
423 uint32_t pos;
424 uint8_t needed_bytes;
425 uint8_t cmd_in_progress;
426 uint32_t cur_addr;
427 uint32_t nonvolatile_cfg;
428 /* Configuration register for Macronix */
429 uint32_t volatile_cfg;
430 uint32_t enh_volatile_cfg;
431 /* Spansion cfg registers. */
432 uint8_t spansion_cr1nv;
433 uint8_t spansion_cr2nv;
434 uint8_t spansion_cr3nv;
435 uint8_t spansion_cr4nv;
436 uint8_t spansion_cr1v;
437 uint8_t spansion_cr2v;
438 uint8_t spansion_cr3v;
439 uint8_t spansion_cr4v;
440 bool write_enable;
441 bool four_bytes_address_mode;
442 bool reset_enable;
443 bool quad_enable;
444 uint8_t ear;
445
446 int64_t dirty_page;
447
448 const FlashPartInfo *pi;
449
450 } Flash;
451
452 typedef struct M25P80Class {
453 SSISlaveClass parent_class;
454 FlashPartInfo *pi;
455 } M25P80Class;
456
457 #define TYPE_M25P80 "m25p80-generic"
458 #define M25P80(obj) \
459 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
460 #define M25P80_CLASS(klass) \
461 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
462 #define M25P80_GET_CLASS(obj) \
463 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
464
465 static inline Manufacturer get_man(Flash *s)
466 {
467 switch (s->pi->id[0]) {
468 case 0x20:
469 return MAN_NUMONYX;
470 case 0xEF:
471 return MAN_WINBOND;
472 case 0x01:
473 return MAN_SPANSION;
474 case 0xC2:
475 return MAN_MACRONIX;
476 default:
477 return MAN_GENERIC;
478 }
479 }
480
481 static void blk_sync_complete(void *opaque, int ret)
482 {
483 QEMUIOVector *iov = opaque;
484
485 qemu_iovec_destroy(iov);
486 g_free(iov);
487
488 /* do nothing. Masters do not directly interact with the backing store,
489 * only the working copy so no mutexing required.
490 */
491 }
492
493 static void flash_sync_page(Flash *s, int page)
494 {
495 QEMUIOVector *iov;
496
497 if (!s->blk || blk_is_read_only(s->blk)) {
498 return;
499 }
500
501 iov = g_new(QEMUIOVector, 1);
502 qemu_iovec_init(iov, 1);
503 qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
504 s->pi->page_size);
505 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
506 blk_sync_complete, iov);
507 }
508
509 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
510 {
511 QEMUIOVector *iov;
512
513 if (!s->blk || blk_is_read_only(s->blk)) {
514 return;
515 }
516
517 assert(!(len % BDRV_SECTOR_SIZE));
518 iov = g_new(QEMUIOVector, 1);
519 qemu_iovec_init(iov, 1);
520 qemu_iovec_add(iov, s->storage + off, len);
521 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
522 }
523
524 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
525 {
526 uint32_t len;
527 uint8_t capa_to_assert = 0;
528
529 switch (cmd) {
530 case ERASE_4K:
531 case ERASE4_4K:
532 len = 4 << 10;
533 capa_to_assert = ER_4K;
534 break;
535 case ERASE_32K:
536 case ERASE4_32K:
537 len = 32 << 10;
538 capa_to_assert = ER_32K;
539 break;
540 case ERASE_SECTOR:
541 case ERASE4_SECTOR:
542 len = s->pi->sector_size;
543 break;
544 case BULK_ERASE:
545 len = s->size;
546 break;
547 case DIE_ERASE:
548 if (s->pi->die_cnt) {
549 len = s->size / s->pi->die_cnt;
550 offset = offset & (~(len - 1));
551 } else {
552 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported"
553 " by device\n");
554 return;
555 }
556 break;
557 default:
558 abort();
559 }
560
561 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
562 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
563 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
564 " device\n", len);
565 }
566
567 if (!s->write_enable) {
568 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
569 return;
570 }
571 memset(s->storage + offset, 0xff, len);
572 flash_sync_area(s, offset, len);
573 }
574
575 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
576 {
577 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
578 flash_sync_page(s, s->dirty_page);
579 s->dirty_page = newpage;
580 }
581 }
582
583 static inline
584 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
585 {
586 uint32_t page = addr / s->pi->page_size;
587 uint8_t prev = s->storage[s->cur_addr];
588
589 if (!s->write_enable) {
590 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
591 }
592
593 if ((prev ^ data) & data) {
594 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 " %" PRIx8
595 " -> %" PRIx8 "\n", addr, prev, data);
596 }
597
598 if (s->pi->flags & EEPROM) {
599 s->storage[s->cur_addr] = data;
600 } else {
601 s->storage[s->cur_addr] &= data;
602 }
603
604 flash_sync_dirty(s, page);
605 s->dirty_page = page;
606 }
607
608 static inline int get_addr_length(Flash *s)
609 {
610 /* check if eeprom is in use */
611 if (s->pi->flags == EEPROM) {
612 return 2;
613 }
614
615 switch (s->cmd_in_progress) {
616 case PP4:
617 case PP4_4:
618 case QPP_4:
619 case READ4:
620 case QIOR4:
621 case ERASE4_4K:
622 case ERASE4_32K:
623 case ERASE4_SECTOR:
624 case FAST_READ4:
625 case DOR4:
626 case QOR4:
627 case DIOR4:
628 return 4;
629 default:
630 return s->four_bytes_address_mode ? 4 : 3;
631 }
632 }
633
634 static void complete_collecting_data(Flash *s)
635 {
636 int i, n;
637
638 n = get_addr_length(s);
639 s->cur_addr = (n == 3 ? s->ear : 0);
640 for (i = 0; i < n; ++i) {
641 s->cur_addr <<= 8;
642 s->cur_addr |= s->data[i];
643 }
644
645 s->cur_addr &= s->size - 1;
646
647 s->state = STATE_IDLE;
648
649 switch (s->cmd_in_progress) {
650 case DPP:
651 case QPP:
652 case QPP_4:
653 case PP:
654 case PP4:
655 case PP4_4:
656 s->state = STATE_PAGE_PROGRAM;
657 break;
658 case READ:
659 case READ4:
660 case FAST_READ:
661 case FAST_READ4:
662 case DOR:
663 case DOR4:
664 case QOR:
665 case QOR4:
666 case DIOR:
667 case DIOR4:
668 case QIOR:
669 case QIOR4:
670 s->state = STATE_READ;
671 break;
672 case ERASE_4K:
673 case ERASE4_4K:
674 case ERASE_32K:
675 case ERASE4_32K:
676 case ERASE_SECTOR:
677 case ERASE4_SECTOR:
678 case DIE_ERASE:
679 flash_erase(s, s->cur_addr, s->cmd_in_progress);
680 break;
681 case WRSR:
682 switch (get_man(s)) {
683 case MAN_SPANSION:
684 s->quad_enable = !!(s->data[1] & 0x02);
685 break;
686 case MAN_MACRONIX:
687 s->quad_enable = extract32(s->data[0], 6, 1);
688 if (s->len > 1) {
689 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
690 }
691 break;
692 default:
693 break;
694 }
695 if (s->write_enable) {
696 s->write_enable = false;
697 }
698 break;
699 case EXTEND_ADDR_WRITE:
700 s->ear = s->data[0];
701 break;
702 case WNVCR:
703 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
704 break;
705 case WVCR:
706 s->volatile_cfg = s->data[0];
707 break;
708 case WEVCR:
709 s->enh_volatile_cfg = s->data[0];
710 break;
711 default:
712 break;
713 }
714 }
715
716 static void reset_memory(Flash *s)
717 {
718 s->cmd_in_progress = NOP;
719 s->cur_addr = 0;
720 s->ear = 0;
721 s->four_bytes_address_mode = false;
722 s->len = 0;
723 s->needed_bytes = 0;
724 s->pos = 0;
725 s->state = STATE_IDLE;
726 s->write_enable = false;
727 s->reset_enable = false;
728 s->quad_enable = false;
729
730 switch (get_man(s)) {
731 case MAN_NUMONYX:
732 s->volatile_cfg = 0;
733 s->volatile_cfg |= VCFG_DUMMY;
734 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
735 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
736 != NVCFG_XIP_MODE_DISABLED) {
737 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED;
738 }
739 s->volatile_cfg |= deposit32(s->volatile_cfg,
740 VCFG_DUMMY_CLK_POS,
741 CFG_DUMMY_CLK_LEN,
742 extract32(s->nonvolatile_cfg,
743 NVCFG_DUMMY_CLK_POS,
744 CFG_DUMMY_CLK_LEN)
745 );
746
747 s->enh_volatile_cfg = 0;
748 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF;
749 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
750 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
751 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
752 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
753 }
754 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
755 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
756 }
757 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
758 s->four_bytes_address_mode = true;
759 }
760 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
761 s->ear = s->size / MAX_3BYTES_SIZE - 1;
762 }
763 break;
764 case MAN_MACRONIX:
765 s->volatile_cfg = 0x7;
766 break;
767 case MAN_SPANSION:
768 s->spansion_cr1v = s->spansion_cr1nv;
769 s->spansion_cr2v = s->spansion_cr2nv;
770 s->spansion_cr3v = s->spansion_cr3nv;
771 s->spansion_cr4v = s->spansion_cr4nv;
772 s->quad_enable = extract32(s->spansion_cr1v,
773 SPANSION_QUAD_CFG_POS,
774 SPANSION_QUAD_CFG_LEN
775 );
776 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
777 SPANSION_ADDR_LEN_POS,
778 SPANSION_ADDR_LEN_LEN
779 );
780 break;
781 default:
782 break;
783 }
784
785 DB_PRINT_L(0, "Reset done.\n");
786 }
787
788 static void decode_fast_read_cmd(Flash *s)
789 {
790 s->needed_bytes = get_addr_length(s);
791 switch (get_man(s)) {
792 /* Dummy cycles - modeled with bytes writes instead of bits */
793 case MAN_WINBOND:
794 s->needed_bytes += 8;
795 break;
796 case MAN_NUMONYX:
797 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
798 break;
799 case MAN_MACRONIX:
800 if (extract32(s->volatile_cfg, 6, 2) == 1) {
801 s->needed_bytes += 6;
802 } else {
803 s->needed_bytes += 8;
804 }
805 break;
806 case MAN_SPANSION:
807 s->needed_bytes += extract32(s->spansion_cr2v,
808 SPANSION_DUMMY_CLK_POS,
809 SPANSION_DUMMY_CLK_LEN
810 );
811 break;
812 default:
813 break;
814 }
815 s->pos = 0;
816 s->len = 0;
817 s->state = STATE_COLLECTING_DATA;
818 }
819
820 static void decode_dio_read_cmd(Flash *s)
821 {
822 s->needed_bytes = get_addr_length(s);
823 /* Dummy cycles modeled with bytes writes instead of bits */
824 switch (get_man(s)) {
825 case MAN_WINBOND:
826 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
827 break;
828 case MAN_SPANSION:
829 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
830 s->needed_bytes += extract32(s->spansion_cr2v,
831 SPANSION_DUMMY_CLK_POS,
832 SPANSION_DUMMY_CLK_LEN
833 );
834 break;
835 case MAN_NUMONYX:
836 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
837 break;
838 case MAN_MACRONIX:
839 switch (extract32(s->volatile_cfg, 6, 2)) {
840 case 1:
841 s->needed_bytes += 6;
842 break;
843 case 2:
844 s->needed_bytes += 8;
845 break;
846 default:
847 s->needed_bytes += 4;
848 break;
849 }
850 break;
851 default:
852 break;
853 }
854 s->pos = 0;
855 s->len = 0;
856 s->state = STATE_COLLECTING_DATA;
857 }
858
859 static void decode_qio_read_cmd(Flash *s)
860 {
861 s->needed_bytes = get_addr_length(s);
862 /* Dummy cycles modeled with bytes writes instead of bits */
863 switch (get_man(s)) {
864 case MAN_WINBOND:
865 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
866 s->needed_bytes += 4;
867 break;
868 case MAN_SPANSION:
869 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
870 s->needed_bytes += extract32(s->spansion_cr2v,
871 SPANSION_DUMMY_CLK_POS,
872 SPANSION_DUMMY_CLK_LEN
873 );
874 break;
875 case MAN_NUMONYX:
876 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
877 break;
878 case MAN_MACRONIX:
879 switch (extract32(s->volatile_cfg, 6, 2)) {
880 case 1:
881 s->needed_bytes += 4;
882 break;
883 case 2:
884 s->needed_bytes += 8;
885 break;
886 default:
887 s->needed_bytes += 6;
888 break;
889 }
890 break;
891 default:
892 break;
893 }
894 s->pos = 0;
895 s->len = 0;
896 s->state = STATE_COLLECTING_DATA;
897 }
898
899 static void decode_new_cmd(Flash *s, uint32_t value)
900 {
901 s->cmd_in_progress = value;
902 int i;
903 DB_PRINT_L(0, "decoded new command:%x\n", value);
904
905 if (value != RESET_MEMORY) {
906 s->reset_enable = false;
907 }
908
909 switch (value) {
910
911 case ERASE_4K:
912 case ERASE4_4K:
913 case ERASE_32K:
914 case ERASE4_32K:
915 case ERASE_SECTOR:
916 case ERASE4_SECTOR:
917 case READ:
918 case READ4:
919 case DPP:
920 case QPP:
921 case QPP_4:
922 case PP:
923 case PP4:
924 case PP4_4:
925 case DIE_ERASE:
926 s->needed_bytes = get_addr_length(s);
927 s->pos = 0;
928 s->len = 0;
929 s->state = STATE_COLLECTING_DATA;
930 break;
931
932 case FAST_READ:
933 case FAST_READ4:
934 case DOR:
935 case DOR4:
936 case QOR:
937 case QOR4:
938 decode_fast_read_cmd(s);
939 break;
940
941 case DIOR:
942 case DIOR4:
943 decode_dio_read_cmd(s);
944 break;
945
946 case QIOR:
947 case QIOR4:
948 decode_qio_read_cmd(s);
949 break;
950
951 case WRSR:
952 if (s->write_enable) {
953 switch (get_man(s)) {
954 case MAN_SPANSION:
955 s->needed_bytes = 2;
956 s->state = STATE_COLLECTING_DATA;
957 break;
958 case MAN_MACRONIX:
959 s->needed_bytes = 2;
960 s->state = STATE_COLLECTING_VAR_LEN_DATA;
961 break;
962 default:
963 s->needed_bytes = 1;
964 s->state = STATE_COLLECTING_DATA;
965 }
966 s->pos = 0;
967 }
968 break;
969
970 case WRDI:
971 s->write_enable = false;
972 break;
973 case WREN:
974 s->write_enable = true;
975 break;
976
977 case RDSR:
978 s->data[0] = (!!s->write_enable) << 1;
979 if (get_man(s) == MAN_MACRONIX) {
980 s->data[0] |= (!!s->quad_enable) << 6;
981 }
982 s->pos = 0;
983 s->len = 1;
984 s->state = STATE_READING_DATA;
985 break;
986
987 case READ_FSR:
988 s->data[0] = FSR_FLASH_READY;
989 if (s->four_bytes_address_mode) {
990 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
991 }
992 s->pos = 0;
993 s->len = 1;
994 s->state = STATE_READING_DATA;
995 break;
996
997 case JEDEC_READ:
998 DB_PRINT_L(0, "populated jedec code\n");
999 for (i = 0; i < s->pi->id_len; i++) {
1000 s->data[i] = s->pi->id[i];
1001 }
1002
1003 s->len = s->pi->id_len;
1004 s->pos = 0;
1005 s->state = STATE_READING_DATA;
1006 break;
1007
1008 case RDCR:
1009 s->data[0] = s->volatile_cfg & 0xFF;
1010 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
1011 s->pos = 0;
1012 s->len = 1;
1013 s->state = STATE_READING_DATA;
1014 break;
1015
1016 case BULK_ERASE:
1017 if (s->write_enable) {
1018 DB_PRINT_L(0, "chip erase\n");
1019 flash_erase(s, 0, BULK_ERASE);
1020 } else {
1021 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
1022 "protect!\n");
1023 }
1024 break;
1025 case NOP:
1026 break;
1027 case EN_4BYTE_ADDR:
1028 s->four_bytes_address_mode = true;
1029 break;
1030 case EX_4BYTE_ADDR:
1031 s->four_bytes_address_mode = false;
1032 break;
1033 case EXTEND_ADDR_READ:
1034 s->data[0] = s->ear;
1035 s->pos = 0;
1036 s->len = 1;
1037 s->state = STATE_READING_DATA;
1038 break;
1039 case EXTEND_ADDR_WRITE:
1040 if (s->write_enable) {
1041 s->needed_bytes = 1;
1042 s->pos = 0;
1043 s->len = 0;
1044 s->state = STATE_COLLECTING_DATA;
1045 }
1046 break;
1047 case RNVCR:
1048 s->data[0] = s->nonvolatile_cfg & 0xFF;
1049 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1050 s->pos = 0;
1051 s->len = 2;
1052 s->state = STATE_READING_DATA;
1053 break;
1054 case WNVCR:
1055 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1056 s->needed_bytes = 2;
1057 s->pos = 0;
1058 s->len = 0;
1059 s->state = STATE_COLLECTING_DATA;
1060 }
1061 break;
1062 case RVCR:
1063 s->data[0] = s->volatile_cfg & 0xFF;
1064 s->pos = 0;
1065 s->len = 1;
1066 s->state = STATE_READING_DATA;
1067 break;
1068 case WVCR:
1069 if (s->write_enable) {
1070 s->needed_bytes = 1;
1071 s->pos = 0;
1072 s->len = 0;
1073 s->state = STATE_COLLECTING_DATA;
1074 }
1075 break;
1076 case REVCR:
1077 s->data[0] = s->enh_volatile_cfg & 0xFF;
1078 s->pos = 0;
1079 s->len = 1;
1080 s->state = STATE_READING_DATA;
1081 break;
1082 case WEVCR:
1083 if (s->write_enable) {
1084 s->needed_bytes = 1;
1085 s->pos = 0;
1086 s->len = 0;
1087 s->state = STATE_COLLECTING_DATA;
1088 }
1089 break;
1090 case RESET_ENABLE:
1091 s->reset_enable = true;
1092 break;
1093 case RESET_MEMORY:
1094 if (s->reset_enable) {
1095 reset_memory(s);
1096 }
1097 break;
1098 case RDCR_EQIO:
1099 switch (get_man(s)) {
1100 case MAN_SPANSION:
1101 s->data[0] = (!!s->quad_enable) << 1;
1102 s->pos = 0;
1103 s->len = 1;
1104 s->state = STATE_READING_DATA;
1105 break;
1106 case MAN_MACRONIX:
1107 s->quad_enable = true;
1108 break;
1109 default:
1110 break;
1111 }
1112 break;
1113 case RSTQIO:
1114 s->quad_enable = false;
1115 break;
1116 default:
1117 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1118 break;
1119 }
1120 }
1121
1122 static int m25p80_cs(SSISlave *ss, bool select)
1123 {
1124 Flash *s = M25P80(ss);
1125
1126 if (select) {
1127 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1128 complete_collecting_data(s);
1129 }
1130 s->len = 0;
1131 s->pos = 0;
1132 s->state = STATE_IDLE;
1133 flash_sync_dirty(s, -1);
1134 }
1135
1136 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
1137
1138 return 0;
1139 }
1140
1141 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
1142 {
1143 Flash *s = M25P80(ss);
1144 uint32_t r = 0;
1145
1146 switch (s->state) {
1147
1148 case STATE_PAGE_PROGRAM:
1149 DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n",
1150 s->cur_addr, (uint8_t)tx);
1151 flash_write8(s, s->cur_addr, (uint8_t)tx);
1152 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1153 break;
1154
1155 case STATE_READ:
1156 r = s->storage[s->cur_addr];
1157 DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr,
1158 (uint8_t)r);
1159 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1160 break;
1161
1162 case STATE_COLLECTING_DATA:
1163 case STATE_COLLECTING_VAR_LEN_DATA:
1164
1165 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1166 qemu_log_mask(LOG_GUEST_ERROR,
1167 "M25P80: Write overrun internal data buffer. "
1168 "SPI controller (QEMU emulator or guest driver) "
1169 "is misbehaving\n");
1170 s->len = s->pos = 0;
1171 s->state = STATE_IDLE;
1172 break;
1173 }
1174
1175 s->data[s->len] = (uint8_t)tx;
1176 s->len++;
1177
1178 if (s->len == s->needed_bytes) {
1179 complete_collecting_data(s);
1180 }
1181 break;
1182
1183 case STATE_READING_DATA:
1184
1185 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1186 qemu_log_mask(LOG_GUEST_ERROR,
1187 "M25P80: Read overrun internal data buffer. "
1188 "SPI controller (QEMU emulator or guest driver) "
1189 "is misbehaving\n");
1190 s->len = s->pos = 0;
1191 s->state = STATE_IDLE;
1192 break;
1193 }
1194
1195 r = s->data[s->pos];
1196 s->pos++;
1197 if (s->pos == s->len) {
1198 s->pos = 0;
1199 s->state = STATE_IDLE;
1200 }
1201 break;
1202
1203 default:
1204 case STATE_IDLE:
1205 decode_new_cmd(s, (uint8_t)tx);
1206 break;
1207 }
1208
1209 return r;
1210 }
1211
1212 static void m25p80_realize(SSISlave *ss, Error **errp)
1213 {
1214 Flash *s = M25P80(ss);
1215 M25P80Class *mc = M25P80_GET_CLASS(s);
1216
1217 s->pi = mc->pi;
1218
1219 s->size = s->pi->sector_size * s->pi->n_sectors;
1220 s->dirty_page = -1;
1221
1222 if (s->blk) {
1223 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
1224 s->storage = blk_blockalign(s->blk, s->size);
1225
1226 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
1227 error_setg(errp, "failed to read the initial flash content");
1228 return;
1229 }
1230 } else {
1231 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
1232 s->storage = blk_blockalign(NULL, s->size);
1233 memset(s->storage, 0xFF, s->size);
1234 }
1235 }
1236
1237 static void m25p80_reset(DeviceState *d)
1238 {
1239 Flash *s = M25P80(d);
1240
1241 reset_memory(s);
1242 }
1243
1244 static void m25p80_pre_save(void *opaque)
1245 {
1246 flash_sync_dirty((Flash *)opaque, -1);
1247 }
1248
1249 static Property m25p80_properties[] = {
1250 /* This is default value for Micron flash */
1251 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1252 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1253 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1254 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1255 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1256 DEFINE_PROP_DRIVE("drive", Flash, blk),
1257 DEFINE_PROP_END_OF_LIST(),
1258 };
1259
1260 static const VMStateDescription vmstate_m25p80 = {
1261 .name = "m25p80",
1262 .version_id = 0,
1263 .minimum_version_id = 0,
1264 .pre_save = m25p80_pre_save,
1265 .fields = (VMStateField[]) {
1266 VMSTATE_UINT8(state, Flash),
1267 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
1268 VMSTATE_UINT32(len, Flash),
1269 VMSTATE_UINT32(pos, Flash),
1270 VMSTATE_UINT8(needed_bytes, Flash),
1271 VMSTATE_UINT8(cmd_in_progress, Flash),
1272 VMSTATE_UINT32(cur_addr, Flash),
1273 VMSTATE_BOOL(write_enable, Flash),
1274 VMSTATE_BOOL(reset_enable, Flash),
1275 VMSTATE_UINT8(ear, Flash),
1276 VMSTATE_BOOL(four_bytes_address_mode, Flash),
1277 VMSTATE_UINT32(nonvolatile_cfg, Flash),
1278 VMSTATE_UINT32(volatile_cfg, Flash),
1279 VMSTATE_UINT32(enh_volatile_cfg, Flash),
1280 VMSTATE_BOOL(quad_enable, Flash),
1281 VMSTATE_UINT8(spansion_cr1nv, Flash),
1282 VMSTATE_UINT8(spansion_cr2nv, Flash),
1283 VMSTATE_UINT8(spansion_cr3nv, Flash),
1284 VMSTATE_UINT8(spansion_cr4nv, Flash),
1285 VMSTATE_END_OF_LIST()
1286 }
1287 };
1288
1289 static void m25p80_class_init(ObjectClass *klass, void *data)
1290 {
1291 DeviceClass *dc = DEVICE_CLASS(klass);
1292 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
1293 M25P80Class *mc = M25P80_CLASS(klass);
1294
1295 k->realize = m25p80_realize;
1296 k->transfer = m25p80_transfer8;
1297 k->set_cs = m25p80_cs;
1298 k->cs_polarity = SSI_CS_LOW;
1299 dc->vmsd = &vmstate_m25p80;
1300 dc->props = m25p80_properties;
1301 dc->reset = m25p80_reset;
1302 mc->pi = data;
1303 }
1304
1305 static const TypeInfo m25p80_info = {
1306 .name = TYPE_M25P80,
1307 .parent = TYPE_SSI_SLAVE,
1308 .instance_size = sizeof(Flash),
1309 .class_size = sizeof(M25P80Class),
1310 .abstract = true,
1311 };
1312
1313 static void m25p80_register_types(void)
1314 {
1315 int i;
1316
1317 type_register_static(&m25p80_info);
1318 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1319 TypeInfo ti = {
1320 .name = known_devices[i].part_name,
1321 .parent = TYPE_M25P80,
1322 .class_init = m25p80_class_init,
1323 .class_data = (void *)&known_devices[i],
1324 };
1325 type_register(&ti);
1326 }
1327 }
1328
1329 type_init(m25p80_register_types)
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