hw/block/nvme.c

   1 /*
   2  * QEMU NVM Express Controller
   3  *
   4  * Copyright (c) 2012, Intel Corporation
   5  *
   6  * Written by Keith Busch <keith.busch@intel.com>
   7  *
   8  * This code is licensed under the GNU GPL v2 or later.
   9  */
  10
  11 /**
  12  * Reference Specs: http://www.nvmexpress.org, 1.1, 1.0e
  13  *
  14  *  http://www.nvmexpress.org/resources/
  15  */
  16
  17 /**
  18  * Usage: add options:
  19  *      -drive file=<file>,if=none,id=<drive_id>
  20  *      -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>
  21  */
  22
  23 #include <hw/block/block.h>
  24 #include <hw/hw.h>
  25 #include <hw/pci/msix.h>
  26 #include <hw/pci/pci.h>
  27 #include "sysemu/sysemu.h"
  28 #include "qapi/visitor.h"
  29 #include "sysemu/block-backend.h"
  30
  31 #include "nvme.h"
  32
  33 static void nvme_process_sq(void *opaque);
  34
  35 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
  36 {
  37     return sqid < n->num_queues && n->sq[sqid] != NULL ? 0 : -1;
  38 }
  39
  40 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
  41 {
  42     return cqid < n->num_queues && n->cq[cqid] != NULL ? 0 : -1;
  43 }
  44
  45 static void nvme_inc_cq_tail(NvmeCQueue *cq)
  46 {
  47     cq->tail++;
  48     if (cq->tail >= cq->size) {
  49         cq->tail = 0;
  50         cq->phase = !cq->phase;
  51     }
  52 }
  53
  54 static void nvme_inc_sq_head(NvmeSQueue *sq)
  55 {
  56     sq->head = (sq->head + 1) % sq->size;
  57 }
  58
  59 static uint8_t nvme_cq_full(NvmeCQueue *cq)
  60 {
  61     return (cq->tail + 1) % cq->size == cq->head;
  62 }
  63
  64 static uint8_t nvme_sq_empty(NvmeSQueue *sq)
  65 {
  66     return sq->head == sq->tail;
  67 }
  68
  69 static void nvme_isr_notify(NvmeCtrl *n, NvmeCQueue *cq)
  70 {
  71     if (cq->irq_enabled) {
  72         if (msix_enabled(&(n->parent_obj))) {
  73             msix_notify(&(n->parent_obj), cq->vector);
  74         } else {
  75             pci_irq_pulse(&n->parent_obj);
  76         }
  77     }
  78 }
  79
  80 static uint16_t nvme_map_prp(QEMUSGList *qsg, uint64_t prp1, uint64_t prp2,
  81     uint32_t len, NvmeCtrl *n)
  82 {
  83     hwaddr trans_len = n->page_size - (prp1 % n->page_size);
  84     trans_len = MIN(len, trans_len);
  85     int num_prps = (len >> n->page_bits) + 1;
  86
  87     if (!prp1) {
  88         return NVME_INVALID_FIELD | NVME_DNR;
  89     }
  90
  91     pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
  92     qemu_sglist_add(qsg, prp1, trans_len);
  93     len -= trans_len;
  94     if (len) {
  95         if (!prp2) {
  96             goto unmap;
  97         }
  98         if (len > n->page_size) {
  99             uint64_t prp_list[n->max_prp_ents];
 100             uint32_t nents, prp_trans;
 101             int i = 0;
 102
 103             nents = (len + n->page_size - 1) >> n->page_bits;
 104             prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
 105             pci_dma_read(&n->parent_obj, prp2, (void *)prp_list, prp_trans);
 106             while (len != 0) {
 107                 uint64_t prp_ent = le64_to_cpu(prp_list[i]);
 108
 109                 if (i == n->max_prp_ents - 1 && len > n->page_size) {
 110                     if (!prp_ent || prp_ent & (n->page_size - 1)) {
 111                         goto unmap;
 112                     }
 113
 114                     i = 0;
 115                     nents = (len + n->page_size - 1) >> n->page_bits;
 116                     prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
 117                     pci_dma_read(&n->parent_obj, prp_ent, (void *)prp_list,
 118                         prp_trans);
 119                     prp_ent = le64_to_cpu(prp_list[i]);
 120                 }
 121
 122                 if (!prp_ent || prp_ent & (n->page_size - 1)) {
 123                     goto unmap;
 124                 }
 125
 126                 trans_len = MIN(len, n->page_size);
 127                 qemu_sglist_add(qsg, prp_ent, trans_len);
 128                 len -= trans_len;
 129                 i++;
 130             }
 131         } else {
 132             if (prp2 & (n->page_size - 1)) {
 133                 goto unmap;
 134             }
 135             qemu_sglist_add(qsg, prp2, len);
 136         }
 137     }
 138     return NVME_SUCCESS;
 139
 140  unmap:
 141     qemu_sglist_destroy(qsg);
 142     return NVME_INVALID_FIELD | NVME_DNR;
 143 }
 144
 145 static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
 146     uint64_t prp1, uint64_t prp2)
 147 {
 148     QEMUSGList qsg;
 149
 150     if (nvme_map_prp(&qsg, prp1, prp2, len, n)) {
 151         return NVME_INVALID_FIELD | NVME_DNR;
 152     }
 153     if (dma_buf_read(ptr, len, &qsg)) {
 154         qemu_sglist_destroy(&qsg);
 155         return NVME_INVALID_FIELD | NVME_DNR;
 156     }
 157     qemu_sglist_destroy(&qsg);
 158     return NVME_SUCCESS;
 159 }
 160
 161 static void nvme_post_cqes(void *opaque)
 162 {
 163     NvmeCQueue *cq = opaque;
 164     NvmeCtrl *n = cq->ctrl;
 165     NvmeRequest *req, *next;
 166
 167     QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
 168         NvmeSQueue *sq;
 169         hwaddr addr;
 170
 171         if (nvme_cq_full(cq)) {
 172             break;
 173         }
 174
 175         QTAILQ_REMOVE(&cq->req_list, req, entry);
 176         sq = req->sq;
 177         req->cqe.status = cpu_to_le16((req->status << 1) | cq->phase);
 178         req->cqe.sq_id = cpu_to_le16(sq->sqid);
 179         req->cqe.sq_head = cpu_to_le16(sq->head);
 180         addr = cq->dma_addr + cq->tail * n->cqe_size;
 181         nvme_inc_cq_tail(cq);
 182         pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
 183             sizeof(req->cqe));
 184         QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
 185     }
 186     nvme_isr_notify(n, cq);
 187 }
 188
 189 static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
 190 {
 191     assert(cq->cqid == req->sq->cqid);
 192     QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
 193     QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
 194     timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 195 }
 196
 197 static void nvme_rw_cb(void *opaque, int ret)
 198 {
 199     NvmeRequest *req = opaque;
 200     NvmeSQueue *sq = req->sq;
 201     NvmeCtrl *n = sq->ctrl;
 202     NvmeCQueue *cq = n->cq[sq->cqid];
 203
 204     if (!ret) {
 205         block_acct_done(blk_get_stats(n->conf.blk), &req->acct);
 206         req->status = NVME_SUCCESS;
 207     } else {
 208         block_acct_failed(blk_get_stats(n->conf.blk), &req->acct);
 209         req->status = NVME_INTERNAL_DEV_ERROR;
 210     }
 211     if (req->has_sg) {
 212         qemu_sglist_destroy(&req->qsg);
 213     }
 214     nvme_enqueue_req_completion(cq, req);
 215 }
 216
 217 static uint16_t nvme_flush(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
 218     NvmeRequest *req)
 219 {
 220     req->has_sg = false;
 221     block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
 222          BLOCK_ACCT_FLUSH);
 223     req->aiocb = blk_aio_flush(n->conf.blk, nvme_rw_cb, req);
 224
 225     return NVME_NO_COMPLETE;
 226 }
 227
 228 static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
 229     NvmeRequest *req)
 230 {
 231     NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
 232     uint32_t nlb  = le32_to_cpu(rw->nlb) + 1;
 233     uint64_t slba = le64_to_cpu(rw->slba);
 234     uint64_t prp1 = le64_to_cpu(rw->prp1);
 235     uint64_t prp2 = le64_to_cpu(rw->prp2);
 236
 237     uint8_t lba_index  = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
 238     uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
 239     uint64_t data_size = (uint64_t)nlb << data_shift;
 240     uint64_t aio_slba  = slba << (data_shift - BDRV_SECTOR_BITS);
 241     int is_write = rw->opcode == NVME_CMD_WRITE ? 1 : 0;
 242     enum BlockAcctType acct = is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ;
 243
 244     if ((slba + nlb) > ns->id_ns.nsze) {
 245         block_acct_invalid(blk_get_stats(n->conf.blk), acct);
 246         return NVME_LBA_RANGE | NVME_DNR;
 247     }
 248
 249     if (nvme_map_prp(&req->qsg, prp1, prp2, data_size, n)) {
 250         block_acct_invalid(blk_get_stats(n->conf.blk), acct);
 251         return NVME_INVALID_FIELD | NVME_DNR;
 252     }
 253
 254     assert((nlb << data_shift) == req->qsg.size);
 255
 256     req->has_sg = true;
 257     dma_acct_start(n->conf.blk, &req->acct, &req->qsg, acct);
 258     req->aiocb = is_write ?
 259         dma_blk_write(n->conf.blk, &req->qsg, aio_slba, nvme_rw_cb, req) :
 260         dma_blk_read(n->conf.blk, &req->qsg, aio_slba, nvme_rw_cb, req);
 261
 262     return NVME_NO_COMPLETE;
 263 }
 264
 265 static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 266 {
 267     NvmeNamespace *ns;
 268     uint32_t nsid = le32_to_cpu(cmd->nsid);
 269
 270     if (nsid == 0 || nsid > n->num_namespaces) {
 271         return NVME_INVALID_NSID | NVME_DNR;
 272     }
 273
 274     ns = &n->namespaces[nsid - 1];
 275     switch (cmd->opcode) {
 276     case NVME_CMD_FLUSH:
 277         return nvme_flush(n, ns, cmd, req);
 278     case NVME_CMD_WRITE:
 279     case NVME_CMD_READ:
 280         return nvme_rw(n, ns, cmd, req);
 281     default:
 282         return NVME_INVALID_OPCODE | NVME_DNR;
 283     }
 284 }
 285
 286 static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
 287 {
 288     n->sq[sq->sqid] = NULL;
 289     timer_del(sq->timer);
 290     timer_free(sq->timer);
 291     g_free(sq->io_req);
 292     if (sq->sqid) {
 293         g_free(sq);
 294     }
 295 }
 296
 297 static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeCmd *cmd)
 298 {
 299     NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
 300     NvmeRequest *req, *next;
 301     NvmeSQueue *sq;
 302     NvmeCQueue *cq;
 303     uint16_t qid = le16_to_cpu(c->qid);
 304
 305     if (!qid || nvme_check_sqid(n, qid)) {
 306         return NVME_INVALID_QID | NVME_DNR;
 307     }
 308
 309     sq = n->sq[qid];
 310     while (!QTAILQ_EMPTY(&sq->out_req_list)) {
 311         req = QTAILQ_FIRST(&sq->out_req_list);
 312         assert(req->aiocb);
 313         blk_aio_cancel(req->aiocb);
 314     }
 315     if (!nvme_check_cqid(n, sq->cqid)) {
 316         cq = n->cq[sq->cqid];
 317         QTAILQ_REMOVE(&cq->sq_list, sq, entry);
 318
 319         nvme_post_cqes(cq);
 320         QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
 321             if (req->sq == sq) {
 322                 QTAILQ_REMOVE(&cq->req_list, req, entry);
 323                 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
 324             }
 325         }
 326     }
 327
 328     nvme_free_sq(sq, n);
 329     return NVME_SUCCESS;
 330 }
 331
 332 static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
 333     uint16_t sqid, uint16_t cqid, uint16_t size)
 334 {
 335     int i;
 336     NvmeCQueue *cq;
 337
 338     sq->ctrl = n;
 339     sq->dma_addr = dma_addr;
 340     sq->sqid = sqid;
 341     sq->size = size;
 342     sq->cqid = cqid;
 343     sq->head = sq->tail = 0;
 344     sq->io_req = g_new(NvmeRequest, sq->size);
 345
 346     QTAILQ_INIT(&sq->req_list);
 347     QTAILQ_INIT(&sq->out_req_list);
 348     for (i = 0; i < sq->size; i++) {
 349         sq->io_req[i].sq = sq;
 350         QTAILQ_INSERT_TAIL(&(sq->req_list), &sq->io_req[i], entry);
 351     }
 352     sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq);
 353
 354     assert(n->cq[cqid]);
 355     cq = n->cq[cqid];
 356     QTAILQ_INSERT_TAIL(&(cq->sq_list), sq, entry);
 357     n->sq[sqid] = sq;
 358 }
 359
 360 static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeCmd *cmd)
 361 {
 362     NvmeSQueue *sq;
 363     NvmeCreateSq *c = (NvmeCreateSq *)cmd;
 364
 365     uint16_t cqid = le16_to_cpu(c->cqid);
 366     uint16_t sqid = le16_to_cpu(c->sqid);
 367     uint16_t qsize = le16_to_cpu(c->qsize);
 368     uint16_t qflags = le16_to_cpu(c->sq_flags);
 369     uint64_t prp1 = le64_to_cpu(c->prp1);
 370
 371     if (!cqid || nvme_check_cqid(n, cqid)) {
 372         return NVME_INVALID_CQID | NVME_DNR;
 373     }
 374     if (!sqid || (sqid && !nvme_check_sqid(n, sqid))) {
 375         return NVME_INVALID_QID | NVME_DNR;
 376     }
 377     if (!qsize || qsize > NVME_CAP_MQES(n->bar.cap)) {
 378         return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
 379     }
 380     if (!prp1 || prp1 & (n->page_size - 1)) {
 381         return NVME_INVALID_FIELD | NVME_DNR;
 382     }
 383     if (!(NVME_SQ_FLAGS_PC(qflags))) {
 384         return NVME_INVALID_FIELD | NVME_DNR;
 385     }
 386     sq = g_malloc0(sizeof(*sq));
 387     nvme_init_sq(sq, n, prp1, sqid, cqid, qsize + 1);
 388     return NVME_SUCCESS;
 389 }
 390
 391 static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
 392 {
 393     n->cq[cq->cqid] = NULL;
 394     timer_del(cq->timer);
 395     timer_free(cq->timer);
 396     msix_vector_unuse(&n->parent_obj, cq->vector);
 397     if (cq->cqid) {
 398         g_free(cq);
 399     }
 400 }
 401
 402 static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeCmd *cmd)
 403 {
 404     NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
 405     NvmeCQueue *cq;
 406     uint16_t qid = le16_to_cpu(c->qid);
 407
 408     if (!qid || nvme_check_cqid(n, qid)) {
 409         return NVME_INVALID_CQID | NVME_DNR;
 410     }
 411
 412     cq = n->cq[qid];
 413     if (!QTAILQ_EMPTY(&cq->sq_list)) {
 414         return NVME_INVALID_QUEUE_DEL;
 415     }
 416     nvme_free_cq(cq, n);
 417     return NVME_SUCCESS;
 418 }
 419
 420 static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
 421     uint16_t cqid, uint16_t vector, uint16_t size, uint16_t irq_enabled)
 422 {
 423     cq->ctrl = n;
 424     cq->cqid = cqid;
 425     cq->size = size;
 426     cq->dma_addr = dma_addr;
 427     cq->phase = 1;
 428     cq->irq_enabled = irq_enabled;
 429     cq->vector = vector;
 430     cq->head = cq->tail = 0;
 431     QTAILQ_INIT(&cq->req_list);
 432     QTAILQ_INIT(&cq->sq_list);
 433     msix_vector_use(&n->parent_obj, cq->vector);
 434     n->cq[cqid] = cq;
 435     cq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_post_cqes, cq);
 436 }
 437
 438 static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cmd)
 439 {
 440     NvmeCQueue *cq;
 441     NvmeCreateCq *c = (NvmeCreateCq *)cmd;
 442     uint16_t cqid = le16_to_cpu(c->cqid);
 443     uint16_t vector = le16_to_cpu(c->irq_vector);
 444     uint16_t qsize = le16_to_cpu(c->qsize);
 445     uint16_t qflags = le16_to_cpu(c->cq_flags);
 446     uint64_t prp1 = le64_to_cpu(c->prp1);
 447
 448     if (!cqid || (cqid && !nvme_check_cqid(n, cqid))) {
 449         return NVME_INVALID_CQID | NVME_DNR;
 450     }
 451     if (!qsize || qsize > NVME_CAP_MQES(n->bar.cap)) {
 452         return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
 453     }
 454     if (!prp1) {
 455         return NVME_INVALID_FIELD | NVME_DNR;
 456     }
 457     if (vector > n->num_queues) {
 458         return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
 459     }
 460     if (!(NVME_CQ_FLAGS_PC(qflags))) {
 461         return NVME_INVALID_FIELD | NVME_DNR;
 462     }
 463
 464     cq = g_malloc0(sizeof(*cq));
 465     nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1,
 466         NVME_CQ_FLAGS_IEN(qflags));
 467     return NVME_SUCCESS;
 468 }
 469
 470 static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd)
 471 {
 472     NvmeNamespace *ns;
 473     NvmeIdentify *c = (NvmeIdentify *)cmd;
 474     uint32_t cns  = le32_to_cpu(c->cns);
 475     uint32_t nsid = le32_to_cpu(c->nsid);
 476     uint64_t prp1 = le64_to_cpu(c->prp1);
 477     uint64_t prp2 = le64_to_cpu(c->prp2);
 478
 479     if (cns) {
 480         return nvme_dma_read_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl),
 481             prp1, prp2);
 482     }
 483     if (nsid == 0 || nsid > n->num_namespaces) {
 484         return NVME_INVALID_NSID | NVME_DNR;
 485     }
 486
 487     ns = &n->namespaces[nsid - 1];
 488     return nvme_dma_read_prp(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns),
 489         prp1, prp2);
 490 }
 491
 492 static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 493 {
 494     uint32_t dw10 = le32_to_cpu(cmd->cdw10);
 495     uint32_t result;
 496
 497     switch (dw10) {
 498     case NVME_VOLATILE_WRITE_CACHE:
 499         result = blk_enable_write_cache(n->conf.blk);
 500         break;
 501     case NVME_NUMBER_OF_QUEUES:
 502         result = cpu_to_le32((n->num_queues - 1) | ((n->num_queues - 1) << 16));
 503         break;
 504     default:
 505         return NVME_INVALID_FIELD | NVME_DNR;
 506     }
 507
 508     req->cqe.result = result;
 509     return NVME_SUCCESS;
 510 }
 511
 512 static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 513 {
 514     uint32_t dw10 = le32_to_cpu(cmd->cdw10);
 515     uint32_t dw11 = le32_to_cpu(cmd->cdw11);
 516
 517     switch (dw10) {
 518     case NVME_VOLATILE_WRITE_CACHE:
 519         blk_set_enable_write_cache(n->conf.blk, dw11 & 1);
 520         break;
 521     case NVME_NUMBER_OF_QUEUES:
 522         req->cqe.result =
 523             cpu_to_le32((n->num_queues - 1) | ((n->num_queues - 1) << 16));
 524         break;
 525     default:
 526         return NVME_INVALID_FIELD | NVME_DNR;
 527     }
 528     return NVME_SUCCESS;
 529 }
 530
 531 static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 532 {
 533     switch (cmd->opcode) {
 534     case NVME_ADM_CMD_DELETE_SQ:
 535         return nvme_del_sq(n, cmd);
 536     case NVME_ADM_CMD_CREATE_SQ:
 537         return nvme_create_sq(n, cmd);
 538     case NVME_ADM_CMD_DELETE_CQ:
 539         return nvme_del_cq(n, cmd);
 540     case NVME_ADM_CMD_CREATE_CQ:
 541         return nvme_create_cq(n, cmd);
 542     case NVME_ADM_CMD_IDENTIFY:
 543         return nvme_identify(n, cmd);
 544     case NVME_ADM_CMD_SET_FEATURES:
 545         return nvme_set_feature(n, cmd, req);
 546     case NVME_ADM_CMD_GET_FEATURES:
 547         return nvme_get_feature(n, cmd, req);
 548     default:
 549         return NVME_INVALID_OPCODE | NVME_DNR;
 550     }
 551 }
 552
 553 static void nvme_process_sq(void *opaque)
 554 {
 555     NvmeSQueue *sq = opaque;
 556     NvmeCtrl *n = sq->ctrl;
 557     NvmeCQueue *cq = n->cq[sq->cqid];
 558
 559     uint16_t status;
 560     hwaddr addr;
 561     NvmeCmd cmd;
 562     NvmeRequest *req;
 563
 564     while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) {
 565         addr = sq->dma_addr + sq->head * n->sqe_size;
 566         pci_dma_read(&n->parent_obj, addr, (void *)&cmd, sizeof(cmd));
 567         nvme_inc_sq_head(sq);
 568
 569         req = QTAILQ_FIRST(&sq->req_list);
 570         QTAILQ_REMOVE(&sq->req_list, req, entry);
 571         QTAILQ_INSERT_TAIL(&sq->out_req_list, req, entry);
 572         memset(&req->cqe, 0, sizeof(req->cqe));
 573         req->cqe.cid = cmd.cid;
 574
 575         status = sq->sqid ? nvme_io_cmd(n, &cmd, req) :
 576             nvme_admin_cmd(n, &cmd, req);
 577         if (status != NVME_NO_COMPLETE) {
 578             req->status = status;
 579             nvme_enqueue_req_completion(cq, req);
 580         }
 581     }
 582 }
 583
 584 static void nvme_clear_ctrl(NvmeCtrl *n)
 585 {
 586     int i;
 587
 588     for (i = 0; i < n->num_queues; i++) {
 589         if (n->sq[i] != NULL) {
 590             nvme_free_sq(n->sq[i], n);
 591         }
 592     }
 593     for (i = 0; i < n->num_queues; i++) {
 594         if (n->cq[i] != NULL) {
 595             nvme_free_cq(n->cq[i], n);
 596         }
 597     }
 598
 599     blk_flush(n->conf.blk);
 600     n->bar.cc = 0;
 601 }
 602
 603 static int nvme_start_ctrl(NvmeCtrl *n)
 604 {
 605     uint32_t page_bits = NVME_CC_MPS(n->bar.cc) + 12;
 606     uint32_t page_size = 1 << page_bits;
 607
 608     if (n->cq[0] || n->sq[0] || !n->bar.asq || !n->bar.acq ||
 609             n->bar.asq & (page_size - 1) || n->bar.acq & (page_size - 1) ||
 610             NVME_CC_MPS(n->bar.cc) < NVME_CAP_MPSMIN(n->bar.cap) ||
 611             NVME_CC_MPS(n->bar.cc) > NVME_CAP_MPSMAX(n->bar.cap) ||
 612             NVME_CC_IOCQES(n->bar.cc) < NVME_CTRL_CQES_MIN(n->id_ctrl.cqes) ||
 613             NVME_CC_IOCQES(n->bar.cc) > NVME_CTRL_CQES_MAX(n->id_ctrl.cqes) ||
 614             NVME_CC_IOSQES(n->bar.cc) < NVME_CTRL_SQES_MIN(n->id_ctrl.sqes) ||
 615             NVME_CC_IOSQES(n->bar.cc) > NVME_CTRL_SQES_MAX(n->id_ctrl.sqes) ||
 616             !NVME_AQA_ASQS(n->bar.aqa) || !NVME_AQA_ACQS(n->bar.aqa)) {
 617         return -1;
 618     }
 619
 620     n->page_bits = page_bits;
 621     n->page_size = page_size;
 622     n->max_prp_ents = n->page_size / sizeof(uint64_t);
 623     n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc);
 624     n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc);
 625     nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0,
 626         NVME_AQA_ACQS(n->bar.aqa) + 1, 1);
 627     nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0,
 628         NVME_AQA_ASQS(n->bar.aqa) + 1);
 629
 630     return 0;
 631 }
 632
 633 static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
 634     unsigned size)
 635 {
 636     switch (offset) {
 637     case 0xc:
 638         n->bar.intms |= data & 0xffffffff;
 639         n->bar.intmc = n->bar.intms;
 640         break;
 641     case 0x10:
 642         n->bar.intms &= ~(data & 0xffffffff);
 643         n->bar.intmc = n->bar.intms;
 644         break;
 645     case 0x14:
 646         /* Windows first sends data, then sends enable bit */
 647         if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) &&
 648             !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc))
 649         {
 650             n->bar.cc = data;
 651         }
 652
 653         if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) {
 654             n->bar.cc = data;
 655             if (nvme_start_ctrl(n)) {
 656                 n->bar.csts = NVME_CSTS_FAILED;
 657             } else {
 658                 n->bar.csts = NVME_CSTS_READY;
 659             }
 660         } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) {
 661             nvme_clear_ctrl(n);
 662             n->bar.csts &= ~NVME_CSTS_READY;
 663         }
 664         if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) {
 665                 nvme_clear_ctrl(n);
 666                 n->bar.cc = data;
 667                 n->bar.csts |= NVME_CSTS_SHST_COMPLETE;
 668         } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) {
 669                 n->bar.csts &= ~NVME_CSTS_SHST_COMPLETE;
 670                 n->bar.cc = data;
 671         }
 672         break;
 673     case 0x24:
 674         n->bar.aqa = data & 0xffffffff;
 675         break;
 676     case 0x28:
 677         n->bar.asq = data;
 678         break;
 679     case 0x2c:
 680         n->bar.asq |= data << 32;
 681         break;
 682     case 0x30:
 683         n->bar.acq = data;
 684         break;
 685     case 0x34:
 686         n->bar.acq |= data << 32;
 687         break;
 688     default:
 689         break;
 690     }
 691 }
 692
 693 static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
 694 {
 695     NvmeCtrl *n = (NvmeCtrl *)opaque;
 696     uint8_t *ptr = (uint8_t *)&n->bar;
 697     uint64_t val = 0;
 698
 699     if (addr < sizeof(n->bar)) {
 700         memcpy(&val, ptr + addr, size);
 701     }
 702     return val;
 703 }
 704
 705 static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
 706 {
 707     uint32_t qid;
 708
 709     if (addr & ((1 << 2) - 1)) {
 710         return;
 711     }
 712
 713     if (((addr - 0x1000) >> 2) & 1) {
 714         uint16_t new_head = val & 0xffff;
 715         int start_sqs;
 716         NvmeCQueue *cq;
 717
 718         qid = (addr - (0x1000 + (1 << 2))) >> 3;
 719         if (nvme_check_cqid(n, qid)) {
 720             return;
 721         }
 722
 723         cq = n->cq[qid];
 724         if (new_head >= cq->size) {
 725             return;
 726         }
 727
 728         start_sqs = nvme_cq_full(cq) ? 1 : 0;
 729         cq->head = new_head;
 730         if (start_sqs) {
 731             NvmeSQueue *sq;
 732             QTAILQ_FOREACH(sq, &cq->sq_list, entry) {
 733                 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 734             }
 735             timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 736         }
 737
 738         if (cq->tail != cq->head) {
 739             nvme_isr_notify(n, cq);
 740         }
 741     } else {
 742         uint16_t new_tail = val & 0xffff;
 743         NvmeSQueue *sq;
 744
 745         qid = (addr - 0x1000) >> 3;
 746         if (nvme_check_sqid(n, qid)) {
 747             return;
 748         }
 749
 750         sq = n->sq[qid];
 751         if (new_tail >= sq->size) {
 752             return;
 753         }
 754
 755         sq->tail = new_tail;
 756         timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 757     }
 758 }
 759
 760 static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data,
 761     unsigned size)
 762 {
 763     NvmeCtrl *n = (NvmeCtrl *)opaque;
 764     if (addr < sizeof(n->bar)) {
 765         nvme_write_bar(n, addr, data, size);
 766     } else if (addr >= 0x1000) {
 767         nvme_process_db(n, addr, data);
 768     }
 769 }
 770
 771 static const MemoryRegionOps nvme_mmio_ops = {
 772     .read = nvme_mmio_read,
 773     .write = nvme_mmio_write,
 774     .endianness = DEVICE_LITTLE_ENDIAN,
 775     .impl = {
 776         .min_access_size = 2,
 777         .max_access_size = 8,
 778     },
 779 };
 780
 781 static int nvme_init(PCIDevice *pci_dev)
 782 {
 783     NvmeCtrl *n = NVME(pci_dev);
 784     NvmeIdCtrl *id = &n->id_ctrl;
 785
 786     int i;
 787     int64_t bs_size;
 788     uint8_t *pci_conf;
 789
 790     if (!n->conf.blk) {
 791         return -1;
 792     }
 793
 794     bs_size = blk_getlength(n->conf.blk);
 795     if (bs_size < 0) {
 796         return -1;
 797     }
 798
 799     blkconf_serial(&n->conf, &n->serial);
 800     if (!n->serial) {
 801         return -1;
 802     }
 803     blkconf_blocksizes(&n->conf);
 804
 805     pci_conf = pci_dev->config;
 806     pci_conf[PCI_INTERRUPT_PIN] = 1;
 807     pci_config_set_prog_interface(pci_dev->config, 0x2);
 808     pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS);
 809     pcie_endpoint_cap_init(&n->parent_obj, 0x80);
 810
 811     n->num_namespaces = 1;
 812     n->num_queues = 64;
 813     n->reg_size = pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4);
 814     n->ns_size = bs_size / (uint64_t)n->num_namespaces;
 815
 816     n->namespaces = g_new0(NvmeNamespace, n->num_namespaces);
 817     n->sq = g_new0(NvmeSQueue *, n->num_queues);
 818     n->cq = g_new0(NvmeCQueue *, n->num_queues);
 819
 820     memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n,
 821                           "nvme", n->reg_size);
 822     pci_register_bar(&n->parent_obj, 0,
 823         PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64,
 824         &n->iomem);
 825     msix_init_exclusive_bar(&n->parent_obj, n->num_queues, 4);
 826
 827     id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
 828     id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
 829     strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
 830     strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' ');
 831     strpadcpy((char *)id->sn, sizeof(id->sn), n->serial, ' ');
 832     id->rab = 6;
 833     id->ieee[0] = 0x00;
 834     id->ieee[1] = 0x02;
 835     id->ieee[2] = 0xb3;
 836     id->oacs = cpu_to_le16(0);
 837     id->frmw = 7 << 1;
 838     id->lpa = 1 << 0;
 839     id->sqes = (0x6 << 4) | 0x6;
 840     id->cqes = (0x4 << 4) | 0x4;
 841     id->nn = cpu_to_le32(n->num_namespaces);
 842     id->psd[0].mp = cpu_to_le16(0x9c4);
 843     id->psd[0].enlat = cpu_to_le32(0x10);
 844     id->psd[0].exlat = cpu_to_le32(0x4);
 845     if (blk_enable_write_cache(n->conf.blk)) {
 846         id->vwc = 1;
 847     }
 848
 849     n->bar.cap = 0;
 850     NVME_CAP_SET_MQES(n->bar.cap, 0x7ff);
 851     NVME_CAP_SET_CQR(n->bar.cap, 1);
 852     NVME_CAP_SET_AMS(n->bar.cap, 1);
 853     NVME_CAP_SET_TO(n->bar.cap, 0xf);
 854     NVME_CAP_SET_CSS(n->bar.cap, 1);
 855     NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
 856
 857     n->bar.vs = 0x00010100;
 858     n->bar.intmc = n->bar.intms = 0;
 859
 860     for (i = 0; i < n->num_namespaces; i++) {
 861         NvmeNamespace *ns = &n->namespaces[i];
 862         NvmeIdNs *id_ns = &ns->id_ns;
 863         id_ns->nsfeat = 0;
 864         id_ns->nlbaf = 0;
 865         id_ns->flbas = 0;
 866         id_ns->mc = 0;
 867         id_ns->dpc = 0;
 868         id_ns->dps = 0;
 869         id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
 870         id_ns->ncap  = id_ns->nuse = id_ns->nsze =
 871             cpu_to_le64(n->ns_size >>
 872                 id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas)].ds);
 873     }
 874     return 0;
 875 }
 876
 877 static void nvme_exit(PCIDevice *pci_dev)
 878 {
 879     NvmeCtrl *n = NVME(pci_dev);
 880
 881     nvme_clear_ctrl(n);
 882     g_free(n->namespaces);
 883     g_free(n->cq);
 884     g_free(n->sq);
 885     msix_uninit_exclusive_bar(pci_dev);
 886 }
 887
 888 static Property nvme_props[] = {
 889     DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
 890     DEFINE_PROP_STRING("serial", NvmeCtrl, serial),
 891     DEFINE_PROP_END_OF_LIST(),
 892 };
 893
 894 static const VMStateDescription nvme_vmstate = {
 895     .name = "nvme",
 896     .unmigratable = 1,
 897 };
 898
 899 static void nvme_class_init(ObjectClass *oc, void *data)
 900 {
 901     DeviceClass *dc = DEVICE_CLASS(oc);
 902     PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
 903
 904     pc->init = nvme_init;
 905     pc->exit = nvme_exit;
 906     pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
 907     pc->vendor_id = PCI_VENDOR_ID_INTEL;
 908     pc->device_id = 0x5845;
 909     pc->revision = 1;
 910     pc->is_express = 1;
 911
 912     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 913     dc->desc = "Non-Volatile Memory Express";
 914     dc->props = nvme_props;
 915     dc->vmsd = &nvme_vmstate;
 916 }
 917
 918 static void nvme_get_bootindex(Object *obj, Visitor *v, void *opaque,
 919                                   const char *name, Error **errp)
 920 {
 921     NvmeCtrl *s = NVME(obj);
 922
 923     visit_type_int32(v, &s->conf.bootindex, name, errp);
 924 }
 925
 926 static void nvme_set_bootindex(Object *obj, Visitor *v, void *opaque,
 927                                   const char *name, Error **errp)
 928 {
 929     NvmeCtrl *s = NVME(obj);
 930     int32_t boot_index;
 931     Error *local_err = NULL;
 932
 933     visit_type_int32(v, &boot_index, name, &local_err);
 934     if (local_err) {
 935         goto out;
 936     }
 937     /* check whether bootindex is present in fw_boot_order list  */
 938     check_boot_index(boot_index, &local_err);
 939     if (local_err) {
 940         goto out;
 941     }
 942     /* change bootindex to a new one */
 943     s->conf.bootindex = boot_index;
 944
 945 out:
 946     if (local_err) {
 947         error_propagate(errp, local_err);
 948     }
 949 }
 950
 951 static void nvme_instance_init(Object *obj)
 952 {
 953     object_property_add(obj, "bootindex", "int32",
 954                         nvme_get_bootindex,
 955                         nvme_set_bootindex, NULL, NULL, NULL);
 956     object_property_set_int(obj, -1, "bootindex", NULL);
 957 }
 958
 959 static const TypeInfo nvme_info = {
 960     .name          = "nvme",
 961     .parent        = TYPE_PCI_DEVICE,
 962     .instance_size = sizeof(NvmeCtrl),
 963     .class_init    = nvme_class_init,
 964     .instance_init = nvme_instance_init,
 965 };
 966
 967 static void nvme_register_types(void)
 968 {
 969     type_register_static(&nvme_info);
 970 }
 971
 972 type_init(nvme_register_types)