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1 /*
2 * QEMU NVM Express Controller
3 *
4 * Copyright (c) 2012, Intel Corporation
5 *
6 * Written by Keith Busch <keith.busch@intel.com>
7 *
8 * This code is licensed under the GNU GPL v2 or later.
9 */
10
11 /**
12 * Reference Specs: http://www.nvmexpress.org, 1.2, 1.1, 1.0e
13 *
14 * https://nvmexpress.org/developers/nvme-specification/
15 */
16
17 /**
18 * Usage: add options:
19 * -drive file=<file>,if=none,id=<drive_id>
20 * -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>, \
21 * cmb_size_mb=<cmb_size_mb[optional]>, \
22 * [pmrdev=<mem_backend_file_id>,] \
23 * max_ioqpairs=<N[optional]>, \
24 * aerl=<N[optional]>, aer_max_queued=<N[optional]>, \
25 * mdts=<N[optional]>
26 *
27 * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
28 * offset 0 in BAR2 and supports only WDS, RDS and SQS for now.
29 *
30 * cmb_size_mb= and pmrdev= options are mutually exclusive due to limitation
31 * in available BAR's. cmb_size_mb= will take precedence over pmrdev= when
32 * both provided.
33 * Enabling pmr emulation can be achieved by pointing to memory-backend-file.
34 * For example:
35 * -object memory-backend-file,id=<mem_id>,share=on,mem-path=<file_path>, \
36 * size=<size> .... -device nvme,...,pmrdev=<mem_id>
37 *
38 *
39 * nvme device parameters
40 * ~~~~~~~~~~~~~~~~~~~~~~
41 * - `aerl`
42 * The Asynchronous Event Request Limit (AERL). Indicates the maximum number
43 * of concurrently outstanding Asynchronous Event Request commands suppoert
44 * by the controller. This is a 0's based value.
45 *
46 * - `aer_max_queued`
47 * This is the maximum number of events that the device will enqueue for
48 * completion when there are no oustanding AERs. When the maximum number of
49 * enqueued events are reached, subsequent events will be dropped.
50 *
51 */
52
53 #include "qemu/osdep.h"
54 #include "qemu/units.h"
55 #include "qemu/error-report.h"
56 #include "hw/block/block.h"
57 #include "hw/pci/msix.h"
58 #include "hw/pci/pci.h"
59 #include "hw/qdev-properties.h"
60 #include "migration/vmstate.h"
61 #include "sysemu/sysemu.h"
62 #include "qapi/error.h"
63 #include "qapi/visitor.h"
64 #include "sysemu/hostmem.h"
65 #include "sysemu/block-backend.h"
66 #include "exec/memory.h"
67 #include "qemu/log.h"
68 #include "qemu/module.h"
69 #include "qemu/cutils.h"
70 #include "trace.h"
71 #include "nvme.h"
72
73 #define NVME_MAX_IOQPAIRS 0xffff
74 #define NVME_DB_SIZE 4
75 #define NVME_SPEC_VER 0x00010300
76 #define NVME_CMB_BIR 2
77 #define NVME_PMR_BIR 2
78 #define NVME_TEMPERATURE 0x143
79 #define NVME_TEMPERATURE_WARNING 0x157
80 #define NVME_TEMPERATURE_CRITICAL 0x175
81 #define NVME_NUM_FW_SLOTS 1
82
83 #define NVME_GUEST_ERR(trace, fmt, ...) \
84 do { \
85 (trace_##trace)(__VA_ARGS__); \
86 qemu_log_mask(LOG_GUEST_ERROR, #trace \
87 " in %s: " fmt "\n", __func__, ## __VA_ARGS__); \
88 } while (0)
89
90 static const bool nvme_feature_support[NVME_FID_MAX] = {
91 [NVME_ARBITRATION] = true,
92 [NVME_POWER_MANAGEMENT] = true,
93 [NVME_TEMPERATURE_THRESHOLD] = true,
94 [NVME_ERROR_RECOVERY] = true,
95 [NVME_VOLATILE_WRITE_CACHE] = true,
96 [NVME_NUMBER_OF_QUEUES] = true,
97 [NVME_INTERRUPT_COALESCING] = true,
98 [NVME_INTERRUPT_VECTOR_CONF] = true,
99 [NVME_WRITE_ATOMICITY] = true,
100 [NVME_ASYNCHRONOUS_EVENT_CONF] = true,
101 [NVME_TIMESTAMP] = true,
102 };
103
104 static const uint32_t nvme_feature_cap[NVME_FID_MAX] = {
105 [NVME_TEMPERATURE_THRESHOLD] = NVME_FEAT_CAP_CHANGE,
106 [NVME_VOLATILE_WRITE_CACHE] = NVME_FEAT_CAP_CHANGE,
107 [NVME_NUMBER_OF_QUEUES] = NVME_FEAT_CAP_CHANGE,
108 [NVME_ASYNCHRONOUS_EVENT_CONF] = NVME_FEAT_CAP_CHANGE,
109 [NVME_TIMESTAMP] = NVME_FEAT_CAP_CHANGE,
110 };
111
112 static void nvme_process_sq(void *opaque);
113
114 static uint16_t nvme_cid(NvmeRequest *req)
115 {
116 if (!req) {
117 return 0xffff;
118 }
119
120 return le16_to_cpu(req->cqe.cid);
121 }
122
123 static uint16_t nvme_sqid(NvmeRequest *req)
124 {
125 return le16_to_cpu(req->sq->sqid);
126 }
127
128 static bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr)
129 {
130 hwaddr low = n->ctrl_mem.addr;
131 hwaddr hi = n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size);
132
133 return addr >= low && addr < hi;
134 }
135
136 static inline void *nvme_addr_to_cmb(NvmeCtrl *n, hwaddr addr)
137 {
138 assert(nvme_addr_is_cmb(n, addr));
139
140 return &n->cmbuf[addr - n->ctrl_mem.addr];
141 }
142
143 static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
144 {
145 hwaddr hi = addr + size - 1;
146 if (hi < addr) {
147 return 1;
148 }
149
150 if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr) && nvme_addr_is_cmb(n, hi)) {
151 memcpy(buf, nvme_addr_to_cmb(n, addr), size);
152 return 0;
153 }
154
155 return pci_dma_read(&n->parent_obj, addr, buf, size);
156 }
157
158 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
159 {
160 return sqid < n->params.max_ioqpairs + 1 && n->sq[sqid] != NULL ? 0 : -1;
161 }
162
163 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
164 {
165 return cqid < n->params.max_ioqpairs + 1 && n->cq[cqid] != NULL ? 0 : -1;
166 }
167
168 static void nvme_inc_cq_tail(NvmeCQueue *cq)
169 {
170 cq->tail++;
171 if (cq->tail >= cq->size) {
172 cq->tail = 0;
173 cq->phase = !cq->phase;
174 }
175 }
176
177 static void nvme_inc_sq_head(NvmeSQueue *sq)
178 {
179 sq->head = (sq->head + 1) % sq->size;
180 }
181
182 static uint8_t nvme_cq_full(NvmeCQueue *cq)
183 {
184 return (cq->tail + 1) % cq->size == cq->head;
185 }
186
187 static uint8_t nvme_sq_empty(NvmeSQueue *sq)
188 {
189 return sq->head == sq->tail;
190 }
191
192 static void nvme_irq_check(NvmeCtrl *n)
193 {
194 if (msix_enabled(&(n->parent_obj))) {
195 return;
196 }
197 if (~n->bar.intms & n->irq_status) {
198 pci_irq_assert(&n->parent_obj);
199 } else {
200 pci_irq_deassert(&n->parent_obj);
201 }
202 }
203
204 static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq)
205 {
206 if (cq->irq_enabled) {
207 if (msix_enabled(&(n->parent_obj))) {
208 trace_pci_nvme_irq_msix(cq->vector);
209 msix_notify(&(n->parent_obj), cq->vector);
210 } else {
211 trace_pci_nvme_irq_pin();
212 assert(cq->vector < 32);
213 n->irq_status |= 1 << cq->vector;
214 nvme_irq_check(n);
215 }
216 } else {
217 trace_pci_nvme_irq_masked();
218 }
219 }
220
221 static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *cq)
222 {
223 if (cq->irq_enabled) {
224 if (msix_enabled(&(n->parent_obj))) {
225 return;
226 } else {
227 assert(cq->vector < 32);
228 n->irq_status &= ~(1 << cq->vector);
229 nvme_irq_check(n);
230 }
231 }
232 }
233
234 static void nvme_req_clear(NvmeRequest *req)
235 {
236 req->ns = NULL;
237 memset(&req->cqe, 0x0, sizeof(req->cqe));
238 req->status = NVME_SUCCESS;
239 }
240
241 static void nvme_req_exit(NvmeRequest *req)
242 {
243 if (req->qsg.sg) {
244 qemu_sglist_destroy(&req->qsg);
245 }
246
247 if (req->iov.iov) {
248 qemu_iovec_destroy(&req->iov);
249 }
250 }
251
252 static uint16_t nvme_map_addr_cmb(NvmeCtrl *n, QEMUIOVector *iov, hwaddr addr,
253 size_t len)
254 {
255 if (!len) {
256 return NVME_SUCCESS;
257 }
258
259 trace_pci_nvme_map_addr_cmb(addr, len);
260
261 if (!nvme_addr_is_cmb(n, addr) || !nvme_addr_is_cmb(n, addr + len - 1)) {
262 return NVME_DATA_TRAS_ERROR;
263 }
264
265 qemu_iovec_add(iov, nvme_addr_to_cmb(n, addr), len);
266
267 return NVME_SUCCESS;
268 }
269
270 static uint16_t nvme_map_addr(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov,
271 hwaddr addr, size_t len)
272 {
273 if (!len) {
274 return NVME_SUCCESS;
275 }
276
277 trace_pci_nvme_map_addr(addr, len);
278
279 if (nvme_addr_is_cmb(n, addr)) {
280 if (qsg && qsg->sg) {
281 return NVME_INVALID_USE_OF_CMB | NVME_DNR;
282 }
283
284 assert(iov);
285
286 if (!iov->iov) {
287 qemu_iovec_init(iov, 1);
288 }
289
290 return nvme_map_addr_cmb(n, iov, addr, len);
291 }
292
293 if (iov && iov->iov) {
294 return NVME_INVALID_USE_OF_CMB | NVME_DNR;
295 }
296
297 assert(qsg);
298
299 if (!qsg->sg) {
300 pci_dma_sglist_init(qsg, &n->parent_obj, 1);
301 }
302
303 qemu_sglist_add(qsg, addr, len);
304
305 return NVME_SUCCESS;
306 }
307
308 static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1, uint64_t prp2,
309 uint32_t len, NvmeRequest *req)
310 {
311 hwaddr trans_len = n->page_size - (prp1 % n->page_size);
312 trans_len = MIN(len, trans_len);
313 int num_prps = (len >> n->page_bits) + 1;
314 uint16_t status;
315 bool prp_list_in_cmb = false;
316 int ret;
317
318 QEMUSGList *qsg = &req->qsg;
319 QEMUIOVector *iov = &req->iov;
320
321 trace_pci_nvme_map_prp(trans_len, len, prp1, prp2, num_prps);
322
323 if (unlikely(!prp1)) {
324 trace_pci_nvme_err_invalid_prp();
325 return NVME_INVALID_FIELD | NVME_DNR;
326 }
327
328 if (nvme_addr_is_cmb(n, prp1)) {
329 qemu_iovec_init(iov, num_prps);
330 } else {
331 pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
332 }
333
334 status = nvme_map_addr(n, qsg, iov, prp1, trans_len);
335 if (status) {
336 return status;
337 }
338
339 len -= trans_len;
340 if (len) {
341 if (unlikely(!prp2)) {
342 trace_pci_nvme_err_invalid_prp2_missing();
343 return NVME_INVALID_FIELD | NVME_DNR;
344 }
345
346 if (len > n->page_size) {
347 uint64_t prp_list[n->max_prp_ents];
348 uint32_t nents, prp_trans;
349 int i = 0;
350
351 if (nvme_addr_is_cmb(n, prp2)) {
352 prp_list_in_cmb = true;
353 }
354
355 nents = (len + n->page_size - 1) >> n->page_bits;
356 prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
357 ret = nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
358 if (ret) {
359 trace_pci_nvme_err_addr_read(prp2);
360 return NVME_DATA_TRAS_ERROR;
361 }
362 while (len != 0) {
363 uint64_t prp_ent = le64_to_cpu(prp_list[i]);
364
365 if (i == n->max_prp_ents - 1 && len > n->page_size) {
366 if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) {
367 trace_pci_nvme_err_invalid_prplist_ent(prp_ent);
368 return NVME_INVALID_FIELD | NVME_DNR;
369 }
370
371 if (prp_list_in_cmb != nvme_addr_is_cmb(n, prp_ent)) {
372 return NVME_INVALID_USE_OF_CMB | NVME_DNR;
373 }
374
375 i = 0;
376 nents = (len + n->page_size - 1) >> n->page_bits;
377 prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
378 ret = nvme_addr_read(n, prp_ent, (void *)prp_list,
379 prp_trans);
380 if (ret) {
381 trace_pci_nvme_err_addr_read(prp_ent);
382 return NVME_DATA_TRAS_ERROR;
383 }
384 prp_ent = le64_to_cpu(prp_list[i]);
385 }
386
387 if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) {
388 trace_pci_nvme_err_invalid_prplist_ent(prp_ent);
389 return NVME_INVALID_FIELD | NVME_DNR;
390 }
391
392 trans_len = MIN(len, n->page_size);
393 status = nvme_map_addr(n, qsg, iov, prp_ent, trans_len);
394 if (status) {
395 return status;
396 }
397
398 len -= trans_len;
399 i++;
400 }
401 } else {
402 if (unlikely(prp2 & (n->page_size - 1))) {
403 trace_pci_nvme_err_invalid_prp2_align(prp2);
404 return NVME_INVALID_FIELD | NVME_DNR;
405 }
406 status = nvme_map_addr(n, qsg, iov, prp2, len);
407 if (status) {
408 return status;
409 }
410 }
411 }
412
413 return NVME_SUCCESS;
414 }
415
416 /*
417 * Map 'nsgld' data descriptors from 'segment'. The function will subtract the
418 * number of bytes mapped in len.
419 */
420 static uint16_t nvme_map_sgl_data(NvmeCtrl *n, QEMUSGList *qsg,
421 QEMUIOVector *iov,
422 NvmeSglDescriptor *segment, uint64_t nsgld,
423 size_t *len, NvmeRequest *req)
424 {
425 dma_addr_t addr, trans_len;
426 uint32_t dlen;
427 uint16_t status;
428
429 for (int i = 0; i < nsgld; i++) {
430 uint8_t type = NVME_SGL_TYPE(segment[i].type);
431
432 switch (type) {
433 case NVME_SGL_DESCR_TYPE_BIT_BUCKET:
434 if (req->cmd.opcode == NVME_CMD_WRITE) {
435 continue;
436 }
437 case NVME_SGL_DESCR_TYPE_DATA_BLOCK:
438 break;
439 case NVME_SGL_DESCR_TYPE_SEGMENT:
440 case NVME_SGL_DESCR_TYPE_LAST_SEGMENT:
441 return NVME_INVALID_NUM_SGL_DESCRS | NVME_DNR;
442 default:
443 return NVME_SGL_DESCR_TYPE_INVALID | NVME_DNR;
444 }
445
446 dlen = le32_to_cpu(segment[i].len);
447
448 if (!dlen) {
449 continue;
450 }
451
452 if (*len == 0) {
453 /*
454 * All data has been mapped, but the SGL contains additional
455 * segments and/or descriptors. The controller might accept
456 * ignoring the rest of the SGL.
457 */
458 uint16_t sgls = le16_to_cpu(n->id_ctrl.sgls);
459 if (sgls & NVME_CTRL_SGLS_EXCESS_LENGTH) {
460 break;
461 }
462
463 trace_pci_nvme_err_invalid_sgl_excess_length(nvme_cid(req));
464 return NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
465 }
466
467 trans_len = MIN(*len, dlen);
468
469 if (type == NVME_SGL_DESCR_TYPE_BIT_BUCKET) {
470 goto next;
471 }
472
473 addr = le64_to_cpu(segment[i].addr);
474
475 if (UINT64_MAX - addr < dlen) {
476 return NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
477 }
478
479 status = nvme_map_addr(n, qsg, iov, addr, trans_len);
480 if (status) {
481 return status;
482 }
483
484 next:
485 *len -= trans_len;
486 }
487
488 return NVME_SUCCESS;
489 }
490
491 static uint16_t nvme_map_sgl(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov,
492 NvmeSglDescriptor sgl, size_t len,
493 NvmeRequest *req)
494 {
495 /*
496 * Read the segment in chunks of 256 descriptors (one 4k page) to avoid
497 * dynamically allocating a potentially huge SGL. The spec allows the SGL
498 * to be larger (as in number of bytes required to describe the SGL
499 * descriptors and segment chain) than the command transfer size, so it is
500 * not bounded by MDTS.
501 */
502 const int SEG_CHUNK_SIZE = 256;
503
504 NvmeSglDescriptor segment[SEG_CHUNK_SIZE], *sgld, *last_sgld;
505 uint64_t nsgld;
506 uint32_t seg_len;
507 uint16_t status;
508 bool sgl_in_cmb = false;
509 hwaddr addr;
510 int ret;
511
512 sgld = &sgl;
513 addr = le64_to_cpu(sgl.addr);
514
515 trace_pci_nvme_map_sgl(nvme_cid(req), NVME_SGL_TYPE(sgl.type), len);
516
517 /*
518 * If the entire transfer can be described with a single data block it can
519 * be mapped directly.
520 */
521 if (NVME_SGL_TYPE(sgl.type) == NVME_SGL_DESCR_TYPE_DATA_BLOCK) {
522 status = nvme_map_sgl_data(n, qsg, iov, sgld, 1, &len, req);
523 if (status) {
524 goto unmap;
525 }
526
527 goto out;
528 }
529
530 /*
531 * If the segment is located in the CMB, the submission queue of the
532 * request must also reside there.
533 */
534 if (nvme_addr_is_cmb(n, addr)) {
535 if (!nvme_addr_is_cmb(n, req->sq->dma_addr)) {
536 return NVME_INVALID_USE_OF_CMB | NVME_DNR;
537 }
538
539 sgl_in_cmb = true;
540 }
541
542 for (;;) {
543 switch (NVME_SGL_TYPE(sgld->type)) {
544 case NVME_SGL_DESCR_TYPE_SEGMENT:
545 case NVME_SGL_DESCR_TYPE_LAST_SEGMENT:
546 break;
547 default:
548 return NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
549 }
550
551 seg_len = le32_to_cpu(sgld->len);
552
553 /* check the length of the (Last) Segment descriptor */
554 if ((!seg_len || seg_len & 0xf) &&
555 (NVME_SGL_TYPE(sgld->type) != NVME_SGL_DESCR_TYPE_BIT_BUCKET)) {
556 return NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
557 }
558
559 if (UINT64_MAX - addr < seg_len) {
560 return NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
561 }
562
563 nsgld = seg_len / sizeof(NvmeSglDescriptor);
564
565 while (nsgld > SEG_CHUNK_SIZE) {
566 if (nvme_addr_read(n, addr, segment, sizeof(segment))) {
567 trace_pci_nvme_err_addr_read(addr);
568 status = NVME_DATA_TRAS_ERROR;
569 goto unmap;
570 }
571
572 status = nvme_map_sgl_data(n, qsg, iov, segment, SEG_CHUNK_SIZE,
573 &len, req);
574 if (status) {
575 goto unmap;
576 }
577
578 nsgld -= SEG_CHUNK_SIZE;
579 addr += SEG_CHUNK_SIZE * sizeof(NvmeSglDescriptor);
580 }
581
582 ret = nvme_addr_read(n, addr, segment, nsgld *
583 sizeof(NvmeSglDescriptor));
584 if (ret) {
585 trace_pci_nvme_err_addr_read(addr);
586 status = NVME_DATA_TRAS_ERROR;
587 goto unmap;
588 }
589
590 last_sgld = &segment[nsgld - 1];
591
592 /*
593 * If the segment ends with a Data Block or Bit Bucket Descriptor Type,
594 * then we are done.
595 */
596 switch (NVME_SGL_TYPE(last_sgld->type)) {
597 case NVME_SGL_DESCR_TYPE_DATA_BLOCK:
598 case NVME_SGL_DESCR_TYPE_BIT_BUCKET:
599 status = nvme_map_sgl_data(n, qsg, iov, segment, nsgld, &len, req);
600 if (status) {
601 goto unmap;
602 }
603
604 goto out;
605
606 default:
607 break;
608 }
609
610 /*
611 * If the last descriptor was not a Data Block or Bit Bucket, then the
612 * current segment must not be a Last Segment.
613 */
614 if (NVME_SGL_TYPE(sgld->type) == NVME_SGL_DESCR_TYPE_LAST_SEGMENT) {
615 status = NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
616 goto unmap;
617 }
618
619 sgld = last_sgld;
620 addr = le64_to_cpu(sgld->addr);
621
622 /*
623 * Do not map the last descriptor; it will be a Segment or Last Segment
624 * descriptor and is handled by the next iteration.
625 */
626 status = nvme_map_sgl_data(n, qsg, iov, segment, nsgld - 1, &len, req);
627 if (status) {
628 goto unmap;
629 }
630
631 /*
632 * If the next segment is in the CMB, make sure that the sgl was
633 * already located there.
634 */
635 if (sgl_in_cmb != nvme_addr_is_cmb(n, addr)) {
636 status = NVME_INVALID_USE_OF_CMB | NVME_DNR;
637 goto unmap;
638 }
639 }
640
641 out:
642 /* if there is any residual left in len, the SGL was too short */
643 if (len) {
644 status = NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
645 goto unmap;
646 }
647
648 return NVME_SUCCESS;
649
650 unmap:
651 if (iov->iov) {
652 qemu_iovec_destroy(iov);
653 }
654
655 if (qsg->sg) {
656 qemu_sglist_destroy(qsg);
657 }
658
659 return status;
660 }
661
662 static uint16_t nvme_map_dptr(NvmeCtrl *n, size_t len, NvmeRequest *req)
663 {
664 uint64_t prp1, prp2;
665
666 switch (NVME_CMD_FLAGS_PSDT(req->cmd.flags)) {
667 case NVME_PSDT_PRP:
668 prp1 = le64_to_cpu(req->cmd.dptr.prp1);
669 prp2 = le64_to_cpu(req->cmd.dptr.prp2);
670
671 return nvme_map_prp(n, prp1, prp2, len, req);
672 case NVME_PSDT_SGL_MPTR_CONTIGUOUS:
673 case NVME_PSDT_SGL_MPTR_SGL:
674 /* SGLs shall not be used for Admin commands in NVMe over PCIe */
675 if (!req->sq->sqid) {
676 return NVME_INVALID_FIELD | NVME_DNR;
677 }
678
679 return nvme_map_sgl(n, &req->qsg, &req->iov, req->cmd.dptr.sgl, len,
680 req);
681 default:
682 return NVME_INVALID_FIELD;
683 }
684 }
685
686 static uint16_t nvme_dma(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
687 DMADirection dir, NvmeRequest *req)
688 {
689 uint16_t status = NVME_SUCCESS;
690
691 status = nvme_map_dptr(n, len, req);
692 if (status) {
693 return status;
694 }
695
696 /* assert that only one of qsg and iov carries data */
697 assert((req->qsg.nsg > 0) != (req->iov.niov > 0));
698
699 if (req->qsg.nsg > 0) {
700 uint64_t residual;
701
702 if (dir == DMA_DIRECTION_TO_DEVICE) {
703 residual = dma_buf_write(ptr, len, &req->qsg);
704 } else {
705 residual = dma_buf_read(ptr, len, &req->qsg);
706 }
707
708 if (unlikely(residual)) {
709 trace_pci_nvme_err_invalid_dma();
710 status = NVME_INVALID_FIELD | NVME_DNR;
711 }
712 } else {
713 size_t bytes;
714
715 if (dir == DMA_DIRECTION_TO_DEVICE) {
716 bytes = qemu_iovec_to_buf(&req->iov, 0, ptr, len);
717 } else {
718 bytes = qemu_iovec_from_buf(&req->iov, 0, ptr, len);
719 }
720
721 if (unlikely(bytes != len)) {
722 trace_pci_nvme_err_invalid_dma();
723 status = NVME_INVALID_FIELD | NVME_DNR;
724 }
725 }
726
727 return status;
728 }
729
730 static void nvme_post_cqes(void *opaque)
731 {
732 NvmeCQueue *cq = opaque;
733 NvmeCtrl *n = cq->ctrl;
734 NvmeRequest *req, *next;
735 int ret;
736
737 QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
738 NvmeSQueue *sq;
739 hwaddr addr;
740
741 if (nvme_cq_full(cq)) {
742 break;
743 }
744
745 sq = req->sq;
746 req->cqe.status = cpu_to_le16((req->status << 1) | cq->phase);
747 req->cqe.sq_id = cpu_to_le16(sq->sqid);
748 req->cqe.sq_head = cpu_to_le16(sq->head);
749 addr = cq->dma_addr + cq->tail * n->cqe_size;
750 ret = pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
751 sizeof(req->cqe));
752 if (ret) {
753 trace_pci_nvme_err_addr_write(addr);
754 trace_pci_nvme_err_cfs();
755 n->bar.csts = NVME_CSTS_FAILED;
756 break;
757 }
758 QTAILQ_REMOVE(&cq->req_list, req, entry);
759 nvme_inc_cq_tail(cq);
760 nvme_req_exit(req);
761 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
762 }
763 if (cq->tail != cq->head) {
764 nvme_irq_assert(n, cq);
765 }
766 }
767
768 static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
769 {
770 assert(cq->cqid == req->sq->cqid);
771 trace_pci_nvme_enqueue_req_completion(nvme_cid(req), cq->cqid,
772 req->status);
773 QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
774 QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
775 timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
776 }
777
778 static void nvme_process_aers(void *opaque)
779 {
780 NvmeCtrl *n = opaque;
781 NvmeAsyncEvent *event, *next;
782
783 trace_pci_nvme_process_aers(n->aer_queued);
784
785 QTAILQ_FOREACH_SAFE(event, &n->aer_queue, entry, next) {
786 NvmeRequest *req;
787 NvmeAerResult *result;
788
789 /* can't post cqe if there is nothing to complete */
790 if (!n->outstanding_aers) {
791 trace_pci_nvme_no_outstanding_aers();
792 break;
793 }
794
795 /* ignore if masked (cqe posted, but event not cleared) */
796 if (n->aer_mask & (1 << event->result.event_type)) {
797 trace_pci_nvme_aer_masked(event->result.event_type, n->aer_mask);
798 continue;
799 }
800
801 QTAILQ_REMOVE(&n->aer_queue, event, entry);
802 n->aer_queued--;
803
804 n->aer_mask |= 1 << event->result.event_type;
805 n->outstanding_aers--;
806
807 req = n->aer_reqs[n->outstanding_aers];
808
809 result = (NvmeAerResult *) &req->cqe.result;
810 result->event_type = event->result.event_type;
811 result->event_info = event->result.event_info;
812 result->log_page = event->result.log_page;
813 g_free(event);
814
815 trace_pci_nvme_aer_post_cqe(result->event_type, result->event_info,
816 result->log_page);
817
818 nvme_enqueue_req_completion(&n->admin_cq, req);
819 }
820 }
821
822 static void nvme_enqueue_event(NvmeCtrl *n, uint8_t event_type,
823 uint8_t event_info, uint8_t log_page)
824 {
825 NvmeAsyncEvent *event;
826
827 trace_pci_nvme_enqueue_event(event_type, event_info, log_page);
828
829 if (n->aer_queued == n->params.aer_max_queued) {
830 trace_pci_nvme_enqueue_event_noqueue(n->aer_queued);
831 return;
832 }
833
834 event = g_new(NvmeAsyncEvent, 1);
835 event->result = (NvmeAerResult) {
836 .event_type = event_type,
837 .event_info = event_info,
838 .log_page = log_page,
839 };
840
841 QTAILQ_INSERT_TAIL(&n->aer_queue, event, entry);
842 n->aer_queued++;
843
844 nvme_process_aers(n);
845 }
846
847 static void nvme_clear_events(NvmeCtrl *n, uint8_t event_type)
848 {
849 n->aer_mask &= ~(1 << event_type);
850 if (!QTAILQ_EMPTY(&n->aer_queue)) {
851 nvme_process_aers(n);
852 }
853 }
854
855 static inline uint16_t nvme_check_mdts(NvmeCtrl *n, size_t len)
856 {
857 uint8_t mdts = n->params.mdts;
858
859 if (mdts && len > n->page_size << mdts) {
860 return NVME_INVALID_FIELD | NVME_DNR;
861 }
862
863 return NVME_SUCCESS;
864 }
865
866 static inline uint16_t nvme_check_bounds(NvmeCtrl *n, NvmeNamespace *ns,
867 uint64_t slba, uint32_t nlb)
868 {
869 uint64_t nsze = le64_to_cpu(ns->id_ns.nsze);
870
871 if (unlikely(UINT64_MAX - slba < nlb || slba + nlb > nsze)) {
872 return NVME_LBA_RANGE | NVME_DNR;
873 }
874
875 return NVME_SUCCESS;
876 }
877
878 static void nvme_rw_cb(void *opaque, int ret)
879 {
880 NvmeRequest *req = opaque;
881 NvmeCtrl *n = nvme_ctrl(req);
882
883 BlockBackend *blk = n->conf.blk;
884 BlockAcctCookie *acct = &req->acct;
885 BlockAcctStats *stats = blk_get_stats(blk);
886
887 Error *local_err = NULL;
888
889 trace_pci_nvme_rw_cb(nvme_cid(req), blk_name(blk));
890
891 if (!ret) {
892 block_acct_done(stats, acct);
893 } else {
894 uint16_t status;
895
896 block_acct_failed(stats, acct);
897
898 switch (req->cmd.opcode) {
899 case NVME_CMD_READ:
900 status = NVME_UNRECOVERED_READ;
901 break;
902 case NVME_CMD_FLUSH:
903 case NVME_CMD_WRITE:
904 case NVME_CMD_WRITE_ZEROES:
905 status = NVME_WRITE_FAULT;
906 break;
907 default:
908 status = NVME_INTERNAL_DEV_ERROR;
909 break;
910 }
911
912 trace_pci_nvme_err_aio(nvme_cid(req), strerror(ret), status);
913
914 error_setg_errno(&local_err, -ret, "aio failed");
915 error_report_err(local_err);
916
917 req->status = status;
918 }
919
920 nvme_enqueue_req_completion(nvme_cq(req), req);
921 }
922
923 static uint16_t nvme_do_aio(BlockBackend *blk, int64_t offset, size_t len,
924 NvmeRequest *req)
925 {
926 BlockAcctCookie *acct = &req->acct;
927 BlockAcctStats *stats = blk_get_stats(blk);
928
929 bool is_write = false;
930
931 trace_pci_nvme_do_aio(nvme_cid(req), req->cmd.opcode,
932 nvme_io_opc_str(req->cmd.opcode), blk_name(blk),
933 offset, len);
934
935 switch (req->cmd.opcode) {
936 case NVME_CMD_FLUSH:
937 block_acct_start(stats, acct, 0, BLOCK_ACCT_FLUSH);
938 req->aiocb = blk_aio_flush(blk, nvme_rw_cb, req);
939 break;
940
941 case NVME_CMD_WRITE_ZEROES:
942 block_acct_start(stats, acct, len, BLOCK_ACCT_WRITE);
943 req->aiocb = blk_aio_pwrite_zeroes(blk, offset, len,
944 BDRV_REQ_MAY_UNMAP, nvme_rw_cb,
945 req);
946 break;
947
948 case NVME_CMD_WRITE:
949 is_write = true;
950
951 /* fallthrough */
952
953 case NVME_CMD_READ:
954 block_acct_start(stats, acct, len,
955 is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ);
956
957 if (req->qsg.sg) {
958 if (is_write) {
959 req->aiocb = dma_blk_write(blk, &req->qsg, offset,
960 BDRV_SECTOR_SIZE, nvme_rw_cb, req);
961 } else {
962 req->aiocb = dma_blk_read(blk, &req->qsg, offset,
963 BDRV_SECTOR_SIZE, nvme_rw_cb, req);
964 }
965 } else {
966 if (is_write) {
967 req->aiocb = blk_aio_pwritev(blk, offset, &req->iov, 0,
968 nvme_rw_cb, req);
969 } else {
970 req->aiocb = blk_aio_preadv(blk, offset, &req->iov, 0,
971 nvme_rw_cb, req);
972 }
973 }
974
975 break;
976 }
977
978 return NVME_NO_COMPLETE;
979 }
980
981 static uint16_t nvme_flush(NvmeCtrl *n, NvmeRequest *req)
982 {
983 return nvme_do_aio(n->conf.blk, 0, 0, req);
984 }
985
986 static uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req)
987 {
988 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
989 NvmeNamespace *ns = req->ns;
990 uint64_t slba = le64_to_cpu(rw->slba);
991 uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1;
992 uint64_t offset = nvme_l2b(ns, slba);
993 uint32_t count = nvme_l2b(ns, nlb);
994 uint16_t status;
995
996 trace_pci_nvme_write_zeroes(nvme_cid(req), slba, nlb);
997
998 status = nvme_check_bounds(n, ns, slba, nlb);
999 if (status) {
1000 trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
1001 return status;
1002 }
1003
1004 return nvme_do_aio(n->conf.blk, offset, count, req);
1005 }
1006
1007 static uint16_t nvme_rw(NvmeCtrl *n, NvmeRequest *req)
1008 {
1009 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
1010 NvmeNamespace *ns = req->ns;
1011 uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1;
1012 uint64_t slba = le64_to_cpu(rw->slba);
1013
1014 uint64_t data_size = nvme_l2b(ns, nlb);
1015 uint64_t data_offset = nvme_l2b(ns, slba);
1016 enum BlockAcctType acct = req->cmd.opcode == NVME_CMD_WRITE ?
1017 BLOCK_ACCT_WRITE : BLOCK_ACCT_READ;
1018 uint16_t status;
1019
1020 trace_pci_nvme_rw(nvme_cid(req), nvme_io_opc_str(rw->opcode), nlb,
1021 data_size, slba);
1022
1023 status = nvme_check_mdts(n, data_size);
1024 if (status) {
1025 trace_pci_nvme_err_mdts(nvme_cid(req), data_size);
1026 goto invalid;
1027 }
1028
1029 status = nvme_check_bounds(n, ns, slba, nlb);
1030 if (status) {
1031 trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
1032 goto invalid;
1033 }
1034
1035 status = nvme_map_dptr(n, data_size, req);
1036 if (status) {
1037 goto invalid;
1038 }
1039
1040 return nvme_do_aio(n->conf.blk, data_offset, data_size, req);
1041
1042 invalid:
1043 block_acct_invalid(blk_get_stats(n->conf.blk), acct);
1044 return status;
1045 }
1046
1047 static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
1048 {
1049 uint32_t nsid = le32_to_cpu(req->cmd.nsid);
1050
1051 trace_pci_nvme_io_cmd(nvme_cid(req), nsid, nvme_sqid(req),
1052 req->cmd.opcode, nvme_io_opc_str(req->cmd.opcode));
1053
1054 if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
1055 trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces);
1056 return NVME_INVALID_NSID | NVME_DNR;
1057 }
1058
1059 req->ns = &n->namespaces[nsid - 1];
1060 switch (req->cmd.opcode) {
1061 case NVME_CMD_FLUSH:
1062 return nvme_flush(n, req);
1063 case NVME_CMD_WRITE_ZEROES:
1064 return nvme_write_zeroes(n, req);
1065 case NVME_CMD_WRITE:
1066 case NVME_CMD_READ:
1067 return nvme_rw(n, req);
1068 default:
1069 trace_pci_nvme_err_invalid_opc(req->cmd.opcode);
1070 return NVME_INVALID_OPCODE | NVME_DNR;
1071 }
1072 }
1073
1074 static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
1075 {
1076 n->sq[sq->sqid] = NULL;
1077 timer_del(sq->timer);
1078 timer_free(sq->timer);
1079 g_free(sq->io_req);
1080 if (sq->sqid) {
1081 g_free(sq);
1082 }
1083 }
1084
1085 static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeRequest *req)
1086 {
1087 NvmeDeleteQ *c = (NvmeDeleteQ *)&req->cmd;
1088 NvmeRequest *r, *next;
1089 NvmeSQueue *sq;
1090 NvmeCQueue *cq;
1091 uint16_t qid = le16_to_cpu(c->qid);
1092
1093 if (unlikely(!qid || nvme_check_sqid(n, qid))) {
1094 trace_pci_nvme_err_invalid_del_sq(qid);
1095 return NVME_INVALID_QID | NVME_DNR;
1096 }
1097
1098 trace_pci_nvme_del_sq(qid);
1099
1100 sq = n->sq[qid];
1101 while (!QTAILQ_EMPTY(&sq->out_req_list)) {
1102 r = QTAILQ_FIRST(&sq->out_req_list);
1103 assert(r->aiocb);
1104 blk_aio_cancel(r->aiocb);
1105 }
1106 if (!nvme_check_cqid(n, sq->cqid)) {
1107 cq = n->cq[sq->cqid];
1108 QTAILQ_REMOVE(&cq->sq_list, sq, entry);
1109
1110 nvme_post_cqes(cq);
1111 QTAILQ_FOREACH_SAFE(r, &cq->req_list, entry, next) {
1112 if (r->sq == sq) {
1113 QTAILQ_REMOVE(&cq->req_list, r, entry);
1114 QTAILQ_INSERT_TAIL(&sq->req_list, r, entry);
1115 }
1116 }
1117 }
1118
1119 nvme_free_sq(sq, n);
1120 return NVME_SUCCESS;
1121 }
1122
1123 static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
1124 uint16_t sqid, uint16_t cqid, uint16_t size)
1125 {
1126 int i;
1127 NvmeCQueue *cq;
1128
1129 sq->ctrl = n;
1130 sq->dma_addr = dma_addr;
1131 sq->sqid = sqid;
1132 sq->size = size;
1133 sq->cqid = cqid;
1134 sq->head = sq->tail = 0;
1135 sq->io_req = g_new0(NvmeRequest, sq->size);
1136
1137 QTAILQ_INIT(&sq->req_list);
1138 QTAILQ_INIT(&sq->out_req_list);
1139 for (i = 0; i < sq->size; i++) {
1140 sq->io_req[i].sq = sq;
1141 QTAILQ_INSERT_TAIL(&(sq->req_list), &sq->io_req[i], entry);
1142 }
1143 sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq);
1144
1145 assert(n->cq[cqid]);
1146 cq = n->cq[cqid];
1147 QTAILQ_INSERT_TAIL(&(cq->sq_list), sq, entry);
1148 n->sq[sqid] = sq;
1149 }
1150
1151 static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeRequest *req)
1152 {
1153 NvmeSQueue *sq;
1154 NvmeCreateSq *c = (NvmeCreateSq *)&req->cmd;
1155
1156 uint16_t cqid = le16_to_cpu(c->cqid);
1157 uint16_t sqid = le16_to_cpu(c->sqid);
1158 uint16_t qsize = le16_to_cpu(c->qsize);
1159 uint16_t qflags = le16_to_cpu(c->sq_flags);
1160 uint64_t prp1 = le64_to_cpu(c->prp1);
1161
1162 trace_pci_nvme_create_sq(prp1, sqid, cqid, qsize, qflags);
1163
1164 if (unlikely(!cqid || nvme_check_cqid(n, cqid))) {
1165 trace_pci_nvme_err_invalid_create_sq_cqid(cqid);
1166 return NVME_INVALID_CQID | NVME_DNR;
1167 }
1168 if (unlikely(!sqid || !nvme_check_sqid(n, sqid))) {
1169 trace_pci_nvme_err_invalid_create_sq_sqid(sqid);
1170 return NVME_INVALID_QID | NVME_DNR;
1171 }
1172 if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) {
1173 trace_pci_nvme_err_invalid_create_sq_size(qsize);
1174 return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
1175 }
1176 if (unlikely(!prp1 || prp1 & (n->page_size - 1))) {
1177 trace_pci_nvme_err_invalid_create_sq_addr(prp1);
1178 return NVME_INVALID_FIELD | NVME_DNR;
1179 }
1180 if (unlikely(!(NVME_SQ_FLAGS_PC(qflags)))) {
1181 trace_pci_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflags));
1182 return NVME_INVALID_FIELD | NVME_DNR;
1183 }
1184 sq = g_malloc0(sizeof(*sq));
1185 nvme_init_sq(sq, n, prp1, sqid, cqid, qsize + 1);
1186 return NVME_SUCCESS;
1187 }
1188
1189 static uint16_t nvme_smart_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
1190 uint64_t off, NvmeRequest *req)
1191 {
1192 uint32_t nsid = le32_to_cpu(req->cmd.nsid);
1193
1194 uint32_t trans_len;
1195 time_t current_ms;
1196 uint64_t units_read = 0, units_written = 0;
1197 uint64_t read_commands = 0, write_commands = 0;
1198 NvmeSmartLog smart;
1199 BlockAcctStats *s;
1200
1201 if (nsid && nsid != 0xffffffff) {
1202 return NVME_INVALID_FIELD | NVME_DNR;
1203 }
1204
1205 s = blk_get_stats(n->conf.blk);
1206
1207 units_read = s->nr_bytes[BLOCK_ACCT_READ] >> BDRV_SECTOR_BITS;
1208 units_written = s->nr_bytes[BLOCK_ACCT_WRITE] >> BDRV_SECTOR_BITS;
1209 read_commands = s->nr_ops[BLOCK_ACCT_READ];
1210 write_commands = s->nr_ops[BLOCK_ACCT_WRITE];
1211
1212 if (off > sizeof(smart)) {
1213 return NVME_INVALID_FIELD | NVME_DNR;
1214 }
1215
1216 trans_len = MIN(sizeof(smart) - off, buf_len);
1217
1218 memset(&smart, 0x0, sizeof(smart));
1219
1220 smart.data_units_read[0] = cpu_to_le64(DIV_ROUND_UP(units_read, 1000));
1221 smart.data_units_written[0] = cpu_to_le64(DIV_ROUND_UP(units_written,
1222 1000));
1223 smart.host_read_commands[0] = cpu_to_le64(read_commands);
1224 smart.host_write_commands[0] = cpu_to_le64(write_commands);
1225
1226 smart.temperature = cpu_to_le16(n->temperature);
1227
1228 if ((n->temperature >= n->features.temp_thresh_hi) ||
1229 (n->temperature <= n->features.temp_thresh_low)) {
1230 smart.critical_warning |= NVME_SMART_TEMPERATURE;
1231 }
1232
1233 current_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1234 smart.power_on_hours[0] =
1235 cpu_to_le64((((current_ms - n->starttime_ms) / 1000) / 60) / 60);
1236
1237 if (!rae) {
1238 nvme_clear_events(n, NVME_AER_TYPE_SMART);
1239 }
1240
1241 return nvme_dma(n, (uint8_t *) &smart + off, trans_len,
1242 DMA_DIRECTION_FROM_DEVICE, req);
1243 }
1244
1245 static uint16_t nvme_fw_log_info(NvmeCtrl *n, uint32_t buf_len, uint64_t off,
1246 NvmeRequest *req)
1247 {
1248 uint32_t trans_len;
1249 NvmeFwSlotInfoLog fw_log = {
1250 .afi = 0x1,
1251 };
1252
1253 strpadcpy((char *)&fw_log.frs1, sizeof(fw_log.frs1), "1.0", ' ');
1254
1255 if (off > sizeof(fw_log)) {
1256 return NVME_INVALID_FIELD | NVME_DNR;
1257 }
1258
1259 trans_len = MIN(sizeof(fw_log) - off, buf_len);
1260
1261 return nvme_dma(n, (uint8_t *) &fw_log + off, trans_len,
1262 DMA_DIRECTION_FROM_DEVICE, req);
1263 }
1264
1265 static uint16_t nvme_error_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
1266 uint64_t off, NvmeRequest *req)
1267 {
1268 uint32_t trans_len;
1269 NvmeErrorLog errlog;
1270
1271 if (!rae) {
1272 nvme_clear_events(n, NVME_AER_TYPE_ERROR);
1273 }
1274
1275 if (off > sizeof(errlog)) {
1276 return NVME_INVALID_FIELD | NVME_DNR;
1277 }
1278
1279 memset(&errlog, 0x0, sizeof(errlog));
1280
1281 trans_len = MIN(sizeof(errlog) - off, buf_len);
1282
1283 return nvme_dma(n, (uint8_t *)&errlog, trans_len,
1284 DMA_DIRECTION_FROM_DEVICE, req);
1285 }
1286
1287 static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req)
1288 {
1289 NvmeCmd *cmd = &req->cmd;
1290
1291 uint32_t dw10 = le32_to_cpu(cmd->cdw10);
1292 uint32_t dw11 = le32_to_cpu(cmd->cdw11);
1293 uint32_t dw12 = le32_to_cpu(cmd->cdw12);
1294 uint32_t dw13 = le32_to_cpu(cmd->cdw13);
1295 uint8_t lid = dw10 & 0xff;
1296 uint8_t lsp = (dw10 >> 8) & 0xf;
1297 uint8_t rae = (dw10 >> 15) & 0x1;
1298 uint32_t numdl, numdu;
1299 uint64_t off, lpol, lpou;
1300 size_t len;
1301 uint16_t status;
1302
1303 numdl = (dw10 >> 16);
1304 numdu = (dw11 & 0xffff);
1305 lpol = dw12;
1306 lpou = dw13;
1307
1308 len = (((numdu << 16) | numdl) + 1) << 2;
1309 off = (lpou << 32ULL) | lpol;
1310
1311 if (off & 0x3) {
1312 return NVME_INVALID_FIELD | NVME_DNR;
1313 }
1314
1315 trace_pci_nvme_get_log(nvme_cid(req), lid, lsp, rae, len, off);
1316
1317 status = nvme_check_mdts(n, len);
1318 if (status) {
1319 trace_pci_nvme_err_mdts(nvme_cid(req), len);
1320 return status;
1321 }
1322
1323 switch (lid) {
1324 case NVME_LOG_ERROR_INFO:
1325 return nvme_error_info(n, rae, len, off, req);
1326 case NVME_LOG_SMART_INFO:
1327 return nvme_smart_info(n, rae, len, off, req);
1328 case NVME_LOG_FW_SLOT_INFO:
1329 return nvme_fw_log_info(n, len, off, req);
1330 default:
1331 trace_pci_nvme_err_invalid_log_page(nvme_cid(req), lid);
1332 return NVME_INVALID_FIELD | NVME_DNR;
1333 }
1334 }
1335
1336 static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
1337 {
1338 n->cq[cq->cqid] = NULL;
1339 timer_del(cq->timer);
1340 timer_free(cq->timer);
1341 msix_vector_unuse(&n->parent_obj, cq->vector);
1342 if (cq->cqid) {
1343 g_free(cq);
1344 }
1345 }
1346
1347 static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeRequest *req)
1348 {
1349 NvmeDeleteQ *c = (NvmeDeleteQ *)&req->cmd;
1350 NvmeCQueue *cq;
1351 uint16_t qid = le16_to_cpu(c->qid);
1352
1353 if (unlikely(!qid || nvme_check_cqid(n, qid))) {
1354 trace_pci_nvme_err_invalid_del_cq_cqid(qid);
1355 return NVME_INVALID_CQID | NVME_DNR;
1356 }
1357
1358 cq = n->cq[qid];
1359 if (unlikely(!QTAILQ_EMPTY(&cq->sq_list))) {
1360 trace_pci_nvme_err_invalid_del_cq_notempty(qid);
1361 return NVME_INVALID_QUEUE_DEL;
1362 }
1363 nvme_irq_deassert(n, cq);
1364 trace_pci_nvme_del_cq(qid);
1365 nvme_free_cq(cq, n);
1366 return NVME_SUCCESS;
1367 }
1368
1369 static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
1370 uint16_t cqid, uint16_t vector, uint16_t size,
1371 uint16_t irq_enabled)
1372 {
1373 int ret;
1374
1375 ret = msix_vector_use(&n->parent_obj, vector);
1376 assert(ret == 0);
1377 cq->ctrl = n;
1378 cq->cqid = cqid;
1379 cq->size = size;
1380 cq->dma_addr = dma_addr;
1381 cq->phase = 1;
1382 cq->irq_enabled = irq_enabled;
1383 cq->vector = vector;
1384 cq->head = cq->tail = 0;
1385 QTAILQ_INIT(&cq->req_list);
1386 QTAILQ_INIT(&cq->sq_list);
1387 n->cq[cqid] = cq;
1388 cq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_post_cqes, cq);
1389 }
1390
1391 static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequest *req)
1392 {
1393 NvmeCQueue *cq;
1394 NvmeCreateCq *c = (NvmeCreateCq *)&req->cmd;
1395 uint16_t cqid = le16_to_cpu(c->cqid);
1396 uint16_t vector = le16_to_cpu(c->irq_vector);
1397 uint16_t qsize = le16_to_cpu(c->qsize);
1398 uint16_t qflags = le16_to_cpu(c->cq_flags);
1399 uint64_t prp1 = le64_to_cpu(c->prp1);
1400
1401 trace_pci_nvme_create_cq(prp1, cqid, vector, qsize, qflags,
1402 NVME_CQ_FLAGS_IEN(qflags) != 0);
1403
1404 if (unlikely(!cqid || !nvme_check_cqid(n, cqid))) {
1405 trace_pci_nvme_err_invalid_create_cq_cqid(cqid);
1406 return NVME_INVALID_CQID | NVME_DNR;
1407 }
1408 if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) {
1409 trace_pci_nvme_err_invalid_create_cq_size(qsize);
1410 return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
1411 }
1412 if (unlikely(!prp1)) {
1413 trace_pci_nvme_err_invalid_create_cq_addr(prp1);
1414 return NVME_INVALID_FIELD | NVME_DNR;
1415 }
1416 if (unlikely(!msix_enabled(&n->parent_obj) && vector)) {
1417 trace_pci_nvme_err_invalid_create_cq_vector(vector);
1418 return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
1419 }
1420 if (unlikely(vector >= n->params.msix_qsize)) {
1421 trace_pci_nvme_err_invalid_create_cq_vector(vector);
1422 return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
1423 }
1424 if (unlikely(!(NVME_CQ_FLAGS_PC(qflags)))) {
1425 trace_pci_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflags));
1426 return NVME_INVALID_FIELD | NVME_DNR;
1427 }
1428
1429 cq = g_malloc0(sizeof(*cq));
1430 nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1,
1431 NVME_CQ_FLAGS_IEN(qflags));
1432
1433 /*
1434 * It is only required to set qs_created when creating a completion queue;
1435 * creating a submission queue without a matching completion queue will
1436 * fail.
1437 */
1438 n->qs_created = true;
1439 return NVME_SUCCESS;
1440 }
1441
1442 static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeRequest *req)
1443 {
1444 trace_pci_nvme_identify_ctrl();
1445
1446 return nvme_dma(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl),
1447 DMA_DIRECTION_FROM_DEVICE, req);
1448 }
1449
1450 static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req)
1451 {
1452 NvmeNamespace *ns;
1453 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
1454 uint32_t nsid = le32_to_cpu(c->nsid);
1455
1456 trace_pci_nvme_identify_ns(nsid);
1457
1458 if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
1459 trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces);
1460 return NVME_INVALID_NSID | NVME_DNR;
1461 }
1462
1463 ns = &n->namespaces[nsid - 1];
1464
1465 return nvme_dma(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns),
1466 DMA_DIRECTION_FROM_DEVICE, req);
1467 }
1468
1469 static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
1470 {
1471 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
1472 static const int data_len = NVME_IDENTIFY_DATA_SIZE;
1473 uint32_t min_nsid = le32_to_cpu(c->nsid);
1474 uint32_t *list;
1475 uint16_t ret;
1476 int j = 0;
1477
1478 trace_pci_nvme_identify_nslist(min_nsid);
1479
1480 /*
1481 * Both 0xffffffff (NVME_NSID_BROADCAST) and 0xfffffffe are invalid values
1482 * since the Active Namespace ID List should return namespaces with ids
1483 * *higher* than the NSID specified in the command. This is also specified
1484 * in the spec (NVM Express v1.3d, Section 5.15.4).
1485 */
1486 if (min_nsid >= NVME_NSID_BROADCAST - 1) {
1487 return NVME_INVALID_NSID | NVME_DNR;
1488 }
1489
1490 list = g_malloc0(data_len);
1491 for (int i = 1; i <= n->num_namespaces; i++) {
1492 if (i <= min_nsid) {
1493 continue;
1494 }
1495 list[j++] = cpu_to_le32(i);
1496 if (j == data_len / sizeof(uint32_t)) {
1497 break;
1498 }
1499 }
1500 ret = nvme_dma(n, (uint8_t *)list, data_len, DMA_DIRECTION_FROM_DEVICE,
1501 req);
1502 g_free(list);
1503 return ret;
1504 }
1505
1506 static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
1507 {
1508 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
1509 uint32_t nsid = le32_to_cpu(c->nsid);
1510
1511 uint8_t list[NVME_IDENTIFY_DATA_SIZE];
1512
1513 struct data {
1514 struct {
1515 NvmeIdNsDescr hdr;
1516 uint8_t v[16];
1517 } uuid;
1518 };
1519
1520 struct data *ns_descrs = (struct data *)list;
1521
1522 trace_pci_nvme_identify_ns_descr_list(nsid);
1523
1524 if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
1525 trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces);
1526 return NVME_INVALID_NSID | NVME_DNR;
1527 }
1528
1529 memset(list, 0x0, sizeof(list));
1530
1531 /*
1532 * Because the NGUID and EUI64 fields are 0 in the Identify Namespace data
1533 * structure, a Namespace UUID (nidt = 0x3) must be reported in the
1534 * Namespace Identification Descriptor. Add a very basic Namespace UUID
1535 * here.
1536 */
1537 ns_descrs->uuid.hdr.nidt = NVME_NIDT_UUID;
1538 ns_descrs->uuid.hdr.nidl = NVME_NIDT_UUID_LEN;
1539 stl_be_p(&ns_descrs->uuid.v, nsid);
1540
1541 return nvme_dma(n, list, NVME_IDENTIFY_DATA_SIZE,
1542 DMA_DIRECTION_FROM_DEVICE, req);
1543 }
1544
1545 static uint16_t nvme_identify(NvmeCtrl *n, NvmeRequest *req)
1546 {
1547 NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
1548
1549 switch (le32_to_cpu(c->cns)) {
1550 case NVME_ID_CNS_NS:
1551 return nvme_identify_ns(n, req);
1552 case NVME_ID_CNS_CTRL:
1553 return nvme_identify_ctrl(n, req);
1554 case NVME_ID_CNS_NS_ACTIVE_LIST:
1555 return nvme_identify_nslist(n, req);
1556 case NVME_ID_CNS_NS_DESCR_LIST:
1557 return nvme_identify_ns_descr_list(n, req);
1558 default:
1559 trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns));
1560 return NVME_INVALID_FIELD | NVME_DNR;
1561 }
1562 }
1563
1564 static uint16_t nvme_abort(NvmeCtrl *n, NvmeRequest *req)
1565 {
1566 uint16_t sqid = le32_to_cpu(req->cmd.cdw10) & 0xffff;
1567
1568 req->cqe.result = 1;
1569 if (nvme_check_sqid(n, sqid)) {
1570 return NVME_INVALID_FIELD | NVME_DNR;
1571 }
1572
1573 return NVME_SUCCESS;
1574 }
1575
1576 static inline void nvme_set_timestamp(NvmeCtrl *n, uint64_t ts)
1577 {
1578 trace_pci_nvme_setfeat_timestamp(ts);
1579
1580 n->host_timestamp = le64_to_cpu(ts);
1581 n->timestamp_set_qemu_clock_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1582 }
1583
1584 static inline uint64_t nvme_get_timestamp(const NvmeCtrl *n)
1585 {
1586 uint64_t current_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1587 uint64_t elapsed_time = current_time - n->timestamp_set_qemu_clock_ms;
1588
1589 union nvme_timestamp {
1590 struct {
1591 uint64_t timestamp:48;
1592 uint64_t sync:1;
1593 uint64_t origin:3;
1594 uint64_t rsvd1:12;
1595 };
1596 uint64_t all;
1597 };
1598
1599 union nvme_timestamp ts;
1600 ts.all = 0;
1601 ts.timestamp = n->host_timestamp + elapsed_time;
1602
1603 /* If the host timestamp is non-zero, set the timestamp origin */
1604 ts.origin = n->host_timestamp ? 0x01 : 0x00;
1605
1606 trace_pci_nvme_getfeat_timestamp(ts.all);
1607
1608 return cpu_to_le64(ts.all);
1609 }
1610
1611 static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeRequest *req)
1612 {
1613 uint64_t timestamp = nvme_get_timestamp(n);
1614
1615 return nvme_dma(n, (uint8_t *)&timestamp, sizeof(timestamp),
1616 DMA_DIRECTION_FROM_DEVICE, req);
1617 }
1618
1619 static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRequest *req)
1620 {
1621 NvmeCmd *cmd = &req->cmd;
1622 uint32_t dw10 = le32_to_cpu(cmd->cdw10);
1623 uint32_t dw11 = le32_to_cpu(cmd->cdw11);
1624 uint32_t nsid = le32_to_cpu(cmd->nsid);
1625 uint32_t result;
1626 uint8_t fid = NVME_GETSETFEAT_FID(dw10);
1627 NvmeGetFeatureSelect sel = NVME_GETFEAT_SELECT(dw10);
1628 uint16_t iv;
1629
1630 static const uint32_t nvme_feature_default[NVME_FID_MAX] = {
1631 [NVME_ARBITRATION] = NVME_ARB_AB_NOLIMIT,
1632 };
1633
1634 trace_pci_nvme_getfeat(nvme_cid(req), fid, sel, dw11);
1635
1636 if (!nvme_feature_support[fid]) {
1637 return NVME_INVALID_FIELD | NVME_DNR;
1638 }
1639
1640 if (nvme_feature_cap[fid] & NVME_FEAT_CAP_NS) {
1641 if (!nsid || nsid > n->num_namespaces) {
1642 /*
1643 * The Reservation Notification Mask and Reservation Persistence
1644 * features require a status code of Invalid Field in Command when
1645 * NSID is 0xFFFFFFFF. Since the device does not support those
1646 * features we can always return Invalid Namespace or Format as we
1647 * should do for all other features.
1648 */
1649 return NVME_INVALID_NSID | NVME_DNR;
1650 }
1651 }
1652
1653 switch (sel) {
1654 case NVME_GETFEAT_SELECT_CURRENT:
1655 break;
1656 case NVME_GETFEAT_SELECT_SAVED:
1657 /* no features are saveable by the controller; fallthrough */
1658 case NVME_GETFEAT_SELECT_DEFAULT:
1659 goto defaults;
1660 case NVME_GETFEAT_SELECT_CAP:
1661 result = nvme_feature_cap[fid];
1662 goto out;
1663 }
1664
1665 switch (fid) {
1666 case NVME_TEMPERATURE_THRESHOLD:
1667 result = 0;
1668
1669 /*
1670 * The controller only implements the Composite Temperature sensor, so
1671 * return 0 for all other sensors.
1672 */
1673 if (NVME_TEMP_TMPSEL(dw11) != NVME_TEMP_TMPSEL_COMPOSITE) {
1674 goto out;
1675 }
1676
1677 switch (NVME_TEMP_THSEL(dw11)) {
1678 case NVME_TEMP_THSEL_OVER:
1679 result = n->features.temp_thresh_hi;
1680 goto out;
1681 case NVME_TEMP_THSEL_UNDER:
1682 result = n->features.temp_thresh_low;
1683 goto out;
1684 }
1685
1686 return NVME_INVALID_FIELD | NVME_DNR;
1687 case NVME_VOLATILE_WRITE_CACHE:
1688 result = blk_enable_write_cache(n->conf.blk);
1689 trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled");
1690 goto out;
1691 case NVME_ASYNCHRONOUS_EVENT_CONF:
1692 result = n->features.async_config;
1693 goto out;
1694 case NVME_TIMESTAMP:
1695 return nvme_get_feature_timestamp(n, req);
1696 default:
1697 break;
1698 }
1699
1700 defaults:
1701 switch (fid) {
1702 case NVME_TEMPERATURE_THRESHOLD:
1703 result = 0;
1704
1705 if (NVME_TEMP_TMPSEL(dw11) != NVME_TEMP_TMPSEL_COMPOSITE) {
1706 break;
1707 }
1708
1709 if (NVME_TEMP_THSEL(dw11) == NVME_TEMP_THSEL_OVER) {
1710 result = NVME_TEMPERATURE_WARNING;
1711 }
1712
1713 break;
1714 case NVME_NUMBER_OF_QUEUES:
1715 result = (n->params.max_ioqpairs - 1) |
1716 ((n->params.max_ioqpairs - 1) << 16);
1717 trace_pci_nvme_getfeat_numq(result);
1718 break;
1719 case NVME_INTERRUPT_VECTOR_CONF:
1720 iv = dw11 & 0xffff;
1721 if (iv >= n->params.max_ioqpairs + 1) {
1722 return NVME_INVALID_FIELD | NVME_DNR;
1723 }
1724
1725 result = iv;
1726 if (iv == n->admin_cq.vector) {
1727 result |= NVME_INTVC_NOCOALESCING;
1728 }
1729
1730 break;
1731 default:
1732 result = nvme_feature_default[fid];
1733 break;
1734 }
1735
1736 out:
1737 req->cqe.result = cpu_to_le32(result);
1738 return NVME_SUCCESS;
1739 }
1740
1741 static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeRequest *req)
1742 {
1743 uint16_t ret;
1744 uint64_t timestamp;
1745
1746 ret = nvme_dma(n, (uint8_t *)&timestamp, sizeof(timestamp),
1747 DMA_DIRECTION_TO_DEVICE, req);
1748 if (ret != NVME_SUCCESS) {
1749 return ret;
1750 }
1751
1752 nvme_set_timestamp(n, timestamp);
1753
1754 return NVME_SUCCESS;
1755 }
1756
1757 static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req)
1758 {
1759 NvmeCmd *cmd = &req->cmd;
1760 uint32_t dw10 = le32_to_cpu(cmd->cdw10);
1761 uint32_t dw11 = le32_to_cpu(cmd->cdw11);
1762 uint32_t nsid = le32_to_cpu(cmd->nsid);
1763 uint8_t fid = NVME_GETSETFEAT_FID(dw10);
1764 uint8_t save = NVME_SETFEAT_SAVE(dw10);
1765
1766 trace_pci_nvme_setfeat(nvme_cid(req), fid, save, dw11);
1767
1768 if (save) {
1769 return NVME_FID_NOT_SAVEABLE | NVME_DNR;
1770 }
1771
1772 if (!nvme_feature_support[fid]) {
1773 return NVME_INVALID_FIELD | NVME_DNR;
1774 }
1775
1776 if (nvme_feature_cap[fid] & NVME_FEAT_CAP_NS) {
1777 if (!nsid || (nsid != NVME_NSID_BROADCAST &&
1778 nsid > n->num_namespaces)) {
1779 return NVME_INVALID_NSID | NVME_DNR;
1780 }
1781 } else if (nsid && nsid != NVME_NSID_BROADCAST) {
1782 if (nsid > n->num_namespaces) {
1783 return NVME_INVALID_NSID | NVME_DNR;
1784 }
1785
1786 return NVME_FEAT_NOT_NS_SPEC | NVME_DNR;
1787 }
1788
1789 if (!(nvme_feature_cap[fid] & NVME_FEAT_CAP_CHANGE)) {
1790 return NVME_FEAT_NOT_CHANGEABLE | NVME_DNR;
1791 }
1792
1793 switch (fid) {
1794 case NVME_TEMPERATURE_THRESHOLD:
1795 if (NVME_TEMP_TMPSEL(dw11) != NVME_TEMP_TMPSEL_COMPOSITE) {
1796 break;
1797 }
1798
1799 switch (NVME_TEMP_THSEL(dw11)) {
1800 case NVME_TEMP_THSEL_OVER:
1801 n->features.temp_thresh_hi = NVME_TEMP_TMPTH(dw11);
1802 break;
1803 case NVME_TEMP_THSEL_UNDER:
1804 n->features.temp_thresh_low = NVME_TEMP_TMPTH(dw11);
1805 break;
1806 default:
1807 return NVME_INVALID_FIELD | NVME_DNR;
1808 }
1809
1810 if (((n->temperature >= n->features.temp_thresh_hi) ||
1811 (n->temperature <= n->features.temp_thresh_low)) &&
1812 NVME_AEC_SMART(n->features.async_config) & NVME_SMART_TEMPERATURE) {
1813 nvme_enqueue_event(n, NVME_AER_TYPE_SMART,
1814 NVME_AER_INFO_SMART_TEMP_THRESH,
1815 NVME_LOG_SMART_INFO);
1816 }
1817
1818 break;
1819 case NVME_VOLATILE_WRITE_CACHE:
1820 if (!(dw11 & 0x1) && blk_enable_write_cache(n->conf.blk)) {
1821 blk_flush(n->conf.blk);
1822 }
1823
1824 blk_set_enable_write_cache(n->conf.blk, dw11 & 1);
1825 break;
1826 case NVME_NUMBER_OF_QUEUES:
1827 if (n->qs_created) {
1828 return NVME_CMD_SEQ_ERROR | NVME_DNR;
1829 }
1830
1831 /*
1832 * NVMe v1.3, Section 5.21.1.7: 0xffff is not an allowed value for NCQR
1833 * and NSQR.
1834 */
1835 if ((dw11 & 0xffff) == 0xffff || ((dw11 >> 16) & 0xffff) == 0xffff) {
1836 return NVME_INVALID_FIELD | NVME_DNR;
1837 }
1838
1839 trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1,
1840 ((dw11 >> 16) & 0xFFFF) + 1,
1841 n->params.max_ioqpairs,
1842 n->params.max_ioqpairs);
1843 req->cqe.result = cpu_to_le32((n->params.max_ioqpairs - 1) |
1844 ((n->params.max_ioqpairs - 1) << 16));
1845 break;
1846 case NVME_ASYNCHRONOUS_EVENT_CONF:
1847 n->features.async_config = dw11;
1848 break;
1849 case NVME_TIMESTAMP:
1850 return nvme_set_feature_timestamp(n, req);
1851 default:
1852 return NVME_FEAT_NOT_CHANGEABLE | NVME_DNR;
1853 }
1854 return NVME_SUCCESS;
1855 }
1856
1857 static uint16_t nvme_aer(NvmeCtrl *n, NvmeRequest *req)
1858 {
1859 trace_pci_nvme_aer(nvme_cid(req));
1860
1861 if (n->outstanding_aers > n->params.aerl) {
1862 trace_pci_nvme_aer_aerl_exceeded();
1863 return NVME_AER_LIMIT_EXCEEDED;
1864 }
1865
1866 n->aer_reqs[n->outstanding_aers] = req;
1867 n->outstanding_aers++;
1868
1869 if (!QTAILQ_EMPTY(&n->aer_queue)) {
1870 nvme_process_aers(n);
1871 }
1872
1873 return NVME_NO_COMPLETE;
1874 }
1875
1876 static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req)
1877 {
1878 trace_pci_nvme_admin_cmd(nvme_cid(req), nvme_sqid(req), req->cmd.opcode,
1879 nvme_adm_opc_str(req->cmd.opcode));
1880
1881 switch (req->cmd.opcode) {
1882 case NVME_ADM_CMD_DELETE_SQ:
1883 return nvme_del_sq(n, req);
1884 case NVME_ADM_CMD_CREATE_SQ:
1885 return nvme_create_sq(n, req);
1886 case NVME_ADM_CMD_GET_LOG_PAGE:
1887 return nvme_get_log(n, req);
1888 case NVME_ADM_CMD_DELETE_CQ:
1889 return nvme_del_cq(n, req);
1890 case NVME_ADM_CMD_CREATE_CQ:
1891 return nvme_create_cq(n, req);
1892 case NVME_ADM_CMD_IDENTIFY:
1893 return nvme_identify(n, req);
1894 case NVME_ADM_CMD_ABORT:
1895 return nvme_abort(n, req);
1896 case NVME_ADM_CMD_SET_FEATURES:
1897 return nvme_set_feature(n, req);
1898 case NVME_ADM_CMD_GET_FEATURES:
1899 return nvme_get_feature(n, req);
1900 case NVME_ADM_CMD_ASYNC_EV_REQ:
1901 return nvme_aer(n, req);
1902 default:
1903 trace_pci_nvme_err_invalid_admin_opc(req->cmd.opcode);
1904 return NVME_INVALID_OPCODE | NVME_DNR;
1905 }
1906 }
1907
1908 static void nvme_process_sq(void *opaque)
1909 {
1910 NvmeSQueue *sq = opaque;
1911 NvmeCtrl *n = sq->ctrl;
1912 NvmeCQueue *cq = n->cq[sq->cqid];
1913
1914 uint16_t status;
1915 hwaddr addr;
1916 NvmeCmd cmd;
1917 NvmeRequest *req;
1918
1919 while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) {
1920 addr = sq->dma_addr + sq->head * n->sqe_size;
1921 if (nvme_addr_read(n, addr, (void *)&cmd, sizeof(cmd))) {
1922 trace_pci_nvme_err_addr_read(addr);
1923 trace_pci_nvme_err_cfs();
1924 n->bar.csts = NVME_CSTS_FAILED;
1925 break;
1926 }
1927 nvme_inc_sq_head(sq);
1928
1929 req = QTAILQ_FIRST(&sq->req_list);
1930 QTAILQ_REMOVE(&sq->req_list, req, entry);
1931 QTAILQ_INSERT_TAIL(&sq->out_req_list, req, entry);
1932 nvme_req_clear(req);
1933 req->cqe.cid = cmd.cid;
1934 memcpy(&req->cmd, &cmd, sizeof(NvmeCmd));
1935
1936 status = sq->sqid ? nvme_io_cmd(n, req) :
1937 nvme_admin_cmd(n, req);
1938 if (status != NVME_NO_COMPLETE) {
1939 req->status = status;
1940 nvme_enqueue_req_completion(cq, req);
1941 }
1942 }
1943 }
1944
1945 static void nvme_clear_ctrl(NvmeCtrl *n)
1946 {
1947 int i;
1948
1949 blk_drain(n->conf.blk);
1950
1951 for (i = 0; i < n->params.max_ioqpairs + 1; i++) {
1952 if (n->sq[i] != NULL) {
1953 nvme_free_sq(n->sq[i], n);
1954 }
1955 }
1956 for (i = 0; i < n->params.max_ioqpairs + 1; i++) {
1957 if (n->cq[i] != NULL) {
1958 nvme_free_cq(n->cq[i], n);
1959 }
1960 }
1961
1962 while (!QTAILQ_EMPTY(&n->aer_queue)) {
1963 NvmeAsyncEvent *event = QTAILQ_FIRST(&n->aer_queue);
1964 QTAILQ_REMOVE(&n->aer_queue, event, entry);
1965 g_free(event);
1966 }
1967
1968 n->aer_queued = 0;
1969 n->outstanding_aers = 0;
1970 n->qs_created = false;
1971
1972 blk_flush(n->conf.blk);
1973 n->bar.cc = 0;
1974 }
1975
1976 static int nvme_start_ctrl(NvmeCtrl *n)
1977 {
1978 uint32_t page_bits = NVME_CC_MPS(n->bar.cc) + 12;
1979 uint32_t page_size = 1 << page_bits;
1980
1981 if (unlikely(n->cq[0])) {
1982 trace_pci_nvme_err_startfail_cq();
1983 return -1;
1984 }
1985 if (unlikely(n->sq[0])) {
1986 trace_pci_nvme_err_startfail_sq();
1987 return -1;
1988 }
1989 if (unlikely(!n->bar.asq)) {
1990 trace_pci_nvme_err_startfail_nbarasq();
1991 return -1;
1992 }
1993 if (unlikely(!n->bar.acq)) {
1994 trace_pci_nvme_err_startfail_nbaracq();
1995 return -1;
1996 }
1997 if (unlikely(n->bar.asq & (page_size - 1))) {
1998 trace_pci_nvme_err_startfail_asq_misaligned(n->bar.asq);
1999 return -1;
2000 }
2001 if (unlikely(n->bar.acq & (page_size - 1))) {
2002 trace_pci_nvme_err_startfail_acq_misaligned(n->bar.acq);
2003 return -1;
2004 }
2005 if (unlikely(NVME_CC_MPS(n->bar.cc) <
2006 NVME_CAP_MPSMIN(n->bar.cap))) {
2007 trace_pci_nvme_err_startfail_page_too_small(
2008 NVME_CC_MPS(n->bar.cc),
2009 NVME_CAP_MPSMIN(n->bar.cap));
2010 return -1;
2011 }
2012 if (unlikely(NVME_CC_MPS(n->bar.cc) >
2013 NVME_CAP_MPSMAX(n->bar.cap))) {
2014 trace_pci_nvme_err_startfail_page_too_large(
2015 NVME_CC_MPS(n->bar.cc),
2016 NVME_CAP_MPSMAX(n->bar.cap));
2017 return -1;
2018 }
2019 if (unlikely(NVME_CC_IOCQES(n->bar.cc) <
2020 NVME_CTRL_CQES_MIN(n->id_ctrl.cqes))) {
2021 trace_pci_nvme_err_startfail_cqent_too_small(
2022 NVME_CC_IOCQES(n->bar.cc),
2023 NVME_CTRL_CQES_MIN(n->bar.cap));
2024 return -1;
2025 }
2026 if (unlikely(NVME_CC_IOCQES(n->bar.cc) >
2027 NVME_CTRL_CQES_MAX(n->id_ctrl.cqes))) {
2028 trace_pci_nvme_err_startfail_cqent_too_large(
2029 NVME_CC_IOCQES(n->bar.cc),
2030 NVME_CTRL_CQES_MAX(n->bar.cap));
2031 return -1;
2032 }
2033 if (unlikely(NVME_CC_IOSQES(n->bar.cc) <
2034 NVME_CTRL_SQES_MIN(n->id_ctrl.sqes))) {
2035 trace_pci_nvme_err_startfail_sqent_too_small(
2036 NVME_CC_IOSQES(n->bar.cc),
2037 NVME_CTRL_SQES_MIN(n->bar.cap));
2038 return -1;
2039 }
2040 if (unlikely(NVME_CC_IOSQES(n->bar.cc) >
2041 NVME_CTRL_SQES_MAX(n->id_ctrl.sqes))) {
2042 trace_pci_nvme_err_startfail_sqent_too_large(
2043 NVME_CC_IOSQES(n->bar.cc),
2044 NVME_CTRL_SQES_MAX(n->bar.cap));
2045 return -1;
2046 }
2047 if (unlikely(!NVME_AQA_ASQS(n->bar.aqa))) {
2048 trace_pci_nvme_err_startfail_asqent_sz_zero();
2049 return -1;
2050 }
2051 if (unlikely(!NVME_AQA_ACQS(n->bar.aqa))) {
2052 trace_pci_nvme_err_startfail_acqent_sz_zero();
2053 return -1;
2054 }
2055
2056 n->page_bits = page_bits;
2057 n->page_size = page_size;
2058 n->max_prp_ents = n->page_size / sizeof(uint64_t);
2059 n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc);
2060 n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc);
2061 nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0,
2062 NVME_AQA_ACQS(n->bar.aqa) + 1, 1);
2063 nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0,
2064 NVME_AQA_ASQS(n->bar.aqa) + 1);
2065
2066 nvme_set_timestamp(n, 0ULL);
2067
2068 QTAILQ_INIT(&n->aer_queue);
2069
2070 return 0;
2071 }
2072
2073 static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
2074 unsigned size)
2075 {
2076 if (unlikely(offset & (sizeof(uint32_t) - 1))) {
2077 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32,
2078 "MMIO write not 32-bit aligned,"
2079 " offset=0x%"PRIx64"", offset);
2080 /* should be ignored, fall through for now */
2081 }
2082
2083 if (unlikely(size < sizeof(uint32_t))) {
2084 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_toosmall,
2085 "MMIO write smaller than 32-bits,"
2086 " offset=0x%"PRIx64", size=%u",
2087 offset, size);
2088 /* should be ignored, fall through for now */
2089 }
2090
2091 switch (offset) {
2092 case 0xc: /* INTMS */
2093 if (unlikely(msix_enabled(&(n->parent_obj)))) {
2094 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix,
2095 "undefined access to interrupt mask set"
2096 " when MSI-X is enabled");
2097 /* should be ignored, fall through for now */
2098 }
2099 n->bar.intms |= data & 0xffffffff;
2100 n->bar.intmc = n->bar.intms;
2101 trace_pci_nvme_mmio_intm_set(data & 0xffffffff, n->bar.intmc);
2102 nvme_irq_check(n);
2103 break;
2104 case 0x10: /* INTMC */
2105 if (unlikely(msix_enabled(&(n->parent_obj)))) {
2106 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix,
2107 "undefined access to interrupt mask clr"
2108 " when MSI-X is enabled");
2109 /* should be ignored, fall through for now */
2110 }
2111 n->bar.intms &= ~(data & 0xffffffff);
2112 n->bar.intmc = n->bar.intms;
2113 trace_pci_nvme_mmio_intm_clr(data & 0xffffffff, n->bar.intmc);
2114 nvme_irq_check(n);
2115 break;
2116 case 0x14: /* CC */
2117 trace_pci_nvme_mmio_cfg(data & 0xffffffff);
2118 /* Windows first sends data, then sends enable bit */
2119 if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) &&
2120 !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc))
2121 {
2122 n->bar.cc = data;
2123 }
2124
2125 if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) {
2126 n->bar.cc = data;
2127 if (unlikely(nvme_start_ctrl(n))) {
2128 trace_pci_nvme_err_startfail();
2129 n->bar.csts = NVME_CSTS_FAILED;
2130 } else {
2131 trace_pci_nvme_mmio_start_success();
2132 n->bar.csts = NVME_CSTS_READY;
2133 }
2134 } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) {
2135 trace_pci_nvme_mmio_stopped();
2136 nvme_clear_ctrl(n);
2137 n->bar.csts &= ~NVME_CSTS_READY;
2138 }
2139 if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) {
2140 trace_pci_nvme_mmio_shutdown_set();
2141 nvme_clear_ctrl(n);
2142 n->bar.cc = data;
2143 n->bar.csts |= NVME_CSTS_SHST_COMPLETE;
2144 } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) {
2145 trace_pci_nvme_mmio_shutdown_cleared();
2146 n->bar.csts &= ~NVME_CSTS_SHST_COMPLETE;
2147 n->bar.cc = data;
2148 }
2149 break;
2150 case 0x1C: /* CSTS */
2151 if (data & (1 << 4)) {
2152 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported,
2153 "attempted to W1C CSTS.NSSRO"
2154 " but CAP.NSSRS is zero (not supported)");
2155 } else if (data != 0) {
2156 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ro_csts,
2157 "attempted to set a read only bit"
2158 " of controller status");
2159 }
2160 break;
2161 case 0x20: /* NSSR */
2162 if (data == 0x4E564D65) {
2163 trace_pci_nvme_ub_mmiowr_ssreset_unsupported();
2164 } else {
2165 /* The spec says that writes of other values have no effect */
2166 return;
2167 }
2168 break;
2169 case 0x24: /* AQA */
2170 n->bar.aqa = data & 0xffffffff;
2171 trace_pci_nvme_mmio_aqattr(data & 0xffffffff);
2172 break;
2173 case 0x28: /* ASQ */
2174 n->bar.asq = data;
2175 trace_pci_nvme_mmio_asqaddr(data);
2176 break;
2177 case 0x2c: /* ASQ hi */
2178 n->bar.asq |= data << 32;
2179 trace_pci_nvme_mmio_asqaddr_hi(data, n->bar.asq);
2180 break;
2181 case 0x30: /* ACQ */
2182 trace_pci_nvme_mmio_acqaddr(data);
2183 n->bar.acq = data;
2184 break;
2185 case 0x34: /* ACQ hi */
2186 n->bar.acq |= data << 32;
2187 trace_pci_nvme_mmio_acqaddr_hi(data, n->bar.acq);
2188 break;
2189 case 0x38: /* CMBLOC */
2190 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbloc_reserved,
2191 "invalid write to reserved CMBLOC"
2192 " when CMBSZ is zero, ignored");
2193 return;
2194 case 0x3C: /* CMBSZ */
2195 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly,
2196 "invalid write to read only CMBSZ, ignored");
2197 return;
2198 case 0xE00: /* PMRCAP */
2199 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly,
2200 "invalid write to PMRCAP register, ignored");
2201 return;
2202 case 0xE04: /* TODO PMRCTL */
2203 break;
2204 case 0xE08: /* PMRSTS */
2205 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly,
2206 "invalid write to PMRSTS register, ignored");
2207 return;
2208 case 0xE0C: /* PMREBS */
2209 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly,
2210 "invalid write to PMREBS register, ignored");
2211 return;
2212 case 0xE10: /* PMRSWTP */
2213 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly,
2214 "invalid write to PMRSWTP register, ignored");
2215 return;
2216 case 0xE14: /* TODO PMRMSC */
2217 break;
2218 default:
2219 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid,
2220 "invalid MMIO write,"
2221 " offset=0x%"PRIx64", data=%"PRIx64"",
2222 offset, data);
2223 break;
2224 }
2225 }
2226
2227 static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
2228 {
2229 NvmeCtrl *n = (NvmeCtrl *)opaque;
2230 uint8_t *ptr = (uint8_t *)&n->bar;
2231 uint64_t val = 0;
2232
2233 trace_pci_nvme_mmio_read(addr);
2234
2235 if (unlikely(addr & (sizeof(uint32_t) - 1))) {
2236 NVME_GUEST_ERR(pci_nvme_ub_mmiord_misaligned32,
2237 "MMIO read not 32-bit aligned,"
2238 " offset=0x%"PRIx64"", addr);
2239 /* should RAZ, fall through for now */
2240 } else if (unlikely(size < sizeof(uint32_t))) {
2241 NVME_GUEST_ERR(pci_nvme_ub_mmiord_toosmall,
2242 "MMIO read smaller than 32-bits,"
2243 " offset=0x%"PRIx64"", addr);
2244 /* should RAZ, fall through for now */
2245 }
2246
2247 if (addr < sizeof(n->bar)) {
2248 /*
2249 * When PMRWBM bit 1 is set then read from
2250 * from PMRSTS should ensure prior writes
2251 * made it to persistent media
2252 */
2253 if (addr == 0xE08 &&
2254 (NVME_PMRCAP_PMRWBM(n->bar.pmrcap) & 0x02)) {
2255 memory_region_msync(&n->pmrdev->mr, 0, n->pmrdev->size);
2256 }
2257 memcpy(&val, ptr + addr, size);
2258 } else {
2259 NVME_GUEST_ERR(pci_nvme_ub_mmiord_invalid_ofs,
2260 "MMIO read beyond last register,"
2261 " offset=0x%"PRIx64", returning 0", addr);
2262 }
2263
2264 return val;
2265 }
2266
2267 static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
2268 {
2269 uint32_t qid;
2270
2271 if (unlikely(addr & ((1 << 2) - 1))) {
2272 NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned,
2273 "doorbell write not 32-bit aligned,"
2274 " offset=0x%"PRIx64", ignoring", addr);
2275 return;
2276 }
2277
2278 if (((addr - 0x1000) >> 2) & 1) {
2279 /* Completion queue doorbell write */
2280
2281 uint16_t new_head = val & 0xffff;
2282 int start_sqs;
2283 NvmeCQueue *cq;
2284
2285 qid = (addr - (0x1000 + (1 << 2))) >> 3;
2286 if (unlikely(nvme_check_cqid(n, qid))) {
2287 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cq,
2288 "completion queue doorbell write"
2289 " for nonexistent queue,"
2290 " sqid=%"PRIu32", ignoring", qid);
2291
2292 /*
2293 * NVM Express v1.3d, Section 4.1 state: "If host software writes
2294 * an invalid value to the Submission Queue Tail Doorbell or
2295 * Completion Queue Head Doorbell regiter and an Asynchronous Event
2296 * Request command is outstanding, then an asynchronous event is
2297 * posted to the Admin Completion Queue with a status code of
2298 * Invalid Doorbell Write Value."
2299 *
2300 * Also note that the spec includes the "Invalid Doorbell Register"
2301 * status code, but nowhere does it specify when to use it.
2302 * However, it seems reasonable to use it here in a similar
2303 * fashion.
2304 */
2305 if (n->outstanding_aers) {
2306 nvme_enqueue_event(n, NVME_AER_TYPE_ERROR,
2307 NVME_AER_INFO_ERR_INVALID_DB_REGISTER,
2308 NVME_LOG_ERROR_INFO);
2309 }
2310
2311 return;
2312 }
2313
2314 cq = n->cq[qid];
2315 if (unlikely(new_head >= cq->size)) {
2316 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cqhead,
2317 "completion queue doorbell write value"
2318 " beyond queue size, sqid=%"PRIu32","
2319 " new_head=%"PRIu16", ignoring",
2320 qid, new_head);
2321
2322 if (n->outstanding_aers) {
2323 nvme_enqueue_event(n, NVME_AER_TYPE_ERROR,
2324 NVME_AER_INFO_ERR_INVALID_DB_VALUE,
2325 NVME_LOG_ERROR_INFO);
2326 }
2327
2328 return;
2329 }
2330
2331 trace_pci_nvme_mmio_doorbell_cq(cq->cqid, new_head);
2332
2333 start_sqs = nvme_cq_full(cq) ? 1 : 0;
2334 cq->head = new_head;
2335 if (start_sqs) {
2336 NvmeSQueue *sq;
2337 QTAILQ_FOREACH(sq, &cq->sq_list, entry) {
2338 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
2339 }
2340 timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
2341 }
2342
2343 if (cq->tail == cq->head) {
2344 nvme_irq_deassert(n, cq);
2345 }
2346 } else {
2347 /* Submission queue doorbell write */
2348
2349 uint16_t new_tail = val & 0xffff;
2350 NvmeSQueue *sq;
2351
2352 qid = (addr - 0x1000) >> 3;
2353 if (unlikely(nvme_check_sqid(n, qid))) {
2354 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sq,
2355 "submission queue doorbell write"
2356 " for nonexistent queue,"
2357 " sqid=%"PRIu32", ignoring", qid);
2358
2359 if (n->outstanding_aers) {
2360 nvme_enqueue_event(n, NVME_AER_TYPE_ERROR,
2361 NVME_AER_INFO_ERR_INVALID_DB_REGISTER,
2362 NVME_LOG_ERROR_INFO);
2363 }
2364
2365 return;
2366 }
2367
2368 sq = n->sq[qid];
2369 if (unlikely(new_tail >= sq->size)) {
2370 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sqtail,
2371 "submission queue doorbell write value"
2372 " beyond queue size, sqid=%"PRIu32","
2373 " new_tail=%"PRIu16", ignoring",
2374 qid, new_tail);
2375
2376 if (n->outstanding_aers) {
2377 nvme_enqueue_event(n, NVME_AER_TYPE_ERROR,
2378 NVME_AER_INFO_ERR_INVALID_DB_VALUE,
2379 NVME_LOG_ERROR_INFO);
2380 }
2381
2382 return;
2383 }
2384
2385 trace_pci_nvme_mmio_doorbell_sq(sq->sqid, new_tail);
2386
2387 sq->tail = new_tail;
2388 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
2389 }
2390 }
2391
2392 static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data,
2393 unsigned size)
2394 {
2395 NvmeCtrl *n = (NvmeCtrl *)opaque;
2396
2397 trace_pci_nvme_mmio_write(addr, data);
2398
2399 if (addr < sizeof(n->bar)) {
2400 nvme_write_bar(n, addr, data, size);
2401 } else {
2402 nvme_process_db(n, addr, data);
2403 }
2404 }
2405
2406 static const MemoryRegionOps nvme_mmio_ops = {
2407 .read = nvme_mmio_read,
2408 .write = nvme_mmio_write,
2409 .endianness = DEVICE_LITTLE_ENDIAN,
2410 .impl = {
2411 .min_access_size = 2,
2412 .max_access_size = 8,
2413 },
2414 };
2415
2416 static void nvme_cmb_write(void *opaque, hwaddr addr, uint64_t data,
2417 unsigned size)
2418 {
2419 NvmeCtrl *n = (NvmeCtrl *)opaque;
2420 stn_le_p(&n->cmbuf[addr], size, data);
2421 }
2422
2423 static uint64_t nvme_cmb_read(void *opaque, hwaddr addr, unsigned size)
2424 {
2425 NvmeCtrl *n = (NvmeCtrl *)opaque;
2426 return ldn_le_p(&n->cmbuf[addr], size);
2427 }
2428
2429 static const MemoryRegionOps nvme_cmb_ops = {
2430 .read = nvme_cmb_read,
2431 .write = nvme_cmb_write,
2432 .endianness = DEVICE_LITTLE_ENDIAN,
2433 .impl = {
2434 .min_access_size = 1,
2435 .max_access_size = 8,
2436 },
2437 };
2438
2439 static void nvme_check_constraints(NvmeCtrl *n, Error **errp)
2440 {
2441 NvmeParams *params = &n->params;
2442
2443 if (params->num_queues) {
2444 warn_report("num_queues is deprecated; please use max_ioqpairs "
2445 "instead");
2446
2447 params->max_ioqpairs = params->num_queues - 1;
2448 }
2449
2450 if (params->max_ioqpairs < 1 ||
2451 params->max_ioqpairs > NVME_MAX_IOQPAIRS) {
2452 error_setg(errp, "max_ioqpairs must be between 1 and %d",
2453 NVME_MAX_IOQPAIRS);
2454 return;
2455 }
2456
2457 if (params->msix_qsize < 1 ||
2458 params->msix_qsize > PCI_MSIX_FLAGS_QSIZE + 1) {
2459 error_setg(errp, "msix_qsize must be between 1 and %d",
2460 PCI_MSIX_FLAGS_QSIZE + 1);
2461 return;
2462 }
2463
2464 if (!n->conf.blk) {
2465 error_setg(errp, "drive property not set");
2466 return;
2467 }
2468
2469 if (!params->serial) {
2470 error_setg(errp, "serial property not set");
2471 return;
2472 }
2473
2474 if (!n->params.cmb_size_mb && n->pmrdev) {
2475 if (host_memory_backend_is_mapped(n->pmrdev)) {
2476 error_setg(errp, "can't use already busy memdev: %s",
2477 object_get_canonical_path_component(OBJECT(n->pmrdev)));
2478 return;
2479 }
2480
2481 if (!is_power_of_2(n->pmrdev->size)) {
2482 error_setg(errp, "pmr backend size needs to be power of 2 in size");
2483 return;
2484 }
2485
2486 host_memory_backend_set_mapped(n->pmrdev, true);
2487 }
2488 }
2489
2490 static void nvme_init_state(NvmeCtrl *n)
2491 {
2492 n->num_namespaces = 1;
2493 /* add one to max_ioqpairs to account for the admin queue pair */
2494 n->reg_size = pow2ceil(sizeof(NvmeBar) +
2495 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE);
2496 n->namespaces = g_new0(NvmeNamespace, n->num_namespaces);
2497 n->sq = g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1);
2498 n->cq = g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1);
2499 n->temperature = NVME_TEMPERATURE;
2500 n->features.temp_thresh_hi = NVME_TEMPERATURE_WARNING;
2501 n->starttime_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
2502 n->aer_reqs = g_new0(NvmeRequest *, n->params.aerl + 1);
2503 }
2504
2505 static void nvme_init_blk(NvmeCtrl *n, Error **errp)
2506 {
2507 if (!blkconf_blocksizes(&n->conf, errp)) {
2508 return;
2509 }
2510 blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.blk),
2511 false, errp);
2512 }
2513
2514 static void nvme_init_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
2515 {
2516 int64_t bs_size;
2517 NvmeIdNs *id_ns = &ns->id_ns;
2518
2519 bs_size = blk_getlength(n->conf.blk);
2520 if (bs_size < 0) {
2521 error_setg_errno(errp, -bs_size, "could not get backing file size");
2522 return;
2523 }
2524
2525 n->ns_size = bs_size;
2526
2527 id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
2528 id_ns->nsze = cpu_to_le64(nvme_ns_nlbas(n, ns));
2529
2530 /* no thin provisioning */
2531 id_ns->ncap = id_ns->nsze;
2532 id_ns->nuse = id_ns->ncap;
2533 }
2534
2535 static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
2536 {
2537 NVME_CMBLOC_SET_BIR(n->bar.cmbloc, NVME_CMB_BIR);
2538 NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0);
2539
2540 NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1);
2541 NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0);
2542 NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 1);
2543 NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1);
2544 NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1);
2545 NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */
2546 NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb);
2547
2548 n->cmbuf = g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
2549 memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n,
2550 "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
2551 pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc),
2552 PCI_BASE_ADDRESS_SPACE_MEMORY |
2553 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2554 PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
2555 }
2556
2557 static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
2558 {
2559 /* Controller Capabilities register */
2560 NVME_CAP_SET_PMRS(n->bar.cap, 1);
2561
2562 /* PMR Capabities register */
2563 n->bar.pmrcap = 0;
2564 NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
2565 NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
2566 NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
2567 NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
2568 /* Turn on bit 1 support */
2569 NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
2570 NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
2571 NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
2572
2573 /* PMR Control register */
2574 n->bar.pmrctl = 0;
2575 NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
2576
2577 /* PMR Status register */
2578 n->bar.pmrsts = 0;
2579 NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
2580 NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
2581 NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
2582 NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
2583
2584 /* PMR Elasticity Buffer Size register */
2585 n->bar.pmrebs = 0;
2586 NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
2587 NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
2588 NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
2589
2590 /* PMR Sustained Write Throughput register */
2591 n->bar.pmrswtp = 0;
2592 NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
2593 NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
2594
2595 /* PMR Memory Space Control register */
2596 n->bar.pmrmsc = 0;
2597 NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
2598 NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
2599
2600 pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
2601 PCI_BASE_ADDRESS_SPACE_MEMORY |
2602 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2603 PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
2604 }
2605
2606 static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
2607 {
2608 uint8_t *pci_conf = pci_dev->config;
2609
2610 pci_conf[PCI_INTERRUPT_PIN] = 1;
2611 pci_config_set_prog_interface(pci_conf, 0x2);
2612 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS);
2613 pcie_endpoint_cap_init(pci_dev, 0x80);
2614
2615 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme",
2616 n->reg_size);
2617 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
2618 PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem);
2619 if (msix_init_exclusive_bar(pci_dev, n->params.msix_qsize, 4, errp)) {
2620 return;
2621 }
2622
2623 if (n->params.cmb_size_mb) {
2624 nvme_init_cmb(n, pci_dev);
2625 } else if (n->pmrdev) {
2626 nvme_init_pmr(n, pci_dev);
2627 }
2628 }
2629
2630 static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
2631 {
2632 NvmeIdCtrl *id = &n->id_ctrl;
2633 uint8_t *pci_conf = pci_dev->config;
2634 char *subnqn;
2635
2636 id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
2637 id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
2638 strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
2639 strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' ');
2640 strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' ');
2641 id->rab = 6;
2642 id->ieee[0] = 0x00;
2643 id->ieee[1] = 0x02;
2644 id->ieee[2] = 0xb3;
2645 id->mdts = n->params.mdts;
2646 id->ver = cpu_to_le32(NVME_SPEC_VER);
2647 id->oacs = cpu_to_le16(0);
2648
2649 /*
2650 * Because the controller always completes the Abort command immediately,
2651 * there can never be more than one concurrently executing Abort command,
2652 * so this value is never used for anything. Note that there can easily be
2653 * many Abort commands in the queues, but they are not considered
2654 * "executing" until processed by nvme_abort.
2655 *
2656 * The specification recommends a value of 3 for Abort Command Limit (four
2657 * concurrently outstanding Abort commands), so lets use that though it is
2658 * inconsequential.
2659 */
2660 id->acl = 3;
2661 id->aerl = n->params.aerl;
2662 id->frmw = (NVME_NUM_FW_SLOTS << 1) | NVME_FRMW_SLOT1_RO;
2663 id->lpa = NVME_LPA_EXTENDED;
2664
2665 /* recommended default value (~70 C) */
2666 id->wctemp = cpu_to_le16(NVME_TEMPERATURE_WARNING);
2667 id->cctemp = cpu_to_le16(NVME_TEMPERATURE_CRITICAL);
2668
2669 id->sqes = (0x6 << 4) | 0x6;
2670 id->cqes = (0x4 << 4) | 0x4;
2671 id->nn = cpu_to_le32(n->num_namespaces);
2672 id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP |
2673 NVME_ONCS_FEATURES);
2674 id->sgls = cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN |
2675 NVME_CTRL_SGLS_BITBUCKET);
2676
2677 subnqn = g_strdup_printf("nqn.2019-08.org.qemu:%s", n->params.serial);
2678 strpadcpy((char *)id->subnqn, sizeof(id->subnqn), subnqn, '\0');
2679 g_free(subnqn);
2680
2681 id->psd[0].mp = cpu_to_le16(0x9c4);
2682 id->psd[0].enlat = cpu_to_le32(0x10);
2683 id->psd[0].exlat = cpu_to_le32(0x4);
2684 if (blk_enable_write_cache(n->conf.blk)) {
2685 id->vwc = 1;
2686 }
2687
2688 n->bar.cap = 0;
2689 NVME_CAP_SET_MQES(n->bar.cap, 0x7ff);
2690 NVME_CAP_SET_CQR(n->bar.cap, 1);
2691 NVME_CAP_SET_TO(n->bar.cap, 0xf);
2692 NVME_CAP_SET_CSS(n->bar.cap, 1);
2693 NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
2694
2695 n->bar.vs = NVME_SPEC_VER;
2696 n->bar.intmc = n->bar.intms = 0;
2697 }
2698
2699 static void nvme_realize(PCIDevice *pci_dev, Error **errp)
2700 {
2701 NvmeCtrl *n = NVME(pci_dev);
2702 Error *local_err = NULL;
2703
2704 int i;
2705
2706 nvme_check_constraints(n, &local_err);
2707 if (local_err) {
2708 error_propagate(errp, local_err);
2709 return;
2710 }
2711
2712 nvme_init_state(n);
2713 nvme_init_blk(n, &local_err);
2714 if (local_err) {
2715 error_propagate(errp, local_err);
2716 return;
2717 }
2718
2719 nvme_init_pci(n, pci_dev, &local_err);
2720 if (local_err) {
2721 error_propagate(errp, local_err);
2722 return;
2723 }
2724
2725 nvme_init_ctrl(n, pci_dev);
2726
2727 for (i = 0; i < n->num_namespaces; i++) {
2728 nvme_init_namespace(n, &n->namespaces[i], &local_err);
2729 if (local_err) {
2730 error_propagate(errp, local_err);
2731 return;
2732 }
2733 }
2734 }
2735
2736 static void nvme_exit(PCIDevice *pci_dev)
2737 {
2738 NvmeCtrl *n = NVME(pci_dev);
2739
2740 nvme_clear_ctrl(n);
2741 g_free(n->namespaces);
2742 g_free(n->cq);
2743 g_free(n->sq);
2744 g_free(n->aer_reqs);
2745
2746 if (n->params.cmb_size_mb) {
2747 g_free(n->cmbuf);
2748 }
2749
2750 if (n->pmrdev) {
2751 host_memory_backend_set_mapped(n->pmrdev, false);
2752 }
2753 msix_uninit_exclusive_bar(pci_dev);
2754 }
2755
2756 static Property nvme_props[] = {
2757 DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
2758 DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmrdev, TYPE_MEMORY_BACKEND,
2759 HostMemoryBackend *),
2760 DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial),
2761 DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0),
2762 DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 0),
2763 DEFINE_PROP_UINT32("max_ioqpairs", NvmeCtrl, params.max_ioqpairs, 64),
2764 DEFINE_PROP_UINT16("msix_qsize", NvmeCtrl, params.msix_qsize, 65),
2765 DEFINE_PROP_UINT8("aerl", NvmeCtrl, params.aerl, 3),
2766 DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64),
2767 DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7),
2768 DEFINE_PROP_END_OF_LIST(),
2769 };
2770
2771 static const VMStateDescription nvme_vmstate = {
2772 .name = "nvme",
2773 .unmigratable = 1,
2774 };
2775
2776 static void nvme_class_init(ObjectClass *oc, void *data)
2777 {
2778 DeviceClass *dc = DEVICE_CLASS(oc);
2779 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2780
2781 pc->realize = nvme_realize;
2782 pc->exit = nvme_exit;
2783 pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
2784 pc->vendor_id = PCI_VENDOR_ID_INTEL;
2785 pc->device_id = 0x5845;
2786 pc->revision = 2;
2787
2788 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2789 dc->desc = "Non-Volatile Memory Express";
2790 device_class_set_props(dc, nvme_props);
2791 dc->vmsd = &nvme_vmstate;
2792 }
2793
2794 static void nvme_instance_init(Object *obj)
2795 {
2796 NvmeCtrl *s = NVME(obj);
2797
2798 device_add_bootindex_property(obj, &s->conf.bootindex,
2799 "bootindex", "/namespace@1,0",
2800 DEVICE(obj));
2801 }
2802
2803 static const TypeInfo nvme_info = {
2804 .name = TYPE_NVME,
2805 .parent = TYPE_PCI_DEVICE,
2806 .instance_size = sizeof(NvmeCtrl),
2807 .class_init = nvme_class_init,
2808 .instance_init = nvme_instance_init,
2809 .interfaces = (InterfaceInfo[]) {
2810 { INTERFACE_PCIE_DEVICE },
2811 { }
2812 },
2813 };
2814
2815 static void nvme_register_types(void)
2816 {
2817 type_register_static(&nvme_info);
2818 }
2819
2820 type_init(nvme_register_types)
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