2 * CFI parallel flash with Intel command set emulation
4 * Copyright (c) 2006 Thorsten Zitterell
5 * Copyright (c) 2005 Jocelyn Mayer
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
30 * It does not support timings
31 * It does not support flash interleaving
32 * It does not implement software data protection as found in many real chips
33 * It does not implement erase suspend/resume commands
34 * It does not implement multiple sectors erase
36 * It does not implement much more ...
39 #include "qemu/osdep.h"
40 #include "hw/block/block.h"
41 #include "hw/block/flash.h"
42 #include "hw/qdev-properties.h"
43 #include "hw/qdev-properties-system.h"
44 #include "sysemu/block-backend.h"
45 #include "qapi/error.h"
46 #include "qemu/error-report.h"
47 #include "qemu/bitops.h"
48 #include "qemu/host-utils.h"
50 #include "qemu/module.h"
51 #include "qemu/option.h"
52 #include "hw/sysbus.h"
53 #include "migration/vmstate.h"
54 #include "sysemu/blockdev.h"
55 #include "sysemu/runstate.h"
59 #define PFLASH_SECURE 1
63 SysBusDevice parent_obj
;
70 uint8_t device_width
; /* If 0, device width not specified. */
71 uint8_t max_device_width
; /* max device width in bytes */
73 uint8_t wcycle
; /* if 0, the flash is read normally */
81 uint8_t cfi_table
[0x52];
83 unsigned int writeblock_size
;
87 VMChangeStateEntry
*vmstate
;
88 bool old_multiple_chip_handling
;
91 static int pflash_post_load(void *opaque
, int version_id
);
93 static const VMStateDescription vmstate_pflash
= {
94 .name
= "pflash_cfi01",
96 .minimum_version_id
= 1,
97 .post_load
= pflash_post_load
,
98 .fields
= (const VMStateField
[]) {
99 VMSTATE_UINT8(wcycle
, PFlashCFI01
),
100 VMSTATE_UINT8(cmd
, PFlashCFI01
),
101 VMSTATE_UINT8(status
, PFlashCFI01
),
102 VMSTATE_UINT64(counter
, PFlashCFI01
),
103 VMSTATE_END_OF_LIST()
108 * Perform a CFI query based on the bank width of the flash.
109 * If this code is called we know we have a device_width set for
112 static uint32_t pflash_cfi_query(PFlashCFI01
*pfl
, hwaddr offset
)
119 * Adjust incoming offset to match expected device-width
120 * addressing. CFI query addresses are always specified in terms of
121 * the maximum supported width of the device. This means that x8
122 * devices and x8/x16 devices in x8 mode behave differently. For
123 * devices that are not used at their max width, we will be
124 * provided with addresses that use higher address bits than
125 * expected (based on the max width), so we will shift them lower
126 * so that they will match the addresses used when
127 * device_width==max_device_width.
129 boff
= offset
>> (ctz32(pfl
->bank_width
) +
130 ctz32(pfl
->max_device_width
) - ctz32(pfl
->device_width
));
132 if (boff
>= sizeof(pfl
->cfi_table
)) {
136 * Now we will construct the CFI response generated by a single
137 * device, then replicate that for all devices that make up the
138 * bus. For wide parts used in x8 mode, CFI query responses
139 * are different than native byte-wide parts.
141 resp
= pfl
->cfi_table
[boff
];
142 if (pfl
->device_width
!= pfl
->max_device_width
) {
143 /* The only case currently supported is x8 mode for a
146 if (pfl
->device_width
!= 1 || pfl
->bank_width
> 4) {
147 trace_pflash_unsupported_device_configuration(pfl
->name
,
148 pfl
->device_width
, pfl
->max_device_width
);
151 /* CFI query data is repeated, rather than zero padded for
152 * wide devices used in x8 mode.
154 for (i
= 1; i
< pfl
->max_device_width
; i
++) {
155 resp
= deposit32(resp
, 8 * i
, 8, pfl
->cfi_table
[boff
]);
158 /* Replicate responses for each device in bank. */
159 if (pfl
->device_width
< pfl
->bank_width
) {
160 for (i
= pfl
->device_width
;
161 i
< pfl
->bank_width
; i
+= pfl
->device_width
) {
162 resp
= deposit32(resp
, 8 * i
, 8 * pfl
->device_width
, resp
);
171 /* Perform a device id query based on the bank width of the flash. */
172 static uint32_t pflash_devid_query(PFlashCFI01
*pfl
, hwaddr offset
)
179 * Adjust incoming offset to match expected device-width
180 * addressing. Device ID read addresses are always specified in
181 * terms of the maximum supported width of the device. This means
182 * that x8 devices and x8/x16 devices in x8 mode behave
183 * differently. For devices that are not used at their max width,
184 * we will be provided with addresses that use higher address bits
185 * than expected (based on the max width), so we will shift them
186 * lower so that they will match the addresses used when
187 * device_width==max_device_width.
189 boff
= offset
>> (ctz32(pfl
->bank_width
) +
190 ctz32(pfl
->max_device_width
) - ctz32(pfl
->device_width
));
193 * Mask off upper bits which may be used in to query block
194 * or sector lock status at other addresses.
195 * Offsets 2/3 are block lock status, is not emulated.
197 switch (boff
& 0xFF) {
200 trace_pflash_manufacturer_id(pfl
->name
, resp
);
204 trace_pflash_device_id(pfl
->name
, resp
);
207 trace_pflash_device_info(pfl
->name
, offset
);
210 /* Replicate responses for each device in bank. */
211 if (pfl
->device_width
< pfl
->bank_width
) {
212 for (i
= pfl
->device_width
;
213 i
< pfl
->bank_width
; i
+= pfl
->device_width
) {
214 resp
= deposit32(resp
, 8 * i
, 8 * pfl
->device_width
, resp
);
221 static uint32_t pflash_data_read(PFlashCFI01
*pfl
, hwaddr offset
,
229 ret
= ldn_be_p(p
+ offset
, width
);
231 ret
= ldn_le_p(p
+ offset
, width
);
233 trace_pflash_data_read(pfl
->name
, offset
, width
, ret
);
237 static uint32_t pflash_read(PFlashCFI01
*pfl
, hwaddr offset
,
246 /* This should never happen : reset state & treat it as a read */
247 trace_pflash_read_unknown_state(pfl
->name
, pfl
->cmd
);
250 * The command 0x00 is not assigned by the CFI open standard,
251 * but QEMU historically uses it for the READ_ARRAY command (0xff).
254 /* fall through to read code */
255 case 0x00: /* This model reset value for READ_ARRAY (not CFI compliant) */
256 /* Flash area read */
257 ret
= pflash_data_read(pfl
, offset
, width
, be
);
259 case 0x10: /* Single byte program */
260 case 0x20: /* Block erase */
261 case 0x28: /* Block erase */
262 case 0x40: /* single byte program */
263 case 0x50: /* Clear status register */
264 case 0x60: /* Block /un)lock */
265 case 0x70: /* Status Register */
266 case 0xe8: /* Write block */
268 * Status register read. Return status from each device in
272 if (pfl
->device_width
&& width
> pfl
->device_width
) {
273 int shift
= pfl
->device_width
* 8;
274 while (shift
+ pfl
->device_width
* 8 <= width
* 8) {
275 ret
|= pfl
->status
<< shift
;
276 shift
+= pfl
->device_width
* 8;
278 } else if (!pfl
->device_width
&& width
> 2) {
280 * Handle 32 bit flash cases where device width is not
281 * set. (Existing behavior before device width added.)
283 ret
|= pfl
->status
<< 16;
285 trace_pflash_read_status(pfl
->name
, ret
);
288 if (!pfl
->device_width
) {
289 /* Preserve old behavior if device width not specified */
290 boff
= offset
& 0xFF;
291 if (pfl
->bank_width
== 2) {
293 } else if (pfl
->bank_width
== 4) {
299 ret
= pfl
->ident0
<< 8 | pfl
->ident1
;
300 trace_pflash_manufacturer_id(pfl
->name
, ret
);
303 ret
= pfl
->ident2
<< 8 | pfl
->ident3
;
304 trace_pflash_device_id(pfl
->name
, ret
);
307 trace_pflash_device_info(pfl
->name
, boff
);
313 * If we have a read larger than the bank_width, combine multiple
314 * manufacturer/device ID queries into a single response.
317 for (i
= 0; i
< width
; i
+= pfl
->bank_width
) {
318 ret
= deposit32(ret
, i
* 8, pfl
->bank_width
* 8,
319 pflash_devid_query(pfl
,
320 offset
+ i
* pfl
->bank_width
));
324 case 0x98: /* Query mode */
325 if (!pfl
->device_width
) {
326 /* Preserve old behavior if device width not specified */
327 boff
= offset
& 0xFF;
328 if (pfl
->bank_width
== 2) {
330 } else if (pfl
->bank_width
== 4) {
334 if (boff
< sizeof(pfl
->cfi_table
)) {
335 ret
= pfl
->cfi_table
[boff
];
341 * If we have a read larger than the bank_width, combine multiple
342 * CFI queries into a single response.
345 for (i
= 0; i
< width
; i
+= pfl
->bank_width
) {
346 ret
= deposit32(ret
, i
* 8, pfl
->bank_width
* 8,
347 pflash_cfi_query(pfl
,
348 offset
+ i
* pfl
->bank_width
));
354 trace_pflash_io_read(pfl
->name
, offset
, width
, ret
, pfl
->cmd
, pfl
->wcycle
);
359 /* update flash content on disk */
360 static void pflash_update(PFlashCFI01
*pfl
, int offset
,
366 offset_end
= offset
+ size
;
367 /* widen to sector boundaries */
368 offset
= QEMU_ALIGN_DOWN(offset
, BDRV_SECTOR_SIZE
);
369 offset_end
= QEMU_ALIGN_UP(offset_end
, BDRV_SECTOR_SIZE
);
370 ret
= blk_pwrite(pfl
->blk
, offset
, offset_end
- offset
,
371 pfl
->storage
+ offset
, 0);
373 /* TODO set error bit in status */
374 error_report("Could not update PFLASH: %s", strerror(-ret
));
379 static inline void pflash_data_write(PFlashCFI01
*pfl
, hwaddr offset
,
380 uint32_t value
, int width
, int be
)
384 trace_pflash_data_write(pfl
->name
, offset
, width
, value
, pfl
->counter
);
385 p
= pfl
->storage
+ offset
;
388 stn_be_p(p
, width
, value
);
390 stn_le_p(p
, width
, value
);
394 static void pflash_write(PFlashCFI01
*pfl
, hwaddr offset
,
395 uint32_t value
, int width
, int be
)
402 trace_pflash_io_write(pfl
->name
, offset
, width
, value
, pfl
->wcycle
);
404 /* Set the device in I/O access mode */
405 memory_region_rom_device_set_romd(&pfl
->mem
, false);
408 switch (pfl
->wcycle
) {
412 case 0x00: /* This model reset value for READ_ARRAY (not CFI) */
413 goto mode_read_array
;
414 case 0x10: /* Single Byte Program */
415 case 0x40: /* Single Byte Program */
416 trace_pflash_write(pfl
->name
, "single byte program (0)");
418 case 0x20: /* Block erase */
420 offset
&= ~(pfl
->sector_len
- 1);
422 trace_pflash_write_block_erase(pfl
->name
, offset
, pfl
->sector_len
);
425 memset(p
+ offset
, 0xff, pfl
->sector_len
);
426 pflash_update(pfl
, offset
, pfl
->sector_len
);
428 pfl
->status
|= 0x20; /* Block erase error */
430 pfl
->status
|= 0x80; /* Ready! */
432 case 0x50: /* Clear status bits */
433 trace_pflash_write(pfl
->name
, "clear status bits");
435 goto mode_read_array
;
436 case 0x60: /* Block (un)lock */
437 trace_pflash_write(pfl
->name
, "block unlock");
439 case 0x70: /* Status Register */
440 trace_pflash_write(pfl
->name
, "read status register");
443 case 0x90: /* Read Device ID */
444 trace_pflash_write(pfl
->name
, "read device information");
447 case 0x98: /* CFI query */
448 trace_pflash_write(pfl
->name
, "CFI query");
450 case 0xe8: /* Write to buffer */
451 trace_pflash_write(pfl
->name
, "write to buffer");
452 /* FIXME should save @offset, @width for case 1+ */
453 qemu_log_mask(LOG_UNIMP
,
454 "%s: Write to buffer emulation is flawed\n",
456 pfl
->status
|= 0x80; /* Ready! */
458 case 0xf0: /* Probe for AMD flash */
459 trace_pflash_write(pfl
->name
, "probe for AMD flash");
460 goto mode_read_array
;
461 case 0xff: /* Read Array */
462 trace_pflash_write(pfl
->name
, "read array mode");
463 goto mode_read_array
;
472 case 0x10: /* Single Byte Program */
473 case 0x40: /* Single Byte Program */
474 trace_pflash_write(pfl
->name
, "single byte program (1)");
476 pflash_data_write(pfl
, offset
, value
, width
, be
);
477 pflash_update(pfl
, offset
, width
);
479 pfl
->status
|= 0x10; /* Programming error */
481 pfl
->status
|= 0x80; /* Ready! */
484 case 0x20: /* Block erase */
486 if (cmd
== 0xd0) { /* confirm */
489 } else if (cmd
== 0xff) { /* Read Array */
490 goto mode_read_array
;
497 * Mask writeblock size based on device width, or bank width if
498 * device width not specified.
500 /* FIXME check @offset, @width */
501 if (pfl
->device_width
) {
502 value
= extract32(value
, 0, pfl
->device_width
* 8);
504 value
= extract32(value
, 0, pfl
->bank_width
* 8);
506 trace_pflash_write_block(pfl
->name
, value
);
507 pfl
->counter
= value
;
514 } else if (cmd
== 0x01) {
517 } else if (cmd
== 0xff) { /* Read Array */
518 goto mode_read_array
;
520 trace_pflash_write(pfl
->name
, "unknown (un)locking command");
521 goto mode_read_array
;
525 if (cmd
== 0xff) { /* Read Array */
526 goto mode_read_array
;
528 trace_pflash_write(pfl
->name
, "leaving query mode");
537 case 0xe8: /* Block write */
538 /* FIXME check @offset, @width */
541 * FIXME writing straight to memory is *wrong*. We
542 * should write to a buffer, and flush it to memory
543 * only on confirm command (see below).
545 pflash_data_write(pfl
, offset
, value
, width
, be
);
547 pfl
->status
|= 0x10; /* Programming error */
553 hwaddr mask
= pfl
->writeblock_size
- 1;
556 trace_pflash_write(pfl
->name
, "block write finished");
559 /* Flush the entire write buffer onto backing storage. */
560 /* FIXME premature! */
561 pflash_update(pfl
, offset
& mask
, pfl
->writeblock_size
);
563 pfl
->status
|= 0x10; /* Programming error */
573 case 3: /* Confirm mode */
575 case 0xe8: /* Block write */
577 /* FIXME this is where we should write out the buffer */
581 qemu_log_mask(LOG_UNIMP
,
582 "%s: Aborting write to buffer not implemented,"
583 " the data is already written to storage!\n"
584 "Flash device reset into READ mode.\n",
586 goto mode_read_array
;
594 /* Should never happen */
595 trace_pflash_write(pfl
->name
, "invalid write state");
596 goto mode_read_array
;
601 qemu_log_mask(LOG_UNIMP
, "%s: Unimplemented flash cmd sequence "
602 "(offset " HWADDR_FMT_plx
", wcycle 0x%x cmd 0x%x value 0x%x)"
603 "\n", __func__
, offset
, pfl
->wcycle
, pfl
->cmd
, value
);
606 trace_pflash_mode_read_array(pfl
->name
);
607 memory_region_rom_device_set_romd(&pfl
->mem
, true);
609 pfl
->cmd
= 0x00; /* This model reset value for READ_ARRAY (not CFI) */
613 static MemTxResult
pflash_mem_read_with_attrs(void *opaque
, hwaddr addr
, uint64_t *value
,
614 unsigned len
, MemTxAttrs attrs
)
616 PFlashCFI01
*pfl
= opaque
;
617 bool be
= !!(pfl
->features
& (1 << PFLASH_BE
));
619 if ((pfl
->features
& (1 << PFLASH_SECURE
)) && !attrs
.secure
) {
620 *value
= pflash_data_read(opaque
, addr
, len
, be
);
622 *value
= pflash_read(opaque
, addr
, len
, be
);
627 static MemTxResult
pflash_mem_write_with_attrs(void *opaque
, hwaddr addr
, uint64_t value
,
628 unsigned len
, MemTxAttrs attrs
)
630 PFlashCFI01
*pfl
= opaque
;
631 bool be
= !!(pfl
->features
& (1 << PFLASH_BE
));
633 if ((pfl
->features
& (1 << PFLASH_SECURE
)) && !attrs
.secure
) {
636 pflash_write(opaque
, addr
, value
, len
, be
);
641 static const MemoryRegionOps pflash_cfi01_ops
= {
642 .read_with_attrs
= pflash_mem_read_with_attrs
,
643 .write_with_attrs
= pflash_mem_write_with_attrs
,
644 .endianness
= DEVICE_NATIVE_ENDIAN
,
647 static void pflash_cfi01_fill_cfi_table(PFlashCFI01
*pfl
)
649 uint64_t blocks_per_device
, sector_len_per_device
, device_len
;
653 * These are only used to expose the parameters of each device
654 * in the cfi_table[].
656 num_devices
= pfl
->device_width
? (pfl
->bank_width
/ pfl
->device_width
) : 1;
657 if (pfl
->old_multiple_chip_handling
) {
658 blocks_per_device
= pfl
->nb_blocs
/ num_devices
;
659 sector_len_per_device
= pfl
->sector_len
;
661 blocks_per_device
= pfl
->nb_blocs
;
662 sector_len_per_device
= pfl
->sector_len
/ num_devices
;
664 device_len
= sector_len_per_device
* blocks_per_device
;
666 /* Hardcoded CFI table */
667 /* Standard "QRY" string */
668 pfl
->cfi_table
[0x10] = 'Q';
669 pfl
->cfi_table
[0x11] = 'R';
670 pfl
->cfi_table
[0x12] = 'Y';
671 /* Command set (Intel) */
672 pfl
->cfi_table
[0x13] = 0x01;
673 pfl
->cfi_table
[0x14] = 0x00;
674 /* Primary extended table address (none) */
675 pfl
->cfi_table
[0x15] = 0x31;
676 pfl
->cfi_table
[0x16] = 0x00;
677 /* Alternate command set (none) */
678 pfl
->cfi_table
[0x17] = 0x00;
679 pfl
->cfi_table
[0x18] = 0x00;
680 /* Alternate extended table (none) */
681 pfl
->cfi_table
[0x19] = 0x00;
682 pfl
->cfi_table
[0x1A] = 0x00;
684 pfl
->cfi_table
[0x1B] = 0x45;
686 pfl
->cfi_table
[0x1C] = 0x55;
687 /* Vpp min (no Vpp pin) */
688 pfl
->cfi_table
[0x1D] = 0x00;
689 /* Vpp max (no Vpp pin) */
690 pfl
->cfi_table
[0x1E] = 0x00;
692 pfl
->cfi_table
[0x1F] = 0x07;
693 /* Timeout for min size buffer write */
694 pfl
->cfi_table
[0x20] = 0x07;
695 /* Typical timeout for block erase */
696 pfl
->cfi_table
[0x21] = 0x0a;
697 /* Typical timeout for full chip erase (4096 ms) */
698 pfl
->cfi_table
[0x22] = 0x00;
700 pfl
->cfi_table
[0x23] = 0x04;
701 /* Max timeout for buffer write */
702 pfl
->cfi_table
[0x24] = 0x04;
703 /* Max timeout for block erase */
704 pfl
->cfi_table
[0x25] = 0x04;
705 /* Max timeout for chip erase */
706 pfl
->cfi_table
[0x26] = 0x00;
708 pfl
->cfi_table
[0x27] = ctz32(device_len
); /* + 1; */
709 /* Flash device interface (8 & 16 bits) */
710 pfl
->cfi_table
[0x28] = 0x02;
711 pfl
->cfi_table
[0x29] = 0x00;
712 /* Max number of bytes in multi-bytes write */
713 if (pfl
->bank_width
== 1) {
714 pfl
->cfi_table
[0x2A] = 0x08;
716 pfl
->cfi_table
[0x2A] = 0x0B;
718 pfl
->writeblock_size
= 1 << pfl
->cfi_table
[0x2A];
719 if (!pfl
->old_multiple_chip_handling
&& num_devices
> 1) {
720 pfl
->writeblock_size
*= num_devices
;
723 pfl
->cfi_table
[0x2B] = 0x00;
724 /* Number of erase block regions (uniform) */
725 pfl
->cfi_table
[0x2C] = 0x01;
726 /* Erase block region 1 */
727 pfl
->cfi_table
[0x2D] = blocks_per_device
- 1;
728 pfl
->cfi_table
[0x2E] = (blocks_per_device
- 1) >> 8;
729 pfl
->cfi_table
[0x2F] = sector_len_per_device
>> 8;
730 pfl
->cfi_table
[0x30] = sector_len_per_device
>> 16;
733 pfl
->cfi_table
[0x31] = 'P';
734 pfl
->cfi_table
[0x32] = 'R';
735 pfl
->cfi_table
[0x33] = 'I';
737 pfl
->cfi_table
[0x34] = '1';
738 pfl
->cfi_table
[0x35] = '0';
740 pfl
->cfi_table
[0x36] = 0x00;
741 pfl
->cfi_table
[0x37] = 0x00;
742 pfl
->cfi_table
[0x38] = 0x00;
743 pfl
->cfi_table
[0x39] = 0x00;
745 pfl
->cfi_table
[0x3a] = 0x00;
747 pfl
->cfi_table
[0x3b] = 0x00;
748 pfl
->cfi_table
[0x3c] = 0x00;
750 pfl
->cfi_table
[0x3f] = 0x01; /* Number of protection fields */
753 static void pflash_cfi01_realize(DeviceState
*dev
, Error
**errp
)
756 PFlashCFI01
*pfl
= PFLASH_CFI01(dev
);
760 if (pfl
->sector_len
== 0) {
761 error_setg(errp
, "attribute \"sector-length\" not specified or zero.");
764 if (pfl
->nb_blocs
== 0) {
765 error_setg(errp
, "attribute \"num-blocks\" not specified or zero.");
768 if (pfl
->name
== NULL
) {
769 error_setg(errp
, "attribute \"name\" not specified.");
773 total_len
= pfl
->sector_len
* pfl
->nb_blocs
;
775 memory_region_init_rom_device(
776 &pfl
->mem
, OBJECT(dev
),
779 pfl
->name
, total_len
, errp
);
784 pfl
->storage
= memory_region_get_ram_ptr(&pfl
->mem
);
785 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &pfl
->mem
);
789 pfl
->ro
= !blk_supports_write_perm(pfl
->blk
);
790 perm
= BLK_PERM_CONSISTENT_READ
| (pfl
->ro
? 0 : BLK_PERM_WRITE
);
791 ret
= blk_set_perm(pfl
->blk
, perm
, BLK_PERM_ALL
, errp
);
800 if (!blk_check_size_and_read_all(pfl
->blk
, pfl
->storage
, total_len
,
802 vmstate_unregister_ram(&pfl
->mem
, DEVICE(pfl
));
808 * Default to devices being used at their maximum device width. This was
809 * assumed before the device_width support was added.
811 if (!pfl
->max_device_width
) {
812 pfl
->max_device_width
= pfl
->device_width
;
817 * The command 0x00 is not assigned by the CFI open standard,
818 * but QEMU historically uses it for the READ_ARRAY command (0xff).
821 pfl
->status
= 0x80; /* WSM ready */
822 pflash_cfi01_fill_cfi_table(pfl
);
825 static void pflash_cfi01_system_reset(DeviceState
*dev
)
827 PFlashCFI01
*pfl
= PFLASH_CFI01(dev
);
829 trace_pflash_reset(pfl
->name
);
831 * The command 0x00 is not assigned by the CFI open standard,
832 * but QEMU historically uses it for the READ_ARRAY command (0xff).
836 memory_region_rom_device_set_romd(&pfl
->mem
, true);
838 * The WSM ready timer occurs at most 150ns after system reset.
839 * This model deliberately ignores this delay.
844 static Property pflash_cfi01_properties
[] = {
845 DEFINE_PROP_DRIVE("drive", PFlashCFI01
, blk
),
846 /* num-blocks is the number of blocks actually visible to the guest,
847 * ie the total size of the device divided by the sector length.
848 * If we're emulating flash devices wired in parallel the actual
849 * number of blocks per individual device will differ.
851 DEFINE_PROP_UINT32("num-blocks", PFlashCFI01
, nb_blocs
, 0),
852 DEFINE_PROP_UINT64("sector-length", PFlashCFI01
, sector_len
, 0),
853 /* width here is the overall width of this QEMU device in bytes.
854 * The QEMU device may be emulating a number of flash devices
855 * wired up in parallel; the width of each individual flash
856 * device should be specified via device-width. If the individual
857 * devices have a maximum width which is greater than the width
858 * they are being used for, this maximum width should be set via
859 * max-device-width (which otherwise defaults to device-width).
860 * So for instance a 32-bit wide QEMU flash device made from four
861 * 16-bit flash devices used in 8-bit wide mode would be configured
862 * with width = 4, device-width = 1, max-device-width = 2.
864 * If device-width is not specified we default to backwards
865 * compatible behaviour which is a bad emulation of two
866 * 16 bit devices making up a 32 bit wide QEMU device. This
867 * is deprecated for new uses of this device.
869 DEFINE_PROP_UINT8("width", PFlashCFI01
, bank_width
, 0),
870 DEFINE_PROP_UINT8("device-width", PFlashCFI01
, device_width
, 0),
871 DEFINE_PROP_UINT8("max-device-width", PFlashCFI01
, max_device_width
, 0),
872 DEFINE_PROP_BIT("big-endian", PFlashCFI01
, features
, PFLASH_BE
, 0),
873 DEFINE_PROP_BIT("secure", PFlashCFI01
, features
, PFLASH_SECURE
, 0),
874 DEFINE_PROP_UINT16("id0", PFlashCFI01
, ident0
, 0),
875 DEFINE_PROP_UINT16("id1", PFlashCFI01
, ident1
, 0),
876 DEFINE_PROP_UINT16("id2", PFlashCFI01
, ident2
, 0),
877 DEFINE_PROP_UINT16("id3", PFlashCFI01
, ident3
, 0),
878 DEFINE_PROP_STRING("name", PFlashCFI01
, name
),
879 DEFINE_PROP_BOOL("old-multiple-chip-handling", PFlashCFI01
,
880 old_multiple_chip_handling
, false),
881 DEFINE_PROP_END_OF_LIST(),
884 static void pflash_cfi01_class_init(ObjectClass
*klass
, void *data
)
886 DeviceClass
*dc
= DEVICE_CLASS(klass
);
888 dc
->reset
= pflash_cfi01_system_reset
;
889 dc
->realize
= pflash_cfi01_realize
;
890 device_class_set_props(dc
, pflash_cfi01_properties
);
891 dc
->vmsd
= &vmstate_pflash
;
892 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
896 static const TypeInfo pflash_cfi01_info
= {
897 .name
= TYPE_PFLASH_CFI01
,
898 .parent
= TYPE_SYS_BUS_DEVICE
,
899 .instance_size
= sizeof(PFlashCFI01
),
900 .class_init
= pflash_cfi01_class_init
,
903 static void pflash_cfi01_register_types(void)
905 type_register_static(&pflash_cfi01_info
);
908 type_init(pflash_cfi01_register_types
)
910 PFlashCFI01
*pflash_cfi01_register(hwaddr base
,
916 uint16_t id0
, uint16_t id1
,
917 uint16_t id2
, uint16_t id3
,
920 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
923 qdev_prop_set_drive(dev
, "drive", blk
);
925 assert(QEMU_IS_ALIGNED(size
, sector_len
));
926 qdev_prop_set_uint32(dev
, "num-blocks", size
/ sector_len
);
927 qdev_prop_set_uint64(dev
, "sector-length", sector_len
);
928 qdev_prop_set_uint8(dev
, "width", bank_width
);
929 qdev_prop_set_bit(dev
, "big-endian", !!be
);
930 qdev_prop_set_uint16(dev
, "id0", id0
);
931 qdev_prop_set_uint16(dev
, "id1", id1
);
932 qdev_prop_set_uint16(dev
, "id2", id2
);
933 qdev_prop_set_uint16(dev
, "id3", id3
);
934 qdev_prop_set_string(dev
, "name", name
);
935 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
937 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
938 return PFLASH_CFI01(dev
);
941 BlockBackend
*pflash_cfi01_get_blk(PFlashCFI01
*fl
)
946 MemoryRegion
*pflash_cfi01_get_memory(PFlashCFI01
*fl
)
952 * Handle -drive if=pflash for machines that use properties.
953 * If @dinfo is null, do nothing.
954 * Else if @fl's property "drive" is already set, fatal error.
955 * Else set it to the BlockBackend with @dinfo.
957 void pflash_cfi01_legacy_drive(PFlashCFI01
*fl
, DriveInfo
*dinfo
)
966 qemu_opts_loc_restore(dinfo
->opts
);
968 error_report("clashes with -machine");
971 qdev_prop_set_drive_err(DEVICE(fl
), "drive", blk_by_legacy_dinfo(dinfo
),
976 static void postload_update_cb(void *opaque
, bool running
, RunState state
)
978 PFlashCFI01
*pfl
= opaque
;
980 /* This is called after bdrv_activate_all. */
981 qemu_del_vm_change_state_handler(pfl
->vmstate
);
984 trace_pflash_postload_cb(pfl
->name
);
985 pflash_update(pfl
, 0, pfl
->sector_len
* pfl
->nb_blocs
);
988 static int pflash_post_load(void *opaque
, int version_id
)
990 PFlashCFI01
*pfl
= opaque
;
993 pfl
->vmstate
= qemu_add_vm_change_state_handler(postload_update_cb
,