2 * CFI parallel flash with Intel command set emulation
4 * Copyright (c) 2006 Thorsten Zitterell
5 * Copyright (c) 2005 Jocelyn Mayer
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
30 * It does not support timings
31 * It does not support flash interleaving
32 * It does not implement software data protection as found in many real chips
33 * It does not implement erase suspend/resume commands
34 * It does not implement multiple sectors erase
36 * It does not implement much more ...
39 #include "qemu/osdep.h"
41 #include "hw/block/flash.h"
42 #include "sysemu/block-backend.h"
43 #include "qapi/error.h"
44 #include "qemu/timer.h"
45 #include "qemu/bitops.h"
46 #include "qemu/host-utils.h"
48 #include "hw/sysbus.h"
49 #include "sysemu/sysemu.h"
52 /* #define PFLASH_DEBUG */
54 #define DPRINTF(fmt, ...) \
56 fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \
59 #define DPRINTF(fmt, ...) do { } while (0)
62 #define PFLASH_CFI01(obj) \
63 OBJECT_CHECK(PFlashCFI01, (obj), TYPE_PFLASH_CFI01)
66 #define PFLASH_SECURE 1
70 SysBusDevice parent_obj
;
77 uint8_t device_width
; /* If 0, device width not specified. */
78 uint8_t max_device_width
; /* max device width in bytes */
80 uint8_t wcycle
; /* if 0, the flash is read normally */
88 uint8_t cfi_table
[0x52];
90 unsigned int writeblock_size
;
95 VMChangeStateEntry
*vmstate
;
96 bool old_multiple_chip_handling
;
99 static int pflash_post_load(void *opaque
, int version_id
);
101 static const VMStateDescription vmstate_pflash
= {
102 .name
= "pflash_cfi01",
104 .minimum_version_id
= 1,
105 .post_load
= pflash_post_load
,
106 .fields
= (VMStateField
[]) {
107 VMSTATE_UINT8(wcycle
, PFlashCFI01
),
108 VMSTATE_UINT8(cmd
, PFlashCFI01
),
109 VMSTATE_UINT8(status
, PFlashCFI01
),
110 VMSTATE_UINT64(counter
, PFlashCFI01
),
111 VMSTATE_END_OF_LIST()
115 static void pflash_timer (void *opaque
)
117 PFlashCFI01
*pfl
= opaque
;
119 trace_pflash_timer_expired(pfl
->cmd
);
122 memory_region_rom_device_set_romd(&pfl
->mem
, true);
127 /* Perform a CFI query based on the bank width of the flash.
128 * If this code is called we know we have a device_width set for
131 static uint32_t pflash_cfi_query(PFlashCFI01
*pfl
, hwaddr offset
)
137 /* Adjust incoming offset to match expected device-width
138 * addressing. CFI query addresses are always specified in terms of
139 * the maximum supported width of the device. This means that x8
140 * devices and x8/x16 devices in x8 mode behave differently. For
141 * devices that are not used at their max width, we will be
142 * provided with addresses that use higher address bits than
143 * expected (based on the max width), so we will shift them lower
144 * so that they will match the addresses used when
145 * device_width==max_device_width.
147 boff
= offset
>> (ctz32(pfl
->bank_width
) +
148 ctz32(pfl
->max_device_width
) - ctz32(pfl
->device_width
));
150 if (boff
>= sizeof(pfl
->cfi_table
)) {
153 /* Now we will construct the CFI response generated by a single
154 * device, then replicate that for all devices that make up the
155 * bus. For wide parts used in x8 mode, CFI query responses
156 * are different than native byte-wide parts.
158 resp
= pfl
->cfi_table
[boff
];
159 if (pfl
->device_width
!= pfl
->max_device_width
) {
160 /* The only case currently supported is x8 mode for a
163 if (pfl
->device_width
!= 1 || pfl
->bank_width
> 4) {
164 DPRINTF("%s: Unsupported device configuration: "
165 "device_width=%d, max_device_width=%d\n",
166 __func__
, pfl
->device_width
,
167 pfl
->max_device_width
);
170 /* CFI query data is repeated, rather than zero padded for
171 * wide devices used in x8 mode.
173 for (i
= 1; i
< pfl
->max_device_width
; i
++) {
174 resp
= deposit32(resp
, 8 * i
, 8, pfl
->cfi_table
[boff
]);
177 /* Replicate responses for each device in bank. */
178 if (pfl
->device_width
< pfl
->bank_width
) {
179 for (i
= pfl
->device_width
;
180 i
< pfl
->bank_width
; i
+= pfl
->device_width
) {
181 resp
= deposit32(resp
, 8 * i
, 8 * pfl
->device_width
, resp
);
190 /* Perform a device id query based on the bank width of the flash. */
191 static uint32_t pflash_devid_query(PFlashCFI01
*pfl
, hwaddr offset
)
197 /* Adjust incoming offset to match expected device-width
198 * addressing. Device ID read addresses are always specified in
199 * terms of the maximum supported width of the device. This means
200 * that x8 devices and x8/x16 devices in x8 mode behave
201 * differently. For devices that are not used at their max width,
202 * we will be provided with addresses that use higher address bits
203 * than expected (based on the max width), so we will shift them
204 * lower so that they will match the addresses used when
205 * device_width==max_device_width.
207 boff
= offset
>> (ctz32(pfl
->bank_width
) +
208 ctz32(pfl
->max_device_width
) - ctz32(pfl
->device_width
));
210 /* Mask off upper bits which may be used in to query block
211 * or sector lock status at other addresses.
212 * Offsets 2/3 are block lock status, is not emulated.
214 switch (boff
& 0xFF) {
217 trace_pflash_manufacturer_id(resp
);
221 trace_pflash_device_id(resp
);
224 trace_pflash_device_info(offset
);
228 /* Replicate responses for each device in bank. */
229 if (pfl
->device_width
< pfl
->bank_width
) {
230 for (i
= pfl
->device_width
;
231 i
< pfl
->bank_width
; i
+= pfl
->device_width
) {
232 resp
= deposit32(resp
, 8 * i
, 8 * pfl
->device_width
, resp
);
239 static uint32_t pflash_data_read(PFlashCFI01
*pfl
, hwaddr offset
,
249 trace_pflash_data_read8(offset
, ret
);
253 ret
= p
[offset
] << 8;
254 ret
|= p
[offset
+ 1];
257 ret
|= p
[offset
+ 1] << 8;
259 trace_pflash_data_read16(offset
, ret
);
263 ret
= p
[offset
] << 24;
264 ret
|= p
[offset
+ 1] << 16;
265 ret
|= p
[offset
+ 2] << 8;
266 ret
|= p
[offset
+ 3];
269 ret
|= p
[offset
+ 1] << 8;
270 ret
|= p
[offset
+ 2] << 16;
271 ret
|= p
[offset
+ 3] << 24;
273 trace_pflash_data_read32(offset
, ret
);
276 DPRINTF("BUG in %s\n", __func__
);
282 static uint32_t pflash_read(PFlashCFI01
*pfl
, hwaddr offset
,
289 trace_pflash_read(offset
, pfl
->cmd
, width
, pfl
->wcycle
);
292 /* This should never happen : reset state & treat it as a read */
293 DPRINTF("%s: unknown command state: %x\n", __func__
, pfl
->cmd
);
296 /* fall through to read code */
298 /* Flash area read */
299 ret
= pflash_data_read(pfl
, offset
, width
, be
);
301 case 0x10: /* Single byte program */
302 case 0x20: /* Block erase */
303 case 0x28: /* Block erase */
304 case 0x40: /* single byte program */
305 case 0x50: /* Clear status register */
306 case 0x60: /* Block /un)lock */
307 case 0x70: /* Status Register */
308 case 0xe8: /* Write block */
309 /* Status register read. Return status from each device in
313 if (pfl
->device_width
&& width
> pfl
->device_width
) {
314 int shift
= pfl
->device_width
* 8;
315 while (shift
+ pfl
->device_width
* 8 <= width
* 8) {
316 ret
|= pfl
->status
<< shift
;
317 shift
+= pfl
->device_width
* 8;
319 } else if (!pfl
->device_width
&& width
> 2) {
320 /* Handle 32 bit flash cases where device width is not
321 * set. (Existing behavior before device width added.)
323 ret
|= pfl
->status
<< 16;
325 DPRINTF("%s: status %x\n", __func__
, ret
);
328 if (!pfl
->device_width
) {
329 /* Preserve old behavior if device width not specified */
330 boff
= offset
& 0xFF;
331 if (pfl
->bank_width
== 2) {
333 } else if (pfl
->bank_width
== 4) {
339 ret
= pfl
->ident0
<< 8 | pfl
->ident1
;
340 trace_pflash_manufacturer_id(ret
);
343 ret
= pfl
->ident2
<< 8 | pfl
->ident3
;
344 trace_pflash_device_id(ret
);
347 trace_pflash_device_info(boff
);
352 /* If we have a read larger than the bank_width, combine multiple
353 * manufacturer/device ID queries into a single response.
356 for (i
= 0; i
< width
; i
+= pfl
->bank_width
) {
357 ret
= deposit32(ret
, i
* 8, pfl
->bank_width
* 8,
358 pflash_devid_query(pfl
,
359 offset
+ i
* pfl
->bank_width
));
363 case 0x98: /* Query mode */
364 if (!pfl
->device_width
) {
365 /* Preserve old behavior if device width not specified */
366 boff
= offset
& 0xFF;
367 if (pfl
->bank_width
== 2) {
369 } else if (pfl
->bank_width
== 4) {
373 if (boff
< sizeof(pfl
->cfi_table
)) {
374 ret
= pfl
->cfi_table
[boff
];
379 /* If we have a read larger than the bank_width, combine multiple
380 * CFI queries into a single response.
383 for (i
= 0; i
< width
; i
+= pfl
->bank_width
) {
384 ret
= deposit32(ret
, i
* 8, pfl
->bank_width
* 8,
385 pflash_cfi_query(pfl
,
386 offset
+ i
* pfl
->bank_width
));
395 /* update flash content on disk */
396 static void pflash_update(PFlashCFI01
*pfl
, int offset
,
401 offset_end
= offset
+ size
;
402 /* widen to sector boundaries */
403 offset
= QEMU_ALIGN_DOWN(offset
, BDRV_SECTOR_SIZE
);
404 offset_end
= QEMU_ALIGN_UP(offset_end
, BDRV_SECTOR_SIZE
);
405 blk_pwrite(pfl
->blk
, offset
, pfl
->storage
+ offset
,
406 offset_end
- offset
, 0);
410 static inline void pflash_data_write(PFlashCFI01
*pfl
, hwaddr offset
,
411 uint32_t value
, int width
, int be
)
413 uint8_t *p
= pfl
->storage
;
415 trace_pflash_data_write(offset
, value
, width
, pfl
->counter
);
422 p
[offset
] = value
>> 8;
423 p
[offset
+ 1] = value
;
426 p
[offset
+ 1] = value
>> 8;
431 p
[offset
] = value
>> 24;
432 p
[offset
+ 1] = value
>> 16;
433 p
[offset
+ 2] = value
>> 8;
434 p
[offset
+ 3] = value
;
437 p
[offset
+ 1] = value
>> 8;
438 p
[offset
+ 2] = value
>> 16;
439 p
[offset
+ 3] = value
>> 24;
446 static void pflash_write(PFlashCFI01
*pfl
, hwaddr offset
,
447 uint32_t value
, int width
, int be
)
454 trace_pflash_write(offset
, value
, width
, pfl
->wcycle
);
456 /* Set the device in I/O access mode */
457 memory_region_rom_device_set_romd(&pfl
->mem
, false);
460 switch (pfl
->wcycle
) {
466 case 0x10: /* Single Byte Program */
467 case 0x40: /* Single Byte Program */
468 DPRINTF("%s: Single Byte Program\n", __func__
);
470 case 0x20: /* Block erase */
472 offset
&= ~(pfl
->sector_len
- 1);
474 DPRINTF("%s: block erase at " TARGET_FMT_plx
" bytes %x\n",
475 __func__
, offset
, (unsigned)pfl
->sector_len
);
478 memset(p
+ offset
, 0xff, pfl
->sector_len
);
479 pflash_update(pfl
, offset
, pfl
->sector_len
);
481 pfl
->status
|= 0x20; /* Block erase error */
483 pfl
->status
|= 0x80; /* Ready! */
485 case 0x50: /* Clear status bits */
486 DPRINTF("%s: Clear status bits\n", __func__
);
489 case 0x60: /* Block (un)lock */
490 DPRINTF("%s: Block unlock\n", __func__
);
492 case 0x70: /* Status Register */
493 DPRINTF("%s: Read status register\n", __func__
);
496 case 0x90: /* Read Device ID */
497 DPRINTF("%s: Read Device information\n", __func__
);
500 case 0x98: /* CFI query */
501 DPRINTF("%s: CFI query\n", __func__
);
503 case 0xe8: /* Write to buffer */
504 DPRINTF("%s: Write to buffer\n", __func__
);
505 /* FIXME should save @offset, @width for case 1+ */
506 qemu_log_mask(LOG_UNIMP
,
507 "%s: Write to buffer emulation is flawed\n",
509 pfl
->status
|= 0x80; /* Ready! */
511 case 0xf0: /* Probe for AMD flash */
512 DPRINTF("%s: Probe for AMD flash\n", __func__
);
514 case 0xff: /* Read array mode */
515 DPRINTF("%s: Read array mode\n", __func__
);
525 case 0x10: /* Single Byte Program */
526 case 0x40: /* Single Byte Program */
527 DPRINTF("%s: Single Byte Program\n", __func__
);
529 pflash_data_write(pfl
, offset
, value
, width
, be
);
530 pflash_update(pfl
, offset
, width
);
532 pfl
->status
|= 0x10; /* Programming error */
534 pfl
->status
|= 0x80; /* Ready! */
537 case 0x20: /* Block erase */
539 if (cmd
== 0xd0) { /* confirm */
542 } else if (cmd
== 0xff) { /* read array mode */
549 /* Mask writeblock size based on device width, or bank width if
550 * device width not specified.
552 /* FIXME check @offset, @width */
553 if (pfl
->device_width
) {
554 value
= extract32(value
, 0, pfl
->device_width
* 8);
556 value
= extract32(value
, 0, pfl
->bank_width
* 8);
558 DPRINTF("%s: block write of %x bytes\n", __func__
, value
);
559 pfl
->counter
= value
;
566 } else if (cmd
== 0x01) {
569 } else if (cmd
== 0xff) {
572 DPRINTF("%s: Unknown (un)locking command\n", __func__
);
580 DPRINTF("%s: leaving query mode\n", __func__
);
589 case 0xe8: /* Block write */
590 /* FIXME check @offset, @width */
593 * FIXME writing straight to memory is *wrong*. We
594 * should write to a buffer, and flush it to memory
595 * only on confirm command (see below).
597 pflash_data_write(pfl
, offset
, value
, width
, be
);
599 pfl
->status
|= 0x10; /* Programming error */
605 hwaddr mask
= pfl
->writeblock_size
- 1;
608 DPRINTF("%s: block write finished\n", __func__
);
611 /* Flush the entire write buffer onto backing storage. */
612 /* FIXME premature! */
613 pflash_update(pfl
, offset
& mask
, pfl
->writeblock_size
);
615 pfl
->status
|= 0x10; /* Programming error */
625 case 3: /* Confirm mode */
627 case 0xe8: /* Block write */
629 /* FIXME this is where we should write out the buffer */
633 qemu_log_mask(LOG_UNIMP
,
634 "%s: Aborting write to buffer not implemented,"
635 " the data is already written to storage!\n"
636 "Flash device reset into READ mode.\n",
646 /* Should never happen */
647 DPRINTF("%s: invalid write state\n", __func__
);
653 qemu_log_mask(LOG_UNIMP
, "%s: Unimplemented flash cmd sequence "
654 "(offset " TARGET_FMT_plx
", wcycle 0x%x cmd 0x%x value 0x%x)"
655 "\n", __func__
, offset
, pfl
->wcycle
, pfl
->cmd
, value
);
658 trace_pflash_reset();
659 memory_region_rom_device_set_romd(&pfl
->mem
, true);
665 static MemTxResult
pflash_mem_read_with_attrs(void *opaque
, hwaddr addr
, uint64_t *value
,
666 unsigned len
, MemTxAttrs attrs
)
668 PFlashCFI01
*pfl
= opaque
;
669 bool be
= !!(pfl
->features
& (1 << PFLASH_BE
));
671 if ((pfl
->features
& (1 << PFLASH_SECURE
)) && !attrs
.secure
) {
672 *value
= pflash_data_read(opaque
, addr
, len
, be
);
674 *value
= pflash_read(opaque
, addr
, len
, be
);
679 static MemTxResult
pflash_mem_write_with_attrs(void *opaque
, hwaddr addr
, uint64_t value
,
680 unsigned len
, MemTxAttrs attrs
)
682 PFlashCFI01
*pfl
= opaque
;
683 bool be
= !!(pfl
->features
& (1 << PFLASH_BE
));
685 if ((pfl
->features
& (1 << PFLASH_SECURE
)) && !attrs
.secure
) {
688 pflash_write(opaque
, addr
, value
, len
, be
);
693 static const MemoryRegionOps pflash_cfi01_ops
= {
694 .read_with_attrs
= pflash_mem_read_with_attrs
,
695 .write_with_attrs
= pflash_mem_write_with_attrs
,
696 .endianness
= DEVICE_NATIVE_ENDIAN
,
699 static void pflash_cfi01_realize(DeviceState
*dev
, Error
**errp
)
701 PFlashCFI01
*pfl
= PFLASH_CFI01(dev
);
704 uint64_t blocks_per_device
, sector_len_per_device
, device_len
;
706 Error
*local_err
= NULL
;
708 if (pfl
->sector_len
== 0) {
709 error_setg(errp
, "attribute \"sector-length\" not specified or zero.");
712 if (pfl
->nb_blocs
== 0) {
713 error_setg(errp
, "attribute \"num-blocks\" not specified or zero.");
716 if (pfl
->name
== NULL
) {
717 error_setg(errp
, "attribute \"name\" not specified.");
721 total_len
= pfl
->sector_len
* pfl
->nb_blocs
;
723 /* These are only used to expose the parameters of each device
724 * in the cfi_table[].
726 num_devices
= pfl
->device_width
? (pfl
->bank_width
/ pfl
->device_width
) : 1;
727 if (pfl
->old_multiple_chip_handling
) {
728 blocks_per_device
= pfl
->nb_blocs
/ num_devices
;
729 sector_len_per_device
= pfl
->sector_len
;
731 blocks_per_device
= pfl
->nb_blocs
;
732 sector_len_per_device
= pfl
->sector_len
/ num_devices
;
734 device_len
= sector_len_per_device
* blocks_per_device
;
736 /* XXX: to be fixed */
738 if (total_len
!= (8 * 1024 * 1024) && total_len
!= (16 * 1024 * 1024) &&
739 total_len
!= (32 * 1024 * 1024) && total_len
!= (64 * 1024 * 1024))
743 memory_region_init_rom_device(
744 &pfl
->mem
, OBJECT(dev
),
747 pfl
->name
, total_len
, &local_err
);
749 error_propagate(errp
, local_err
);
753 pfl
->storage
= memory_region_get_ram_ptr(&pfl
->mem
);
754 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &pfl
->mem
);
758 pfl
->ro
= blk_is_read_only(pfl
->blk
);
759 perm
= BLK_PERM_CONSISTENT_READ
| (pfl
->ro
? 0 : BLK_PERM_WRITE
);
760 ret
= blk_set_perm(pfl
->blk
, perm
, BLK_PERM_ALL
, errp
);
769 /* read the initial flash content */
770 ret
= blk_pread(pfl
->blk
, 0, pfl
->storage
, total_len
);
773 vmstate_unregister_ram(&pfl
->mem
, DEVICE(pfl
));
774 error_setg(errp
, "failed to read the initial flash content");
779 /* Default to devices being used at their maximum device width. This was
780 * assumed before the device_width support was added.
782 if (!pfl
->max_device_width
) {
783 pfl
->max_device_width
= pfl
->device_width
;
786 pfl
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, pflash_timer
, pfl
);
790 /* Hardcoded CFI table */
791 /* Standard "QRY" string */
792 pfl
->cfi_table
[0x10] = 'Q';
793 pfl
->cfi_table
[0x11] = 'R';
794 pfl
->cfi_table
[0x12] = 'Y';
795 /* Command set (Intel) */
796 pfl
->cfi_table
[0x13] = 0x01;
797 pfl
->cfi_table
[0x14] = 0x00;
798 /* Primary extended table address (none) */
799 pfl
->cfi_table
[0x15] = 0x31;
800 pfl
->cfi_table
[0x16] = 0x00;
801 /* Alternate command set (none) */
802 pfl
->cfi_table
[0x17] = 0x00;
803 pfl
->cfi_table
[0x18] = 0x00;
804 /* Alternate extended table (none) */
805 pfl
->cfi_table
[0x19] = 0x00;
806 pfl
->cfi_table
[0x1A] = 0x00;
808 pfl
->cfi_table
[0x1B] = 0x45;
810 pfl
->cfi_table
[0x1C] = 0x55;
811 /* Vpp min (no Vpp pin) */
812 pfl
->cfi_table
[0x1D] = 0x00;
813 /* Vpp max (no Vpp pin) */
814 pfl
->cfi_table
[0x1E] = 0x00;
816 pfl
->cfi_table
[0x1F] = 0x07;
817 /* Timeout for min size buffer write */
818 pfl
->cfi_table
[0x20] = 0x07;
819 /* Typical timeout for block erase */
820 pfl
->cfi_table
[0x21] = 0x0a;
821 /* Typical timeout for full chip erase (4096 ms) */
822 pfl
->cfi_table
[0x22] = 0x00;
824 pfl
->cfi_table
[0x23] = 0x04;
825 /* Max timeout for buffer write */
826 pfl
->cfi_table
[0x24] = 0x04;
827 /* Max timeout for block erase */
828 pfl
->cfi_table
[0x25] = 0x04;
829 /* Max timeout for chip erase */
830 pfl
->cfi_table
[0x26] = 0x00;
832 pfl
->cfi_table
[0x27] = ctz32(device_len
); /* + 1; */
833 /* Flash device interface (8 & 16 bits) */
834 pfl
->cfi_table
[0x28] = 0x02;
835 pfl
->cfi_table
[0x29] = 0x00;
836 /* Max number of bytes in multi-bytes write */
837 if (pfl
->bank_width
== 1) {
838 pfl
->cfi_table
[0x2A] = 0x08;
840 pfl
->cfi_table
[0x2A] = 0x0B;
842 pfl
->writeblock_size
= 1 << pfl
->cfi_table
[0x2A];
843 if (!pfl
->old_multiple_chip_handling
&& num_devices
> 1) {
844 pfl
->writeblock_size
*= num_devices
;
847 pfl
->cfi_table
[0x2B] = 0x00;
848 /* Number of erase block regions (uniform) */
849 pfl
->cfi_table
[0x2C] = 0x01;
850 /* Erase block region 1 */
851 pfl
->cfi_table
[0x2D] = blocks_per_device
- 1;
852 pfl
->cfi_table
[0x2E] = (blocks_per_device
- 1) >> 8;
853 pfl
->cfi_table
[0x2F] = sector_len_per_device
>> 8;
854 pfl
->cfi_table
[0x30] = sector_len_per_device
>> 16;
857 pfl
->cfi_table
[0x31] = 'P';
858 pfl
->cfi_table
[0x32] = 'R';
859 pfl
->cfi_table
[0x33] = 'I';
861 pfl
->cfi_table
[0x34] = '1';
862 pfl
->cfi_table
[0x35] = '0';
864 pfl
->cfi_table
[0x36] = 0x00;
865 pfl
->cfi_table
[0x37] = 0x00;
866 pfl
->cfi_table
[0x38] = 0x00;
867 pfl
->cfi_table
[0x39] = 0x00;
869 pfl
->cfi_table
[0x3a] = 0x00;
871 pfl
->cfi_table
[0x3b] = 0x00;
872 pfl
->cfi_table
[0x3c] = 0x00;
874 pfl
->cfi_table
[0x3f] = 0x01; /* Number of protection fields */
877 static Property pflash_cfi01_properties
[] = {
878 DEFINE_PROP_DRIVE("drive", PFlashCFI01
, blk
),
879 /* num-blocks is the number of blocks actually visible to the guest,
880 * ie the total size of the device divided by the sector length.
881 * If we're emulating flash devices wired in parallel the actual
882 * number of blocks per indvidual device will differ.
884 DEFINE_PROP_UINT32("num-blocks", PFlashCFI01
, nb_blocs
, 0),
885 DEFINE_PROP_UINT64("sector-length", PFlashCFI01
, sector_len
, 0),
886 /* width here is the overall width of this QEMU device in bytes.
887 * The QEMU device may be emulating a number of flash devices
888 * wired up in parallel; the width of each individual flash
889 * device should be specified via device-width. If the individual
890 * devices have a maximum width which is greater than the width
891 * they are being used for, this maximum width should be set via
892 * max-device-width (which otherwise defaults to device-width).
893 * So for instance a 32-bit wide QEMU flash device made from four
894 * 16-bit flash devices used in 8-bit wide mode would be configured
895 * with width = 4, device-width = 1, max-device-width = 2.
897 * If device-width is not specified we default to backwards
898 * compatible behaviour which is a bad emulation of two
899 * 16 bit devices making up a 32 bit wide QEMU device. This
900 * is deprecated for new uses of this device.
902 DEFINE_PROP_UINT8("width", PFlashCFI01
, bank_width
, 0),
903 DEFINE_PROP_UINT8("device-width", PFlashCFI01
, device_width
, 0),
904 DEFINE_PROP_UINT8("max-device-width", PFlashCFI01
, max_device_width
, 0),
905 DEFINE_PROP_BIT("big-endian", PFlashCFI01
, features
, PFLASH_BE
, 0),
906 DEFINE_PROP_BIT("secure", PFlashCFI01
, features
, PFLASH_SECURE
, 0),
907 DEFINE_PROP_UINT16("id0", PFlashCFI01
, ident0
, 0),
908 DEFINE_PROP_UINT16("id1", PFlashCFI01
, ident1
, 0),
909 DEFINE_PROP_UINT16("id2", PFlashCFI01
, ident2
, 0),
910 DEFINE_PROP_UINT16("id3", PFlashCFI01
, ident3
, 0),
911 DEFINE_PROP_STRING("name", PFlashCFI01
, name
),
912 DEFINE_PROP_BOOL("old-multiple-chip-handling", PFlashCFI01
,
913 old_multiple_chip_handling
, false),
914 DEFINE_PROP_END_OF_LIST(),
917 static void pflash_cfi01_class_init(ObjectClass
*klass
, void *data
)
919 DeviceClass
*dc
= DEVICE_CLASS(klass
);
921 dc
->realize
= pflash_cfi01_realize
;
922 dc
->props
= pflash_cfi01_properties
;
923 dc
->vmsd
= &vmstate_pflash
;
924 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
928 static const TypeInfo pflash_cfi01_info
= {
929 .name
= TYPE_PFLASH_CFI01
,
930 .parent
= TYPE_SYS_BUS_DEVICE
,
931 .instance_size
= sizeof(PFlashCFI01
),
932 .class_init
= pflash_cfi01_class_init
,
935 static void pflash_cfi01_register_types(void)
937 type_register_static(&pflash_cfi01_info
);
940 type_init(pflash_cfi01_register_types
)
942 PFlashCFI01
*pflash_cfi01_register(hwaddr base
,
943 DeviceState
*qdev
, const char *name
,
946 uint32_t sector_len
, int nb_blocs
,
948 uint16_t id0
, uint16_t id1
,
949 uint16_t id2
, uint16_t id3
,
952 DeviceState
*dev
= qdev_create(NULL
, TYPE_PFLASH_CFI01
);
955 qdev_prop_set_drive(dev
, "drive", blk
, &error_abort
);
957 qdev_prop_set_uint32(dev
, "num-blocks", nb_blocs
);
958 qdev_prop_set_uint64(dev
, "sector-length", sector_len
);
959 qdev_prop_set_uint8(dev
, "width", bank_width
);
960 qdev_prop_set_bit(dev
, "big-endian", !!be
);
961 qdev_prop_set_uint16(dev
, "id0", id0
);
962 qdev_prop_set_uint16(dev
, "id1", id1
);
963 qdev_prop_set_uint16(dev
, "id2", id2
);
964 qdev_prop_set_uint16(dev
, "id3", id3
);
965 qdev_prop_set_string(dev
, "name", name
);
966 qdev_init_nofail(dev
);
968 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
969 return PFLASH_CFI01(dev
);
972 MemoryRegion
*pflash_cfi01_get_memory(PFlashCFI01
*fl
)
977 static void postload_update_cb(void *opaque
, int running
, RunState state
)
979 PFlashCFI01
*pfl
= opaque
;
981 /* This is called after bdrv_invalidate_cache_all. */
982 qemu_del_vm_change_state_handler(pfl
->vmstate
);
985 DPRINTF("%s: updating bdrv for %s\n", __func__
, pfl
->name
);
986 pflash_update(pfl
, 0, pfl
->sector_len
* pfl
->nb_blocs
);
989 static int pflash_post_load(void *opaque
, int version_id
)
991 PFlashCFI01
*pfl
= opaque
;
994 pfl
->vmstate
= qemu_add_vm_change_state_handler(postload_update_cb
,