hw/block/pflash_cfi02.c

   1 /*
   2  *  CFI parallel flash with AMD command set emulation
   3  *
   4  *  Copyright (c) 2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /*
  21  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  22  * Supported commands/modes are:
  23  * - flash read
  24  * - flash write
  25  * - flash ID read
  26  * - sector erase
  27  * - chip erase
  28  * - unlock bypass command
  29  * - CFI queries
  30  *
  31  * It does not support flash interleaving.
  32  * It does not implement software data protection as found in many real chips
  33  * It does not implement erase suspend/resume commands
  34  * It does not implement multiple sectors erase
  35  */
  36
  37 #include "qemu/osdep.h"
  38 #include "hw/hw.h"
  39 #include "hw/block/block.h"
  40 #include "hw/block/flash.h"
  41 #include "qapi/error.h"
  42 #include "qemu/timer.h"
  43 #include "sysemu/block-backend.h"
  44 #include "qemu/host-utils.h"
  45 #include "qemu/module.h"
  46 #include "hw/sysbus.h"
  47 #include "trace.h"
  48
  49 #define PFLASH_DEBUG false
  50 #define DPRINTF(fmt, ...)                                  \
  51 do {                                                       \
  52     if (PFLASH_DEBUG) {                                    \
  53         fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__);   \
  54     }                                                      \
  55 } while (0)
  56
  57 #define PFLASH_LAZY_ROMD_THRESHOLD 42
  58
  59 /*
  60  * The size of the cfi_table indirectly depends on this and the start of the
  61  * PRI table directly depends on it. 4 is the maximum size (and also what
  62  * seems common) without changing the PRT table address.
  63  */
  64 #define PFLASH_MAX_ERASE_REGIONS 4
  65
  66 /* Special write cycles for CFI queries. */
  67 enum {
  68     WCYCLE_CFI              = 7,
  69 };
  70
  71 struct PFlashCFI02 {
  72     /*< private >*/
  73     SysBusDevice parent_obj;
  74     /*< public >*/
  75
  76     BlockBackend *blk;
  77     uint32_t uniform_nb_blocs;
  78     uint32_t uniform_sector_len;
  79     uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS];
  80     uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS];
  81     uint32_t chip_len;
  82     uint8_t mappings;
  83     uint8_t width;
  84     uint8_t be;
  85     int wcycle; /* if 0, the flash is read normally */
  86     int bypass;
  87     int ro;
  88     uint8_t cmd;
  89     uint8_t status;
  90     /* FIXME: implement array device properties */
  91     uint16_t ident0;
  92     uint16_t ident1;
  93     uint16_t ident2;
  94     uint16_t ident3;
  95     uint16_t unlock_addr0;
  96     uint16_t unlock_addr1;
  97     uint8_t cfi_table[0x4d];
  98     QEMUTimer timer;
  99     /* The device replicates the flash memory across its memory space.  Emulate
 100      * that by having a container (.mem) filled with an array of aliases
 101      * (.mem_mappings) pointing to the flash memory (.orig_mem).
 102      */
 103     MemoryRegion mem;
 104     MemoryRegion *mem_mappings;    /* array; one per mapping */
 105     MemoryRegion orig_mem;
 106     int rom_mode;
 107     int read_counter; /* used for lazy switch-back to rom mode */
 108     char *name;
 109     void *storage;
 110 };
 111
 112 /*
 113  * Toggle status bit DQ7.
 114  */
 115 static inline void toggle_dq7(PFlashCFI02 *pfl)
 116 {
 117     pfl->status ^= 0x80;
 118 }
 119
 120 /*
 121  * Set status bit DQ7 to bit 7 of value.
 122  */
 123 static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value)
 124 {
 125     pfl->status &= 0x7F;
 126     pfl->status |= value & 0x80;
 127 }
 128
 129 /*
 130  * Toggle status bit DQ6.
 131  */
 132 static inline void toggle_dq6(PFlashCFI02 *pfl)
 133 {
 134     pfl->status ^= 0x40;
 135 }
 136
 137 /*
 138  * Set up replicated mappings of the same region.
 139  */
 140 static void pflash_setup_mappings(PFlashCFI02 *pfl)
 141 {
 142     unsigned i;
 143     hwaddr size = memory_region_size(&pfl->orig_mem);
 144
 145     memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
 146     pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
 147     for (i = 0; i < pfl->mappings; ++i) {
 148         memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
 149                                  "pflash-alias", &pfl->orig_mem, 0, size);
 150         memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
 151     }
 152 }
 153
 154 static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode)
 155 {
 156     memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode);
 157     pfl->rom_mode = rom_mode;
 158 }
 159
 160 static void pflash_timer (void *opaque)
 161 {
 162     PFlashCFI02 *pfl = opaque;
 163
 164     trace_pflash_timer_expired(pfl->cmd);
 165     /* Reset flash */
 166     toggle_dq7(pfl);
 167     if (pfl->bypass) {
 168         pfl->wcycle = 2;
 169     } else {
 170         pflash_register_memory(pfl, 1);
 171         pfl->wcycle = 0;
 172     }
 173     pfl->cmd = 0;
 174 }
 175
 176 /*
 177  * Read data from flash.
 178  */
 179 static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset,
 180                                  unsigned int width)
 181 {
 182     uint8_t *p = (uint8_t *)pfl->storage + offset;
 183     uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width);
 184     trace_pflash_data_read(offset, width << 1, ret);
 185     return ret;
 186 }
 187
 188 /*
 189  * offset should be a byte offset of the QEMU device and _not_ a device
 190  * offset.
 191  */
 192 static uint32_t pflash_sector_len(PFlashCFI02 *pfl, hwaddr offset)
 193 {
 194     assert(offset < pfl->chip_len);
 195     int nb_regions = pfl->cfi_table[0x2C];
 196     hwaddr addr = 0;
 197     for (int i = 0; i < nb_regions; ++i) {
 198         uint64_t region_size = (uint64_t)pfl->nb_blocs[i] * pfl->sector_len[i];
 199         if (addr <= offset && offset < addr + region_size) {
 200             return pfl->sector_len[i];
 201         }
 202         addr += region_size;
 203     }
 204     abort();
 205 }
 206
 207 static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
 208 {
 209     PFlashCFI02 *pfl = opaque;
 210     hwaddr boff;
 211     uint64_t ret;
 212
 213     ret = -1;
 214     /* Lazy reset to ROMD mode after a certain amount of read accesses */
 215     if (!pfl->rom_mode && pfl->wcycle == 0 &&
 216         ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
 217         pflash_register_memory(pfl, 1);
 218     }
 219     offset &= pfl->chip_len - 1;
 220     boff = offset & 0xFF;
 221     if (pfl->width == 2) {
 222         boff = boff >> 1;
 223     } else if (pfl->width == 4) {
 224         boff = boff >> 2;
 225     }
 226     switch (pfl->cmd) {
 227     default:
 228         /* This should never happen : reset state & treat it as a read*/
 229         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 230         pfl->wcycle = 0;
 231         pfl->cmd = 0;
 232         /* fall through to the read code */
 233     case 0x80:
 234         /* We accept reads during second unlock sequence... */
 235     case 0x00:
 236         /* Flash area read */
 237         ret = pflash_data_read(pfl, offset, width);
 238         break;
 239     case 0x90:
 240         /* flash ID read */
 241         switch (boff) {
 242         case 0x00:
 243         case 0x01:
 244             ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
 245             break;
 246         case 0x02:
 247             ret = 0x00; /* Pretend all sectors are unprotected */
 248             break;
 249         case 0x0E:
 250         case 0x0F:
 251             ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
 252             if (ret != (uint8_t)-1) {
 253                 break;
 254             }
 255             /* Fall through to data read. */
 256         default:
 257             ret = pflash_data_read(pfl, offset, width);
 258         }
 259         DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff, ret);
 260         break;
 261     case 0xA0:
 262     case 0x10:
 263     case 0x30:
 264         /* Status register read */
 265         ret = pfl->status;
 266         DPRINTF("%s: status %" PRIx64 "\n", __func__, ret);
 267         toggle_dq6(pfl);
 268         break;
 269     case 0x98:
 270         /* CFI query mode */
 271         if (boff < sizeof(pfl->cfi_table)) {
 272             ret = pfl->cfi_table[boff];
 273         } else {
 274             ret = 0;
 275         }
 276         break;
 277     }
 278     trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle);
 279
 280     return ret;
 281 }
 282
 283 /* update flash content on disk */
 284 static void pflash_update(PFlashCFI02 *pfl, int offset, int size)
 285 {
 286     int offset_end;
 287     if (pfl->blk) {
 288         offset_end = offset + size;
 289         /* widen to sector boundaries */
 290         offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
 291         offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
 292         blk_pwrite(pfl->blk, offset, pfl->storage + offset,
 293                    offset_end - offset, 0);
 294     }
 295 }
 296
 297 static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
 298                          unsigned int width)
 299 {
 300     PFlashCFI02 *pfl = opaque;
 301     hwaddr boff;
 302     uint8_t *p;
 303     uint8_t cmd;
 304     uint32_t sector_len;
 305
 306     trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle);
 307     cmd = value;
 308     if (pfl->cmd != 0xA0 && cmd == 0xF0) {
 309         goto reset_flash;
 310     }
 311     offset &= pfl->chip_len - 1;
 312
 313     boff = offset;
 314     if (pfl->width == 2) {
 315         boff = boff >> 1;
 316     } else if (pfl->width == 4) {
 317         boff = boff >> 2;
 318     }
 319     /* Only the least-significant 11 bits are used in most cases. */
 320     boff &= 0x7FF;
 321     switch (pfl->wcycle) {
 322     case 0:
 323         /* Set the device in I/O access mode if required */
 324         if (pfl->rom_mode)
 325             pflash_register_memory(pfl, 0);
 326         pfl->read_counter = 0;
 327         /* We're in read mode */
 328     check_unlock0:
 329         if (boff == 0x55 && cmd == 0x98) {
 330         enter_CFI_mode:
 331             /* Enter CFI query mode */
 332             pfl->wcycle = WCYCLE_CFI;
 333             pfl->cmd = 0x98;
 334             return;
 335         }
 336         if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
 337             DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
 338                     __func__, boff, cmd, pfl->unlock_addr0);
 339             goto reset_flash;
 340         }
 341         DPRINTF("%s: unlock sequence started\n", __func__);
 342         break;
 343     case 1:
 344         /* We started an unlock sequence */
 345     check_unlock1:
 346         if (boff != pfl->unlock_addr1 || cmd != 0x55) {
 347             DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
 348                     boff, cmd);
 349             goto reset_flash;
 350         }
 351         DPRINTF("%s: unlock sequence done\n", __func__);
 352         break;
 353     case 2:
 354         /* We finished an unlock sequence */
 355         if (!pfl->bypass && boff != pfl->unlock_addr0) {
 356             DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
 357                     boff, cmd);
 358             goto reset_flash;
 359         }
 360         switch (cmd) {
 361         case 0x20:
 362             pfl->bypass = 1;
 363             goto do_bypass;
 364         case 0x80:
 365         case 0x90:
 366         case 0xA0:
 367             pfl->cmd = cmd;
 368             DPRINTF("%s: starting command %02x\n", __func__, cmd);
 369             break;
 370         default:
 371             DPRINTF("%s: unknown command %02x\n", __func__, cmd);
 372             goto reset_flash;
 373         }
 374         break;
 375     case 3:
 376         switch (pfl->cmd) {
 377         case 0x80:
 378             /* We need another unlock sequence */
 379             goto check_unlock0;
 380         case 0xA0:
 381             trace_pflash_data_write(offset, width << 1, value, 0);
 382             if (!pfl->ro) {
 383                 p = (uint8_t *)pfl->storage + offset;
 384                 if (pfl->be) {
 385                     uint64_t current = ldn_be_p(p, width);
 386                     stn_be_p(p, width, current & value);
 387                 } else {
 388                     uint64_t current = ldn_le_p(p, width);
 389                     stn_le_p(p, width, current & value);
 390                 }
 391                 pflash_update(pfl, offset, width);
 392             }
 393             /*
 394              * While programming, status bit DQ7 should hold the opposite
 395              * value from how it was programmed.
 396              */
 397             set_dq7(pfl, ~value);
 398             /* Let's pretend write is immediate */
 399             if (pfl->bypass)
 400                 goto do_bypass;
 401             goto reset_flash;
 402         case 0x90:
 403             if (pfl->bypass && cmd == 0x00) {
 404                 /* Unlock bypass reset */
 405                 goto reset_flash;
 406             }
 407             /* We can enter CFI query mode from autoselect mode */
 408             if (boff == 0x55 && cmd == 0x98)
 409                 goto enter_CFI_mode;
 410             /* No break here */
 411         default:
 412             DPRINTF("%s: invalid write for command %02x\n",
 413                     __func__, pfl->cmd);
 414             goto reset_flash;
 415         }
 416     case 4:
 417         switch (pfl->cmd) {
 418         case 0xA0:
 419             /* Ignore writes while flash data write is occurring */
 420             /* As we suppose write is immediate, this should never happen */
 421             return;
 422         case 0x80:
 423             goto check_unlock1;
 424         default:
 425             /* Should never happen */
 426             DPRINTF("%s: invalid command state %02x (wc 4)\n",
 427                     __func__, pfl->cmd);
 428             goto reset_flash;
 429         }
 430         break;
 431     case 5:
 432         switch (cmd) {
 433         case 0x10:
 434             if (boff != pfl->unlock_addr0) {
 435                 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
 436                         __func__, offset);
 437                 goto reset_flash;
 438             }
 439             /* Chip erase */
 440             DPRINTF("%s: start chip erase\n", __func__);
 441             if (!pfl->ro) {
 442                 memset(pfl->storage, 0xff, pfl->chip_len);
 443                 pflash_update(pfl, 0, pfl->chip_len);
 444             }
 445             set_dq7(pfl, 0x00);
 446             /* Let's wait 5 seconds before chip erase is done */
 447             timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 448                       (NANOSECONDS_PER_SECOND * 5));
 449             break;
 450         case 0x30:
 451             /* Sector erase */
 452             p = pfl->storage;
 453             sector_len = pflash_sector_len(pfl, offset);
 454             offset &= ~(sector_len - 1);
 455             DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n",
 456                     __func__, pfl->width * 2, offset,
 457                     pfl->width * 2, offset + sector_len - 1);
 458             if (!pfl->ro) {
 459                 memset(p + offset, 0xff, sector_len);
 460                 pflash_update(pfl, offset, sector_len);
 461             }
 462             set_dq7(pfl, 0x00);
 463             /* Let's wait 1/2 second before sector erase is done */
 464             timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 465                       (NANOSECONDS_PER_SECOND / 2));
 466             break;
 467         default:
 468             DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
 469             goto reset_flash;
 470         }
 471         pfl->cmd = cmd;
 472         break;
 473     case 6:
 474         switch (pfl->cmd) {
 475         case 0x10:
 476             /* Ignore writes during chip erase */
 477             return;
 478         case 0x30:
 479             /* Ignore writes during sector erase */
 480             return;
 481         default:
 482             /* Should never happen */
 483             DPRINTF("%s: invalid command state %02x (wc 6)\n",
 484                     __func__, pfl->cmd);
 485             goto reset_flash;
 486         }
 487         break;
 488     /* Special values for CFI queries */
 489     case WCYCLE_CFI:
 490         DPRINTF("%s: invalid write in CFI query mode\n", __func__);
 491         goto reset_flash;
 492     default:
 493         /* Should never happen */
 494         DPRINTF("%s: invalid write state (wc 7)\n",  __func__);
 495         goto reset_flash;
 496     }
 497     pfl->wcycle++;
 498
 499     return;
 500
 501     /* Reset flash */
 502  reset_flash:
 503     trace_pflash_reset();
 504     pfl->bypass = 0;
 505     pfl->wcycle = 0;
 506     pfl->cmd = 0;
 507     return;
 508
 509  do_bypass:
 510     pfl->wcycle = 2;
 511     pfl->cmd = 0;
 512 }
 513
 514 static const MemoryRegionOps pflash_cfi02_ops = {
 515     .read = pflash_read,
 516     .write = pflash_write,
 517     .valid.min_access_size = 1,
 518     .valid.max_access_size = 4,
 519     .endianness = DEVICE_NATIVE_ENDIAN,
 520 };
 521
 522 static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
 523 {
 524     PFlashCFI02 *pfl = PFLASH_CFI02(dev);
 525     int ret;
 526     Error *local_err = NULL;
 527
 528     if (pfl->uniform_sector_len == 0 && pfl->sector_len[0] == 0) {
 529         error_setg(errp, "attribute \"sector-length\" not specified or zero.");
 530         return;
 531     }
 532     if (pfl->uniform_nb_blocs == 0 && pfl->nb_blocs[0] == 0) {
 533         error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
 534         return;
 535     }
 536     if (pfl->name == NULL) {
 537         error_setg(errp, "attribute \"name\" not specified.");
 538         return;
 539     }
 540
 541     int nb_regions;
 542     pfl->chip_len = 0;
 543     for (nb_regions = 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_regions) {
 544         if (pfl->nb_blocs[nb_regions] == 0) {
 545             break;
 546         }
 547         uint64_t sector_len_per_device = pfl->sector_len[nb_regions];
 548
 549         /*
 550          * The size of each flash sector must be a power of 2 and it must be
 551          * aligned at the same power of 2.
 552          */
 553         if (sector_len_per_device & 0xff ||
 554             sector_len_per_device >= (1 << 24) ||
 555             !is_power_of_2(sector_len_per_device))
 556         {
 557             error_setg(errp, "unsupported configuration: "
 558                        "sector length[%d] per device = %" PRIx64 ".",
 559                        nb_regions, sector_len_per_device);
 560             return;
 561         }
 562         if (pfl->chip_len & (sector_len_per_device - 1)) {
 563             error_setg(errp, "unsupported configuration: "
 564                        "flash region %d not correctly aligned.",
 565                        nb_regions);
 566             return;
 567         }
 568
 569         pfl->chip_len += (uint64_t)pfl->sector_len[nb_regions] *
 570                           pfl->nb_blocs[nb_regions];
 571     }
 572
 573     uint64_t uniform_len = (uint64_t)pfl->uniform_nb_blocs *
 574                            pfl->uniform_sector_len;
 575     if (nb_regions == 0) {
 576         nb_regions = 1;
 577         pfl->nb_blocs[0] = pfl->uniform_nb_blocs;
 578         pfl->sector_len[0] = pfl->uniform_sector_len;
 579         pfl->chip_len = uniform_len;
 580     } else if (uniform_len != 0 && uniform_len != pfl->chip_len) {
 581         error_setg(errp, "\"num-blocks\"*\"sector-length\" "
 582                    "different from \"num-blocks0\"*\'sector-length0\" + ... + "
 583                    "\"num-blocks3\"*\"sector-length3\"");
 584         return;
 585     }
 586
 587     memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl),
 588                                   &pflash_cfi02_ops, pfl, pfl->name,
 589                                   pfl->chip_len, &local_err);
 590     if (local_err) {
 591         error_propagate(errp, local_err);
 592         return;
 593     }
 594
 595     pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
 596
 597     if (pfl->blk) {
 598         uint64_t perm;
 599         pfl->ro = blk_is_read_only(pfl->blk);
 600         perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
 601         ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
 602         if (ret < 0) {
 603             return;
 604         }
 605     } else {
 606         pfl->ro = 0;
 607     }
 608
 609     if (pfl->blk) {
 610         if (!blk_check_size_and_read_all(pfl->blk, pfl->storage,
 611                                          pfl->chip_len, errp)) {
 612             vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
 613             return;
 614         }
 615     }
 616
 617     /* Only 11 bits are used in the comparison. */
 618     pfl->unlock_addr0 &= 0x7FF;
 619     pfl->unlock_addr1 &= 0x7FF;
 620
 621     pflash_setup_mappings(pfl);
 622     pfl->rom_mode = 1;
 623     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
 624
 625     timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
 626     pfl->wcycle = 0;
 627     pfl->cmd = 0;
 628     pfl->status = 0;
 629
 630     /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
 631     const uint16_t pri_ofs = 0x40;
 632     /* Standard "QRY" string */
 633     pfl->cfi_table[0x10] = 'Q';
 634     pfl->cfi_table[0x11] = 'R';
 635     pfl->cfi_table[0x12] = 'Y';
 636     /* Command set (AMD/Fujitsu) */
 637     pfl->cfi_table[0x13] = 0x02;
 638     pfl->cfi_table[0x14] = 0x00;
 639     /* Primary extended table address */
 640     pfl->cfi_table[0x15] = pri_ofs;
 641     pfl->cfi_table[0x16] = pri_ofs >> 8;
 642     /* Alternate command set (none) */
 643     pfl->cfi_table[0x17] = 0x00;
 644     pfl->cfi_table[0x18] = 0x00;
 645     /* Alternate extended table (none) */
 646     pfl->cfi_table[0x19] = 0x00;
 647     pfl->cfi_table[0x1A] = 0x00;
 648     /* Vcc min */
 649     pfl->cfi_table[0x1B] = 0x27;
 650     /* Vcc max */
 651     pfl->cfi_table[0x1C] = 0x36;
 652     /* Vpp min (no Vpp pin) */
 653     pfl->cfi_table[0x1D] = 0x00;
 654     /* Vpp max (no Vpp pin) */
 655     pfl->cfi_table[0x1E] = 0x00;
 656     /* Timeout per single byte/word write (128 ms) */
 657     pfl->cfi_table[0x1F] = 0x07;
 658     /* Timeout for min size buffer write (NA) */
 659     pfl->cfi_table[0x20] = 0x00;
 660     /* Typical timeout for block erase (512 ms) */
 661     pfl->cfi_table[0x21] = 0x09;
 662     /* Typical timeout for full chip erase (4096 ms) */
 663     pfl->cfi_table[0x22] = 0x0C;
 664     /* Reserved */
 665     pfl->cfi_table[0x23] = 0x01;
 666     /* Max timeout for buffer write (NA) */
 667     pfl->cfi_table[0x24] = 0x00;
 668     /* Max timeout for block erase */
 669     pfl->cfi_table[0x25] = 0x0A;
 670     /* Max timeout for chip erase */
 671     pfl->cfi_table[0x26] = 0x0D;
 672     /* Device size */
 673     pfl->cfi_table[0x27] = ctz32(pfl->chip_len);
 674     /* Flash device interface (8 & 16 bits) */
 675     pfl->cfi_table[0x28] = 0x02;
 676     pfl->cfi_table[0x29] = 0x00;
 677     /* Max number of bytes in multi-bytes write */
 678     /* XXX: disable buffered write as it's not supported */
 679     //    pfl->cfi_table[0x2A] = 0x05;
 680     pfl->cfi_table[0x2A] = 0x00;
 681     pfl->cfi_table[0x2B] = 0x00;
 682     /* Number of erase block regions */
 683     pfl->cfi_table[0x2c] = nb_regions;
 684     /* Erase block regions */
 685     for (int i = 0; i < nb_regions; ++i) {
 686         uint32_t sector_len_per_device = pfl->sector_len[i];
 687         pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1;
 688         pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8;
 689         pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8;
 690         pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16;
 691     }
 692     assert(0x2c + 4 * nb_regions < pri_ofs);
 693
 694     /* Extended */
 695     pfl->cfi_table[0x00 + pri_ofs] = 'P';
 696     pfl->cfi_table[0x01 + pri_ofs] = 'R';
 697     pfl->cfi_table[0x02 + pri_ofs] = 'I';
 698
 699     /* Extended version 1.0 */
 700     pfl->cfi_table[0x03 + pri_ofs] = '1';
 701     pfl->cfi_table[0x04 + pri_ofs] = '0';
 702
 703     /* Address sensitive unlock required. */
 704     pfl->cfi_table[0x05 + pri_ofs] = 0x00;
 705     /* Erase suspend not supported. */
 706     pfl->cfi_table[0x06 + pri_ofs] = 0x00;
 707     /* Sector protect not supported. */
 708     pfl->cfi_table[0x07 + pri_ofs] = 0x00;
 709     /* Temporary sector unprotect not supported. */
 710     pfl->cfi_table[0x08 + pri_ofs] = 0x00;
 711
 712     /* Sector protect/unprotect scheme. */
 713     pfl->cfi_table[0x09 + pri_ofs] = 0x00;
 714
 715     /* Simultaneous operation not supported. */
 716     pfl->cfi_table[0x0a + pri_ofs] = 0x00;
 717     /* Burst mode not supported. */
 718     pfl->cfi_table[0x0b + pri_ofs] = 0x00;
 719     /* Page mode not supported. */
 720     pfl->cfi_table[0x0c + pri_ofs] = 0x00;
 721     assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table));
 722 }
 723
 724 static Property pflash_cfi02_properties[] = {
 725     DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk),
 726     DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, uniform_nb_blocs, 0),
 727     DEFINE_PROP_UINT32("sector-length", PFlashCFI02, uniform_sector_len, 0),
 728     DEFINE_PROP_UINT32("num-blocks0", PFlashCFI02, nb_blocs[0], 0),
 729     DEFINE_PROP_UINT32("sector-length0", PFlashCFI02, sector_len[0], 0),
 730     DEFINE_PROP_UINT32("num-blocks1", PFlashCFI02, nb_blocs[1], 0),
 731     DEFINE_PROP_UINT32("sector-length1", PFlashCFI02, sector_len[1], 0),
 732     DEFINE_PROP_UINT32("num-blocks2", PFlashCFI02, nb_blocs[2], 0),
 733     DEFINE_PROP_UINT32("sector-length2", PFlashCFI02, sector_len[2], 0),
 734     DEFINE_PROP_UINT32("num-blocks3", PFlashCFI02, nb_blocs[3], 0),
 735     DEFINE_PROP_UINT32("sector-length3", PFlashCFI02, sector_len[3], 0),
 736     DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0),
 737     DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0),
 738     DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0),
 739     DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0),
 740     DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0),
 741     DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0),
 742     DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0),
 743     DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0),
 744     DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0),
 745     DEFINE_PROP_STRING("name", PFlashCFI02, name),
 746     DEFINE_PROP_END_OF_LIST(),
 747 };
 748
 749 static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp)
 750 {
 751     PFlashCFI02 *pfl = PFLASH_CFI02(dev);
 752     timer_del(&pfl->timer);
 753 }
 754
 755 static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
 756 {
 757     DeviceClass *dc = DEVICE_CLASS(klass);
 758
 759     dc->realize = pflash_cfi02_realize;
 760     dc->unrealize = pflash_cfi02_unrealize;
 761     dc->props = pflash_cfi02_properties;
 762     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 763 }
 764
 765 static const TypeInfo pflash_cfi02_info = {
 766     .name           = TYPE_PFLASH_CFI02,
 767     .parent         = TYPE_SYS_BUS_DEVICE,
 768     .instance_size  = sizeof(PFlashCFI02),
 769     .class_init     = pflash_cfi02_class_init,
 770 };
 771
 772 static void pflash_cfi02_register_types(void)
 773 {
 774     type_register_static(&pflash_cfi02_info);
 775 }
 776
 777 type_init(pflash_cfi02_register_types)
 778
 779 PFlashCFI02 *pflash_cfi02_register(hwaddr base,
 780                                    const char *name,
 781                                    hwaddr size,
 782                                    BlockBackend *blk,
 783                                    uint32_t sector_len,
 784                                    int nb_mappings, int width,
 785                                    uint16_t id0, uint16_t id1,
 786                                    uint16_t id2, uint16_t id3,
 787                                    uint16_t unlock_addr0,
 788                                    uint16_t unlock_addr1,
 789                                    int be)
 790 {
 791     DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02);
 792
 793     if (blk) {
 794         qdev_prop_set_drive(dev, "drive", blk, &error_abort);
 795     }
 796     assert(size % sector_len == 0);
 797     qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
 798     qdev_prop_set_uint32(dev, "sector-length", sector_len);
 799     qdev_prop_set_uint8(dev, "width", width);
 800     qdev_prop_set_uint8(dev, "mappings", nb_mappings);
 801     qdev_prop_set_uint8(dev, "big-endian", !!be);
 802     qdev_prop_set_uint16(dev, "id0", id0);
 803     qdev_prop_set_uint16(dev, "id1", id1);
 804     qdev_prop_set_uint16(dev, "id2", id2);
 805     qdev_prop_set_uint16(dev, "id3", id3);
 806     qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
 807     qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
 808     qdev_prop_set_string(dev, "name", name);
 809     qdev_init_nofail(dev);
 810
 811     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 812     return PFLASH_CFI02(dev);
 813 }