hw/block/pflash_cfi02.c

   1 /*
   2  *  CFI parallel flash with AMD command set emulation
   3  *
   4  *  Copyright (c) 2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /*
  21  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  22  * Supported commands/modes are:
  23  * - flash read
  24  * - flash write
  25  * - flash ID read
  26  * - sector erase
  27  * - chip erase
  28  * - unlock bypass command
  29  * - CFI queries
  30  *
  31  * It does not support flash interleaving.
  32  * It does not implement boot blocs with reduced size
  33  * It does not implement software data protection as found in many real chips
  34  * It does not implement erase suspend/resume commands
  35  * It does not implement multiple sectors erase
  36  */
  37
  38 #include "qemu/osdep.h"
  39 #include "hw/hw.h"
  40 #include "hw/block/block.h"
  41 #include "hw/block/flash.h"
  42 #include "qapi/error.h"
  43 #include "qemu/timer.h"
  44 #include "sysemu/block-backend.h"
  45 #include "qemu/host-utils.h"
  46 #include "qemu/module.h"
  47 #include "hw/sysbus.h"
  48 #include "trace.h"
  49
  50 //#define PFLASH_DEBUG
  51 #ifdef PFLASH_DEBUG
  52 #define DPRINTF(fmt, ...)                                  \
  53 do {                                                       \
  54     fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__);       \
  55 } while (0)
  56 #else
  57 #define DPRINTF(fmt, ...) do { } while (0)
  58 #endif
  59
  60 #define PFLASH_LAZY_ROMD_THRESHOLD 42
  61
  62 struct PFlashCFI02 {
  63     /*< private >*/
  64     SysBusDevice parent_obj;
  65     /*< public >*/
  66
  67     BlockBackend *blk;
  68     uint32_t sector_len;
  69     uint32_t nb_blocs;
  70     uint32_t chip_len;
  71     uint8_t mappings;
  72     uint8_t width;
  73     uint8_t be;
  74     int wcycle; /* if 0, the flash is read normally */
  75     int bypass;
  76     int ro;
  77     uint8_t cmd;
  78     uint8_t status;
  79     /* FIXME: implement array device properties */
  80     uint16_t ident0;
  81     uint16_t ident1;
  82     uint16_t ident2;
  83     uint16_t ident3;
  84     uint16_t unlock_addr0;
  85     uint16_t unlock_addr1;
  86     uint8_t cfi_table[0x52];
  87     QEMUTimer timer;
  88     /* The device replicates the flash memory across its memory space.  Emulate
  89      * that by having a container (.mem) filled with an array of aliases
  90      * (.mem_mappings) pointing to the flash memory (.orig_mem).
  91      */
  92     MemoryRegion mem;
  93     MemoryRegion *mem_mappings;    /* array; one per mapping */
  94     MemoryRegion orig_mem;
  95     int rom_mode;
  96     int read_counter; /* used for lazy switch-back to rom mode */
  97     char *name;
  98     void *storage;
  99 };
 100
 101 /*
 102  * Set up replicated mappings of the same region.
 103  */
 104 static void pflash_setup_mappings(PFlashCFI02 *pfl)
 105 {
 106     unsigned i;
 107     hwaddr size = memory_region_size(&pfl->orig_mem);
 108
 109     memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
 110     pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
 111     for (i = 0; i < pfl->mappings; ++i) {
 112         memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
 113                                  "pflash-alias", &pfl->orig_mem, 0, size);
 114         memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
 115     }
 116 }
 117
 118 static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode)
 119 {
 120     memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode);
 121     pfl->rom_mode = rom_mode;
 122 }
 123
 124 static void pflash_timer (void *opaque)
 125 {
 126     PFlashCFI02 *pfl = opaque;
 127
 128     trace_pflash_timer_expired(pfl->cmd);
 129     /* Reset flash */
 130     pfl->status ^= 0x80;
 131     if (pfl->bypass) {
 132         pfl->wcycle = 2;
 133     } else {
 134         pflash_register_memory(pfl, 1);
 135         pfl->wcycle = 0;
 136     }
 137     pfl->cmd = 0;
 138 }
 139
 140 static uint32_t pflash_read(PFlashCFI02 *pfl, hwaddr offset,
 141                             int width, int be)
 142 {
 143     hwaddr boff;
 144     uint32_t ret;
 145     uint8_t *p;
 146
 147     ret = -1;
 148     trace_pflash_read(offset, pfl->cmd, width, pfl->wcycle);
 149     /* Lazy reset to ROMD mode after a certain amount of read accesses */
 150     if (!pfl->rom_mode && pfl->wcycle == 0 &&
 151         ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
 152         pflash_register_memory(pfl, 1);
 153     }
 154     offset &= pfl->chip_len - 1;
 155     boff = offset & 0xFF;
 156     if (pfl->width == 2)
 157         boff = boff >> 1;
 158     else if (pfl->width == 4)
 159         boff = boff >> 2;
 160     switch (pfl->cmd) {
 161     default:
 162         /* This should never happen : reset state & treat it as a read*/
 163         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 164         pfl->wcycle = 0;
 165         pfl->cmd = 0;
 166         /* fall through to the read code */
 167     case 0x80:
 168         /* We accept reads during second unlock sequence... */
 169     case 0x00:
 170     flash_read:
 171         /* Flash area read */
 172         p = pfl->storage;
 173         switch (width) {
 174         case 1:
 175             ret = p[offset];
 176             trace_pflash_data_read8(offset, ret);
 177             break;
 178         case 2:
 179             if (be) {
 180                 ret = p[offset] << 8;
 181                 ret |= p[offset + 1];
 182             } else {
 183                 ret = p[offset];
 184                 ret |= p[offset + 1] << 8;
 185             }
 186             trace_pflash_data_read16(offset, ret);
 187             break;
 188         case 4:
 189             if (be) {
 190                 ret = p[offset] << 24;
 191                 ret |= p[offset + 1] << 16;
 192                 ret |= p[offset + 2] << 8;
 193                 ret |= p[offset + 3];
 194             } else {
 195                 ret = p[offset];
 196                 ret |= p[offset + 1] << 8;
 197                 ret |= p[offset + 2] << 16;
 198                 ret |= p[offset + 3] << 24;
 199             }
 200             trace_pflash_data_read32(offset, ret);
 201             break;
 202         }
 203         break;
 204     case 0x90:
 205         /* flash ID read */
 206         switch (boff) {
 207         case 0x00:
 208         case 0x01:
 209             ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
 210             break;
 211         case 0x02:
 212             ret = 0x00; /* Pretend all sectors are unprotected */
 213             break;
 214         case 0x0E:
 215         case 0x0F:
 216             ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
 217             if (ret == (uint8_t)-1) {
 218                 goto flash_read;
 219             }
 220             break;
 221         default:
 222             goto flash_read;
 223         }
 224         DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret);
 225         break;
 226     case 0xA0:
 227     case 0x10:
 228     case 0x30:
 229         /* Status register read */
 230         ret = pfl->status;
 231         DPRINTF("%s: status %x\n", __func__, ret);
 232         /* Toggle bit 6 */
 233         pfl->status ^= 0x40;
 234         break;
 235     case 0x98:
 236         /* CFI query mode */
 237         if (boff < sizeof(pfl->cfi_table)) {
 238             ret = pfl->cfi_table[boff];
 239         } else {
 240             ret = 0;
 241         }
 242         break;
 243     }
 244
 245     return ret;
 246 }
 247
 248 /* update flash content on disk */
 249 static void pflash_update(PFlashCFI02 *pfl, int offset,
 250                           int size)
 251 {
 252     int offset_end;
 253     if (pfl->blk) {
 254         offset_end = offset + size;
 255         /* widen to sector boundaries */
 256         offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
 257         offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
 258         blk_pwrite(pfl->blk, offset, pfl->storage + offset,
 259                    offset_end - offset, 0);
 260     }
 261 }
 262
 263 static void pflash_write(PFlashCFI02 *pfl, hwaddr offset,
 264                          uint32_t value, int width, int be)
 265 {
 266     hwaddr boff;
 267     uint8_t *p;
 268     uint8_t cmd;
 269
 270     cmd = value;
 271     if (pfl->cmd != 0xA0 && cmd == 0xF0) {
 272 #if 0
 273         DPRINTF("%s: flash reset asked (%02x %02x)\n",
 274                 __func__, pfl->cmd, cmd);
 275 #endif
 276         goto reset_flash;
 277     }
 278     trace_pflash_write(offset, value, width, pfl->wcycle);
 279     offset &= pfl->chip_len - 1;
 280
 281     DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__,
 282             offset, value, width);
 283     boff = offset & (pfl->sector_len - 1);
 284     if (pfl->width == 2)
 285         boff = boff >> 1;
 286     else if (pfl->width == 4)
 287         boff = boff >> 2;
 288     switch (pfl->wcycle) {
 289     case 0:
 290         /* Set the device in I/O access mode if required */
 291         if (pfl->rom_mode)
 292             pflash_register_memory(pfl, 0);
 293         pfl->read_counter = 0;
 294         /* We're in read mode */
 295     check_unlock0:
 296         if (boff == 0x55 && cmd == 0x98) {
 297         enter_CFI_mode:
 298             /* Enter CFI query mode */
 299             pfl->wcycle = 7;
 300             pfl->cmd = 0x98;
 301             return;
 302         }
 303         if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
 304             DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
 305                     __func__, boff, cmd, pfl->unlock_addr0);
 306             goto reset_flash;
 307         }
 308         DPRINTF("%s: unlock sequence started\n", __func__);
 309         break;
 310     case 1:
 311         /* We started an unlock sequence */
 312     check_unlock1:
 313         if (boff != pfl->unlock_addr1 || cmd != 0x55) {
 314             DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
 315                     boff, cmd);
 316             goto reset_flash;
 317         }
 318         DPRINTF("%s: unlock sequence done\n", __func__);
 319         break;
 320     case 2:
 321         /* We finished an unlock sequence */
 322         if (!pfl->bypass && boff != pfl->unlock_addr0) {
 323             DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
 324                     boff, cmd);
 325             goto reset_flash;
 326         }
 327         switch (cmd) {
 328         case 0x20:
 329             pfl->bypass = 1;
 330             goto do_bypass;
 331         case 0x80:
 332         case 0x90:
 333         case 0xA0:
 334             pfl->cmd = cmd;
 335             DPRINTF("%s: starting command %02x\n", __func__, cmd);
 336             break;
 337         default:
 338             DPRINTF("%s: unknown command %02x\n", __func__, cmd);
 339             goto reset_flash;
 340         }
 341         break;
 342     case 3:
 343         switch (pfl->cmd) {
 344         case 0x80:
 345             /* We need another unlock sequence */
 346             goto check_unlock0;
 347         case 0xA0:
 348             trace_pflash_data_write(offset, value, width, 0);
 349             p = pfl->storage;
 350             if (!pfl->ro) {
 351                 switch (width) {
 352                 case 1:
 353                     p[offset] &= value;
 354                     pflash_update(pfl, offset, 1);
 355                     break;
 356                 case 2:
 357                     if (be) {
 358                         p[offset] &= value >> 8;
 359                         p[offset + 1] &= value;
 360                     } else {
 361                         p[offset] &= value;
 362                         p[offset + 1] &= value >> 8;
 363                     }
 364                     pflash_update(pfl, offset, 2);
 365                     break;
 366                 case 4:
 367                     if (be) {
 368                         p[offset] &= value >> 24;
 369                         p[offset + 1] &= value >> 16;
 370                         p[offset + 2] &= value >> 8;
 371                         p[offset + 3] &= value;
 372                     } else {
 373                         p[offset] &= value;
 374                         p[offset + 1] &= value >> 8;
 375                         p[offset + 2] &= value >> 16;
 376                         p[offset + 3] &= value >> 24;
 377                     }
 378                     pflash_update(pfl, offset, 4);
 379                     break;
 380                 }
 381             }
 382             pfl->status = 0x00 | ~(value & 0x80);
 383             /* Let's pretend write is immediate */
 384             if (pfl->bypass)
 385                 goto do_bypass;
 386             goto reset_flash;
 387         case 0x90:
 388             if (pfl->bypass && cmd == 0x00) {
 389                 /* Unlock bypass reset */
 390                 goto reset_flash;
 391             }
 392             /* We can enter CFI query mode from autoselect mode */
 393             if (boff == 0x55 && cmd == 0x98)
 394                 goto enter_CFI_mode;
 395             /* No break here */
 396         default:
 397             DPRINTF("%s: invalid write for command %02x\n",
 398                     __func__, pfl->cmd);
 399             goto reset_flash;
 400         }
 401     case 4:
 402         switch (pfl->cmd) {
 403         case 0xA0:
 404             /* Ignore writes while flash data write is occurring */
 405             /* As we suppose write is immediate, this should never happen */
 406             return;
 407         case 0x80:
 408             goto check_unlock1;
 409         default:
 410             /* Should never happen */
 411             DPRINTF("%s: invalid command state %02x (wc 4)\n",
 412                     __func__, pfl->cmd);
 413             goto reset_flash;
 414         }
 415         break;
 416     case 5:
 417         switch (cmd) {
 418         case 0x10:
 419             if (boff != pfl->unlock_addr0) {
 420                 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
 421                         __func__, offset);
 422                 goto reset_flash;
 423             }
 424             /* Chip erase */
 425             DPRINTF("%s: start chip erase\n", __func__);
 426             if (!pfl->ro) {
 427                 memset(pfl->storage, 0xFF, pfl->chip_len);
 428                 pflash_update(pfl, 0, pfl->chip_len);
 429             }
 430             pfl->status = 0x00;
 431             /* Let's wait 5 seconds before chip erase is done */
 432             timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 433                       (NANOSECONDS_PER_SECOND * 5));
 434             break;
 435         case 0x30:
 436             /* Sector erase */
 437             p = pfl->storage;
 438             offset &= ~(pfl->sector_len - 1);
 439             DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__,
 440                     offset);
 441             if (!pfl->ro) {
 442                 memset(p + offset, 0xFF, pfl->sector_len);
 443                 pflash_update(pfl, offset, pfl->sector_len);
 444             }
 445             pfl->status = 0x00;
 446             /* Let's wait 1/2 second before sector erase is done */
 447             timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 448                       (NANOSECONDS_PER_SECOND / 2));
 449             break;
 450         default:
 451             DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
 452             goto reset_flash;
 453         }
 454         pfl->cmd = cmd;
 455         break;
 456     case 6:
 457         switch (pfl->cmd) {
 458         case 0x10:
 459             /* Ignore writes during chip erase */
 460             return;
 461         case 0x30:
 462             /* Ignore writes during sector erase */
 463             return;
 464         default:
 465             /* Should never happen */
 466             DPRINTF("%s: invalid command state %02x (wc 6)\n",
 467                     __func__, pfl->cmd);
 468             goto reset_flash;
 469         }
 470         break;
 471     case 7: /* Special value for CFI queries */
 472         DPRINTF("%s: invalid write in CFI query mode\n", __func__);
 473         goto reset_flash;
 474     default:
 475         /* Should never happen */
 476         DPRINTF("%s: invalid write state (wc 7)\n",  __func__);
 477         goto reset_flash;
 478     }
 479     pfl->wcycle++;
 480
 481     return;
 482
 483     /* Reset flash */
 484  reset_flash:
 485     trace_pflash_reset();
 486     pfl->bypass = 0;
 487     pfl->wcycle = 0;
 488     pfl->cmd = 0;
 489     return;
 490
 491  do_bypass:
 492     pfl->wcycle = 2;
 493     pfl->cmd = 0;
 494 }
 495
 496 static uint64_t pflash_be_readfn(void *opaque, hwaddr addr, unsigned size)
 497 {
 498     return pflash_read(opaque, addr, size, 1);
 499 }
 500
 501 static void pflash_be_writefn(void *opaque, hwaddr addr,
 502                               uint64_t value, unsigned size)
 503 {
 504     pflash_write(opaque, addr, value, size, 1);
 505 }
 506
 507 static uint64_t pflash_le_readfn(void *opaque, hwaddr addr, unsigned size)
 508 {
 509     return pflash_read(opaque, addr, size, 0);
 510 }
 511
 512 static void pflash_le_writefn(void *opaque, hwaddr addr,
 513                               uint64_t value, unsigned size)
 514 {
 515     pflash_write(opaque, addr, value, size, 0);
 516 }
 517
 518 static const MemoryRegionOps pflash_cfi02_ops_be = {
 519     .read = pflash_be_readfn,
 520     .write = pflash_be_writefn,
 521     .valid.min_access_size = 1,
 522     .valid.max_access_size = 4,
 523     .endianness = DEVICE_NATIVE_ENDIAN,
 524 };
 525
 526 static const MemoryRegionOps pflash_cfi02_ops_le = {
 527     .read = pflash_le_readfn,
 528     .write = pflash_le_writefn,
 529     .valid.min_access_size = 1,
 530     .valid.max_access_size = 4,
 531     .endianness = DEVICE_NATIVE_ENDIAN,
 532 };
 533
 534 static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
 535 {
 536     PFlashCFI02 *pfl = PFLASH_CFI02(dev);
 537     uint32_t chip_len;
 538     int ret;
 539     Error *local_err = NULL;
 540
 541     if (pfl->sector_len == 0) {
 542         error_setg(errp, "attribute \"sector-length\" not specified or zero.");
 543         return;
 544     }
 545     if (pfl->nb_blocs == 0) {
 546         error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
 547         return;
 548     }
 549     if (pfl->name == NULL) {
 550         error_setg(errp, "attribute \"name\" not specified.");
 551         return;
 552     }
 553
 554     chip_len = pfl->sector_len * pfl->nb_blocs;
 555
 556     memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), pfl->be ?
 557                                   &pflash_cfi02_ops_be : &pflash_cfi02_ops_le,
 558                                   pfl, pfl->name, chip_len, &local_err);
 559     if (local_err) {
 560         error_propagate(errp, local_err);
 561         return;
 562     }
 563
 564     pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
 565     pfl->chip_len = chip_len;
 566
 567     if (pfl->blk) {
 568         uint64_t perm;
 569         pfl->ro = blk_is_read_only(pfl->blk);
 570         perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
 571         ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
 572         if (ret < 0) {
 573             return;
 574         }
 575     } else {
 576         pfl->ro = 0;
 577     }
 578
 579     if (pfl->blk) {
 580         if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, chip_len,
 581                                          errp)) {
 582             vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
 583             return;
 584         }
 585     }
 586
 587     pflash_setup_mappings(pfl);
 588     pfl->rom_mode = 1;
 589     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
 590
 591     timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
 592     pfl->wcycle = 0;
 593     pfl->cmd = 0;
 594     pfl->status = 0;
 595     /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
 596     /* Standard "QRY" string */
 597     pfl->cfi_table[0x10] = 'Q';
 598     pfl->cfi_table[0x11] = 'R';
 599     pfl->cfi_table[0x12] = 'Y';
 600     /* Command set (AMD/Fujitsu) */
 601     pfl->cfi_table[0x13] = 0x02;
 602     pfl->cfi_table[0x14] = 0x00;
 603     /* Primary extended table address */
 604     pfl->cfi_table[0x15] = 0x31;
 605     pfl->cfi_table[0x16] = 0x00;
 606     /* Alternate command set (none) */
 607     pfl->cfi_table[0x17] = 0x00;
 608     pfl->cfi_table[0x18] = 0x00;
 609     /* Alternate extended table (none) */
 610     pfl->cfi_table[0x19] = 0x00;
 611     pfl->cfi_table[0x1A] = 0x00;
 612     /* Vcc min */
 613     pfl->cfi_table[0x1B] = 0x27;
 614     /* Vcc max */
 615     pfl->cfi_table[0x1C] = 0x36;
 616     /* Vpp min (no Vpp pin) */
 617     pfl->cfi_table[0x1D] = 0x00;
 618     /* Vpp max (no Vpp pin) */
 619     pfl->cfi_table[0x1E] = 0x00;
 620     /* Reserved */
 621     pfl->cfi_table[0x1F] = 0x07;
 622     /* Timeout for min size buffer write (NA) */
 623     pfl->cfi_table[0x20] = 0x00;
 624     /* Typical timeout for block erase (512 ms) */
 625     pfl->cfi_table[0x21] = 0x09;
 626     /* Typical timeout for full chip erase (4096 ms) */
 627     pfl->cfi_table[0x22] = 0x0C;
 628     /* Reserved */
 629     pfl->cfi_table[0x23] = 0x01;
 630     /* Max timeout for buffer write (NA) */
 631     pfl->cfi_table[0x24] = 0x00;
 632     /* Max timeout for block erase */
 633     pfl->cfi_table[0x25] = 0x0A;
 634     /* Max timeout for chip erase */
 635     pfl->cfi_table[0x26] = 0x0D;
 636     /* Device size */
 637     pfl->cfi_table[0x27] = ctz32(chip_len);
 638     /* Flash device interface (8 & 16 bits) */
 639     pfl->cfi_table[0x28] = 0x02;
 640     pfl->cfi_table[0x29] = 0x00;
 641     /* Max number of bytes in multi-bytes write */
 642     /* XXX: disable buffered write as it's not supported */
 643     //    pfl->cfi_table[0x2A] = 0x05;
 644     pfl->cfi_table[0x2A] = 0x00;
 645     pfl->cfi_table[0x2B] = 0x00;
 646     /* Number of erase block regions (uniform) */
 647     pfl->cfi_table[0x2C] = 0x01;
 648     /* Erase block region 1 */
 649     pfl->cfi_table[0x2D] = pfl->nb_blocs - 1;
 650     pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8;
 651     pfl->cfi_table[0x2F] = pfl->sector_len >> 8;
 652     pfl->cfi_table[0x30] = pfl->sector_len >> 16;
 653
 654     /* Extended */
 655     pfl->cfi_table[0x31] = 'P';
 656     pfl->cfi_table[0x32] = 'R';
 657     pfl->cfi_table[0x33] = 'I';
 658
 659     pfl->cfi_table[0x34] = '1';
 660     pfl->cfi_table[0x35] = '0';
 661
 662     pfl->cfi_table[0x36] = 0x00;
 663     pfl->cfi_table[0x37] = 0x00;
 664     pfl->cfi_table[0x38] = 0x00;
 665     pfl->cfi_table[0x39] = 0x00;
 666
 667     pfl->cfi_table[0x3a] = 0x00;
 668
 669     pfl->cfi_table[0x3b] = 0x00;
 670     pfl->cfi_table[0x3c] = 0x00;
 671 }
 672
 673 static Property pflash_cfi02_properties[] = {
 674     DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk),
 675     DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, nb_blocs, 0),
 676     DEFINE_PROP_UINT32("sector-length", PFlashCFI02, sector_len, 0),
 677     DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0),
 678     DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0),
 679     DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0),
 680     DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0),
 681     DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0),
 682     DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0),
 683     DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0),
 684     DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0),
 685     DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0),
 686     DEFINE_PROP_STRING("name", PFlashCFI02, name),
 687     DEFINE_PROP_END_OF_LIST(),
 688 };
 689
 690 static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp)
 691 {
 692     PFlashCFI02 *pfl = PFLASH_CFI02(dev);
 693     timer_del(&pfl->timer);
 694 }
 695
 696 static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
 697 {
 698     DeviceClass *dc = DEVICE_CLASS(klass);
 699
 700     dc->realize = pflash_cfi02_realize;
 701     dc->unrealize = pflash_cfi02_unrealize;
 702     dc->props = pflash_cfi02_properties;
 703     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 704 }
 705
 706 static const TypeInfo pflash_cfi02_info = {
 707     .name           = TYPE_PFLASH_CFI02,
 708     .parent         = TYPE_SYS_BUS_DEVICE,
 709     .instance_size  = sizeof(PFlashCFI02),
 710     .class_init     = pflash_cfi02_class_init,
 711 };
 712
 713 static void pflash_cfi02_register_types(void)
 714 {
 715     type_register_static(&pflash_cfi02_info);
 716 }
 717
 718 type_init(pflash_cfi02_register_types)
 719
 720 PFlashCFI02 *pflash_cfi02_register(hwaddr base,
 721                                    const char *name,
 722                                    hwaddr size,
 723                                    BlockBackend *blk,
 724                                    uint32_t sector_len,
 725                                    int nb_mappings, int width,
 726                                    uint16_t id0, uint16_t id1,
 727                                    uint16_t id2, uint16_t id3,
 728                                    uint16_t unlock_addr0,
 729                                    uint16_t unlock_addr1,
 730                                    int be)
 731 {
 732     DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02);
 733
 734     if (blk) {
 735         qdev_prop_set_drive(dev, "drive", blk, &error_abort);
 736     }
 737     assert(size % sector_len == 0);
 738     qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
 739     qdev_prop_set_uint32(dev, "sector-length", sector_len);
 740     qdev_prop_set_uint8(dev, "width", width);
 741     qdev_prop_set_uint8(dev, "mappings", nb_mappings);
 742     qdev_prop_set_uint8(dev, "big-endian", !!be);
 743     qdev_prop_set_uint16(dev, "id0", id0);
 744     qdev_prop_set_uint16(dev, "id1", id1);
 745     qdev_prop_set_uint16(dev, "id2", id2);
 746     qdev_prop_set_uint16(dev, "id3", id3);
 747     qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
 748     qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
 749     qdev_prop_set_string(dev, "name", name);
 750     qdev_init_nofail(dev);
 751
 752     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 753     return PFLASH_CFI02(dev);
 754 }