hw/block/pflash_cfi02.c

   1 /*
   2  *  CFI parallel flash with AMD command set emulation
   3  *
   4  *  Copyright (c) 2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /*
  21  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  22  * Supported commands/modes are:
  23  * - flash read
  24  * - flash write
  25  * - flash ID read
  26  * - sector erase
  27  * - chip erase
  28  * - unlock bypass command
  29  * - CFI queries
  30  *
  31  * It does not support flash interleaving.
  32  * It does not implement boot blocs with reduced size
  33  * It does not implement software data protection as found in many real chips
  34  * It does not implement erase suspend/resume commands
  35  * It does not implement multiple sectors erase
  36  */
  37
  38 #include "qemu/osdep.h"
  39 #include "hw/hw.h"
  40 #include "hw/block/block.h"
  41 #include "hw/block/flash.h"
  42 #include "qapi/error.h"
  43 #include "qemu/timer.h"
  44 #include "sysemu/block-backend.h"
  45 #include "qemu/host-utils.h"
  46 #include "qemu/module.h"
  47 #include "hw/sysbus.h"
  48 #include "trace.h"
  49
  50 #define PFLASH_DEBUG false
  51 #define DPRINTF(fmt, ...)                                  \
  52 do {                                                       \
  53     if (PFLASH_DEBUG) {                                    \
  54         fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__);   \
  55     }                                                      \
  56 } while (0)
  57
  58 #define PFLASH_LAZY_ROMD_THRESHOLD 42
  59
  60 /* Special write cycles for CFI queries. */
  61 enum {
  62     WCYCLE_CFI              = 7,
  63 };
  64
  65 struct PFlashCFI02 {
  66     /*< private >*/
  67     SysBusDevice parent_obj;
  68     /*< public >*/
  69
  70     BlockBackend *blk;
  71     uint32_t sector_len;
  72     uint32_t nb_blocs;
  73     uint32_t chip_len;
  74     uint8_t mappings;
  75     uint8_t width;
  76     uint8_t be;
  77     int wcycle; /* if 0, the flash is read normally */
  78     int bypass;
  79     int ro;
  80     uint8_t cmd;
  81     uint8_t status;
  82     /* FIXME: implement array device properties */
  83     uint16_t ident0;
  84     uint16_t ident1;
  85     uint16_t ident2;
  86     uint16_t ident3;
  87     uint16_t unlock_addr0;
  88     uint16_t unlock_addr1;
  89     uint8_t cfi_table[0x52];
  90     QEMUTimer timer;
  91     /* The device replicates the flash memory across its memory space.  Emulate
  92      * that by having a container (.mem) filled with an array of aliases
  93      * (.mem_mappings) pointing to the flash memory (.orig_mem).
  94      */
  95     MemoryRegion mem;
  96     MemoryRegion *mem_mappings;    /* array; one per mapping */
  97     MemoryRegion orig_mem;
  98     int rom_mode;
  99     int read_counter; /* used for lazy switch-back to rom mode */
 100     char *name;
 101     void *storage;
 102 };
 103
 104 /*
 105  * Toggle status bit DQ7.
 106  */
 107 static inline void toggle_dq7(PFlashCFI02 *pfl)
 108 {
 109     pfl->status ^= 0x80;
 110 }
 111
 112 /*
 113  * Set status bit DQ7 to bit 7 of value.
 114  */
 115 static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value)
 116 {
 117     pfl->status &= 0x7F;
 118     pfl->status |= value & 0x80;
 119 }
 120
 121 /*
 122  * Toggle status bit DQ6.
 123  */
 124 static inline void toggle_dq6(PFlashCFI02 *pfl)
 125 {
 126     pfl->status ^= 0x40;
 127 }
 128
 129 /*
 130  * Set up replicated mappings of the same region.
 131  */
 132 static void pflash_setup_mappings(PFlashCFI02 *pfl)
 133 {
 134     unsigned i;
 135     hwaddr size = memory_region_size(&pfl->orig_mem);
 136
 137     memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
 138     pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
 139     for (i = 0; i < pfl->mappings; ++i) {
 140         memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
 141                                  "pflash-alias", &pfl->orig_mem, 0, size);
 142         memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
 143     }
 144 }
 145
 146 static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode)
 147 {
 148     memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode);
 149     pfl->rom_mode = rom_mode;
 150 }
 151
 152 static void pflash_timer (void *opaque)
 153 {
 154     PFlashCFI02 *pfl = opaque;
 155
 156     trace_pflash_timer_expired(pfl->cmd);
 157     /* Reset flash */
 158     toggle_dq7(pfl);
 159     if (pfl->bypass) {
 160         pfl->wcycle = 2;
 161     } else {
 162         pflash_register_memory(pfl, 1);
 163         pfl->wcycle = 0;
 164     }
 165     pfl->cmd = 0;
 166 }
 167
 168 /*
 169  * Read data from flash.
 170  */
 171 static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset,
 172                                  unsigned int width)
 173 {
 174     uint8_t *p = (uint8_t *)pfl->storage + offset;
 175     uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width);
 176     trace_pflash_data_read(offset, width << 1, ret);
 177     return ret;
 178 }
 179
 180 static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
 181 {
 182     PFlashCFI02 *pfl = opaque;
 183     hwaddr boff;
 184     uint64_t ret;
 185
 186     ret = -1;
 187     /* Lazy reset to ROMD mode after a certain amount of read accesses */
 188     if (!pfl->rom_mode && pfl->wcycle == 0 &&
 189         ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
 190         pflash_register_memory(pfl, 1);
 191     }
 192     offset &= pfl->chip_len - 1;
 193     boff = offset & 0xFF;
 194     if (pfl->width == 2)
 195         boff = boff >> 1;
 196     else if (pfl->width == 4)
 197         boff = boff >> 2;
 198     switch (pfl->cmd) {
 199     default:
 200         /* This should never happen : reset state & treat it as a read*/
 201         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 202         pfl->wcycle = 0;
 203         pfl->cmd = 0;
 204         /* fall through to the read code */
 205     case 0x80:
 206         /* We accept reads during second unlock sequence... */
 207     case 0x00:
 208         /* Flash area read */
 209         ret = pflash_data_read(pfl, offset, width);
 210         break;
 211     case 0x90:
 212         /* flash ID read */
 213         switch (boff) {
 214         case 0x00:
 215         case 0x01:
 216             ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
 217             break;
 218         case 0x02:
 219             ret = 0x00; /* Pretend all sectors are unprotected */
 220             break;
 221         case 0x0E:
 222         case 0x0F:
 223             ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
 224             if (ret != (uint8_t)-1) {
 225                 break;
 226             }
 227             /* Fall through to data read. */
 228         default:
 229             ret = pflash_data_read(pfl, offset, width);
 230         }
 231         DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff, ret);
 232         break;
 233     case 0xA0:
 234     case 0x10:
 235     case 0x30:
 236         /* Status register read */
 237         ret = pfl->status;
 238         DPRINTF("%s: status %" PRIx64 "\n", __func__, ret);
 239         toggle_dq6(pfl);
 240         break;
 241     case 0x98:
 242         /* CFI query mode */
 243         if (boff < sizeof(pfl->cfi_table)) {
 244             ret = pfl->cfi_table[boff];
 245         } else {
 246             ret = 0;
 247         }
 248         break;
 249     }
 250     trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle);
 251
 252     return ret;
 253 }
 254
 255 /* update flash content on disk */
 256 static void pflash_update(PFlashCFI02 *pfl, int offset, int size)
 257 {
 258     int offset_end;
 259     if (pfl->blk) {
 260         offset_end = offset + size;
 261         /* widen to sector boundaries */
 262         offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
 263         offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
 264         blk_pwrite(pfl->blk, offset, pfl->storage + offset,
 265                    offset_end - offset, 0);
 266     }
 267 }
 268
 269 static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
 270                          unsigned int width)
 271 {
 272     PFlashCFI02 *pfl = opaque;
 273     hwaddr boff;
 274     uint8_t *p;
 275     uint8_t cmd;
 276
 277     trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle);
 278     cmd = value;
 279     if (pfl->cmd != 0xA0 && cmd == 0xF0) {
 280         goto reset_flash;
 281     }
 282     offset &= pfl->chip_len - 1;
 283
 284     boff = offset;
 285     if (pfl->width == 2)
 286         boff = boff >> 1;
 287     else if (pfl->width == 4)
 288         boff = boff >> 2;
 289     /* Only the least-significant 11 bits are used in most cases. */
 290     boff &= 0x7FF;
 291     switch (pfl->wcycle) {
 292     case 0:
 293         /* Set the device in I/O access mode if required */
 294         if (pfl->rom_mode)
 295             pflash_register_memory(pfl, 0);
 296         pfl->read_counter = 0;
 297         /* We're in read mode */
 298     check_unlock0:
 299         if (boff == 0x55 && cmd == 0x98) {
 300         enter_CFI_mode:
 301             /* Enter CFI query mode */
 302             pfl->wcycle = WCYCLE_CFI;
 303             pfl->cmd = 0x98;
 304             return;
 305         }
 306         if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
 307             DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
 308                     __func__, boff, cmd, pfl->unlock_addr0);
 309             goto reset_flash;
 310         }
 311         DPRINTF("%s: unlock sequence started\n", __func__);
 312         break;
 313     case 1:
 314         /* We started an unlock sequence */
 315     check_unlock1:
 316         if (boff != pfl->unlock_addr1 || cmd != 0x55) {
 317             DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
 318                     boff, cmd);
 319             goto reset_flash;
 320         }
 321         DPRINTF("%s: unlock sequence done\n", __func__);
 322         break;
 323     case 2:
 324         /* We finished an unlock sequence */
 325         if (!pfl->bypass && boff != pfl->unlock_addr0) {
 326             DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
 327                     boff, cmd);
 328             goto reset_flash;
 329         }
 330         switch (cmd) {
 331         case 0x20:
 332             pfl->bypass = 1;
 333             goto do_bypass;
 334         case 0x80:
 335         case 0x90:
 336         case 0xA0:
 337             pfl->cmd = cmd;
 338             DPRINTF("%s: starting command %02x\n", __func__, cmd);
 339             break;
 340         default:
 341             DPRINTF("%s: unknown command %02x\n", __func__, cmd);
 342             goto reset_flash;
 343         }
 344         break;
 345     case 3:
 346         switch (pfl->cmd) {
 347         case 0x80:
 348             /* We need another unlock sequence */
 349             goto check_unlock0;
 350         case 0xA0:
 351             trace_pflash_data_write(offset, width << 1, value, 0);
 352             if (!pfl->ro) {
 353                 p = (uint8_t *)pfl->storage + offset;
 354                 if (pfl->be) {
 355                     uint64_t current = ldn_be_p(p, width);
 356                     stn_be_p(p, width, current & value);
 357                 } else {
 358                     uint64_t current = ldn_le_p(p, width);
 359                     stn_le_p(p, width, current & value);
 360                 }
 361                 pflash_update(pfl, offset, width);
 362             }
 363             /*
 364              * While programming, status bit DQ7 should hold the opposite
 365              * value from how it was programmed.
 366              */
 367             set_dq7(pfl, ~value);
 368             /* Let's pretend write is immediate */
 369             if (pfl->bypass)
 370                 goto do_bypass;
 371             goto reset_flash;
 372         case 0x90:
 373             if (pfl->bypass && cmd == 0x00) {
 374                 /* Unlock bypass reset */
 375                 goto reset_flash;
 376             }
 377             /* We can enter CFI query mode from autoselect mode */
 378             if (boff == 0x55 && cmd == 0x98)
 379                 goto enter_CFI_mode;
 380             /* No break here */
 381         default:
 382             DPRINTF("%s: invalid write for command %02x\n",
 383                     __func__, pfl->cmd);
 384             goto reset_flash;
 385         }
 386     case 4:
 387         switch (pfl->cmd) {
 388         case 0xA0:
 389             /* Ignore writes while flash data write is occurring */
 390             /* As we suppose write is immediate, this should never happen */
 391             return;
 392         case 0x80:
 393             goto check_unlock1;
 394         default:
 395             /* Should never happen */
 396             DPRINTF("%s: invalid command state %02x (wc 4)\n",
 397                     __func__, pfl->cmd);
 398             goto reset_flash;
 399         }
 400         break;
 401     case 5:
 402         switch (cmd) {
 403         case 0x10:
 404             if (boff != pfl->unlock_addr0) {
 405                 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
 406                         __func__, offset);
 407                 goto reset_flash;
 408             }
 409             /* Chip erase */
 410             DPRINTF("%s: start chip erase\n", __func__);
 411             if (!pfl->ro) {
 412                 memset(pfl->storage, 0xFF, pfl->chip_len);
 413                 pflash_update(pfl, 0, pfl->chip_len);
 414             }
 415             set_dq7(pfl, 0x00);
 416             /* Let's wait 5 seconds before chip erase is done */
 417             timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 418                       (NANOSECONDS_PER_SECOND * 5));
 419             break;
 420         case 0x30:
 421             /* Sector erase */
 422             p = pfl->storage;
 423             offset &= ~(pfl->sector_len - 1);
 424             DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__,
 425                     offset);
 426             if (!pfl->ro) {
 427                 memset(p + offset, 0xFF, pfl->sector_len);
 428                 pflash_update(pfl, offset, pfl->sector_len);
 429             }
 430             set_dq7(pfl, 0x00);
 431             /* Let's wait 1/2 second before sector erase is done */
 432             timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 433                       (NANOSECONDS_PER_SECOND / 2));
 434             break;
 435         default:
 436             DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
 437             goto reset_flash;
 438         }
 439         pfl->cmd = cmd;
 440         break;
 441     case 6:
 442         switch (pfl->cmd) {
 443         case 0x10:
 444             /* Ignore writes during chip erase */
 445             return;
 446         case 0x30:
 447             /* Ignore writes during sector erase */
 448             return;
 449         default:
 450             /* Should never happen */
 451             DPRINTF("%s: invalid command state %02x (wc 6)\n",
 452                     __func__, pfl->cmd);
 453             goto reset_flash;
 454         }
 455         break;
 456     /* Special values for CFI queries */
 457     case WCYCLE_CFI:
 458         DPRINTF("%s: invalid write in CFI query mode\n", __func__);
 459         goto reset_flash;
 460     default:
 461         /* Should never happen */
 462         DPRINTF("%s: invalid write state (wc 7)\n",  __func__);
 463         goto reset_flash;
 464     }
 465     pfl->wcycle++;
 466
 467     return;
 468
 469     /* Reset flash */
 470  reset_flash:
 471     trace_pflash_reset();
 472     pfl->bypass = 0;
 473     pfl->wcycle = 0;
 474     pfl->cmd = 0;
 475     return;
 476
 477  do_bypass:
 478     pfl->wcycle = 2;
 479     pfl->cmd = 0;
 480 }
 481
 482 static const MemoryRegionOps pflash_cfi02_ops = {
 483     .read = pflash_read,
 484     .write = pflash_write,
 485     .valid.min_access_size = 1,
 486     .valid.max_access_size = 4,
 487     .endianness = DEVICE_NATIVE_ENDIAN,
 488 };
 489
 490 static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
 491 {
 492     PFlashCFI02 *pfl = PFLASH_CFI02(dev);
 493     uint32_t chip_len;
 494     int ret;
 495     Error *local_err = NULL;
 496
 497     if (pfl->sector_len == 0) {
 498         error_setg(errp, "attribute \"sector-length\" not specified or zero.");
 499         return;
 500     }
 501     if (pfl->nb_blocs == 0) {
 502         error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
 503         return;
 504     }
 505     if (pfl->name == NULL) {
 506         error_setg(errp, "attribute \"name\" not specified.");
 507         return;
 508     }
 509
 510     chip_len = pfl->sector_len * pfl->nb_blocs;
 511
 512     memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl),
 513                                   &pflash_cfi02_ops, pfl, pfl->name,
 514                                   chip_len, &local_err);
 515     if (local_err) {
 516         error_propagate(errp, local_err);
 517         return;
 518     }
 519
 520     pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
 521     pfl->chip_len = chip_len;
 522
 523     if (pfl->blk) {
 524         uint64_t perm;
 525         pfl->ro = blk_is_read_only(pfl->blk);
 526         perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
 527         ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
 528         if (ret < 0) {
 529             return;
 530         }
 531     } else {
 532         pfl->ro = 0;
 533     }
 534
 535     if (pfl->blk) {
 536         if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, chip_len,
 537                                          errp)) {
 538             vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
 539             return;
 540         }
 541     }
 542
 543     /* Only 11 bits are used in the comparison. */
 544     pfl->unlock_addr0 &= 0x7FF;
 545     pfl->unlock_addr1 &= 0x7FF;
 546
 547     pflash_setup_mappings(pfl);
 548     pfl->rom_mode = 1;
 549     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
 550
 551     timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
 552     pfl->wcycle = 0;
 553     pfl->cmd = 0;
 554     pfl->status = 0;
 555     /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
 556     /* Standard "QRY" string */
 557     pfl->cfi_table[0x10] = 'Q';
 558     pfl->cfi_table[0x11] = 'R';
 559     pfl->cfi_table[0x12] = 'Y';
 560     /* Command set (AMD/Fujitsu) */
 561     pfl->cfi_table[0x13] = 0x02;
 562     pfl->cfi_table[0x14] = 0x00;
 563     /* Primary extended table address */
 564     pfl->cfi_table[0x15] = 0x31;
 565     pfl->cfi_table[0x16] = 0x00;
 566     /* Alternate command set (none) */
 567     pfl->cfi_table[0x17] = 0x00;
 568     pfl->cfi_table[0x18] = 0x00;
 569     /* Alternate extended table (none) */
 570     pfl->cfi_table[0x19] = 0x00;
 571     pfl->cfi_table[0x1A] = 0x00;
 572     /* Vcc min */
 573     pfl->cfi_table[0x1B] = 0x27;
 574     /* Vcc max */
 575     pfl->cfi_table[0x1C] = 0x36;
 576     /* Vpp min (no Vpp pin) */
 577     pfl->cfi_table[0x1D] = 0x00;
 578     /* Vpp max (no Vpp pin) */
 579     pfl->cfi_table[0x1E] = 0x00;
 580     /* Reserved */
 581     pfl->cfi_table[0x1F] = 0x07;
 582     /* Timeout for min size buffer write (NA) */
 583     pfl->cfi_table[0x20] = 0x00;
 584     /* Typical timeout for block erase (512 ms) */
 585     pfl->cfi_table[0x21] = 0x09;
 586     /* Typical timeout for full chip erase (4096 ms) */
 587     pfl->cfi_table[0x22] = 0x0C;
 588     /* Reserved */
 589     pfl->cfi_table[0x23] = 0x01;
 590     /* Max timeout for buffer write (NA) */
 591     pfl->cfi_table[0x24] = 0x00;
 592     /* Max timeout for block erase */
 593     pfl->cfi_table[0x25] = 0x0A;
 594     /* Max timeout for chip erase */
 595     pfl->cfi_table[0x26] = 0x0D;
 596     /* Device size */
 597     pfl->cfi_table[0x27] = ctz32(chip_len);
 598     /* Flash device interface (8 & 16 bits) */
 599     pfl->cfi_table[0x28] = 0x02;
 600     pfl->cfi_table[0x29] = 0x00;
 601     /* Max number of bytes in multi-bytes write */
 602     /* XXX: disable buffered write as it's not supported */
 603     //    pfl->cfi_table[0x2A] = 0x05;
 604     pfl->cfi_table[0x2A] = 0x00;
 605     pfl->cfi_table[0x2B] = 0x00;
 606     /* Number of erase block regions (uniform) */
 607     pfl->cfi_table[0x2C] = 0x01;
 608     /* Erase block region 1 */
 609     pfl->cfi_table[0x2D] = pfl->nb_blocs - 1;
 610     pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8;
 611     pfl->cfi_table[0x2F] = pfl->sector_len >> 8;
 612     pfl->cfi_table[0x30] = pfl->sector_len >> 16;
 613
 614     /* Extended */
 615     pfl->cfi_table[0x31] = 'P';
 616     pfl->cfi_table[0x32] = 'R';
 617     pfl->cfi_table[0x33] = 'I';
 618
 619     pfl->cfi_table[0x34] = '1';
 620     pfl->cfi_table[0x35] = '0';
 621
 622     pfl->cfi_table[0x36] = 0x00;
 623     pfl->cfi_table[0x37] = 0x00;
 624     pfl->cfi_table[0x38] = 0x00;
 625     pfl->cfi_table[0x39] = 0x00;
 626
 627     pfl->cfi_table[0x3a] = 0x00;
 628
 629     pfl->cfi_table[0x3b] = 0x00;
 630     pfl->cfi_table[0x3c] = 0x00;
 631 }
 632
 633 static Property pflash_cfi02_properties[] = {
 634     DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk),
 635     DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, nb_blocs, 0),
 636     DEFINE_PROP_UINT32("sector-length", PFlashCFI02, sector_len, 0),
 637     DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0),
 638     DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0),
 639     DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0),
 640     DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0),
 641     DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0),
 642     DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0),
 643     DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0),
 644     DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0),
 645     DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0),
 646     DEFINE_PROP_STRING("name", PFlashCFI02, name),
 647     DEFINE_PROP_END_OF_LIST(),
 648 };
 649
 650 static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp)
 651 {
 652     PFlashCFI02 *pfl = PFLASH_CFI02(dev);
 653     timer_del(&pfl->timer);
 654 }
 655
 656 static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
 657 {
 658     DeviceClass *dc = DEVICE_CLASS(klass);
 659
 660     dc->realize = pflash_cfi02_realize;
 661     dc->unrealize = pflash_cfi02_unrealize;
 662     dc->props = pflash_cfi02_properties;
 663     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 664 }
 665
 666 static const TypeInfo pflash_cfi02_info = {
 667     .name           = TYPE_PFLASH_CFI02,
 668     .parent         = TYPE_SYS_BUS_DEVICE,
 669     .instance_size  = sizeof(PFlashCFI02),
 670     .class_init     = pflash_cfi02_class_init,
 671 };
 672
 673 static void pflash_cfi02_register_types(void)
 674 {
 675     type_register_static(&pflash_cfi02_info);
 676 }
 677
 678 type_init(pflash_cfi02_register_types)
 679
 680 PFlashCFI02 *pflash_cfi02_register(hwaddr base,
 681                                    const char *name,
 682                                    hwaddr size,
 683                                    BlockBackend *blk,
 684                                    uint32_t sector_len,
 685                                    int nb_mappings, int width,
 686                                    uint16_t id0, uint16_t id1,
 687                                    uint16_t id2, uint16_t id3,
 688                                    uint16_t unlock_addr0,
 689                                    uint16_t unlock_addr1,
 690                                    int be)
 691 {
 692     DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02);
 693
 694     if (blk) {
 695         qdev_prop_set_drive(dev, "drive", blk, &error_abort);
 696     }
 697     assert(size % sector_len == 0);
 698     qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
 699     qdev_prop_set_uint32(dev, "sector-length", sector_len);
 700     qdev_prop_set_uint8(dev, "width", width);
 701     qdev_prop_set_uint8(dev, "mappings", nb_mappings);
 702     qdev_prop_set_uint8(dev, "big-endian", !!be);
 703     qdev_prop_set_uint16(dev, "id0", id0);
 704     qdev_prop_set_uint16(dev, "id1", id1);
 705     qdev_prop_set_uint16(dev, "id2", id2);
 706     qdev_prop_set_uint16(dev, "id3", id3);
 707     qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
 708     qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
 709     qdev_prop_set_string(dev, "name", name);
 710     qdev_init_nofail(dev);
 711
 712     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 713     return PFLASH_CFI02(dev);
 714 }