hw/block/pflash_cfi02.c

   1 /*
   2  *  CFI parallel flash with AMD command set emulation
   3  *
   4  *  Copyright (c) 2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /*
  21  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  22  * Supported commands/modes are:
  23  * - flash read
  24  * - flash write
  25  * - flash ID read
  26  * - sector erase
  27  * - chip erase
  28  * - unlock bypass command
  29  * - CFI queries
  30  *
  31  * It does not support flash interleaving.
  32  * It does not implement software data protection as found in many real chips
  33  * It does not implement erase suspend/resume commands
  34  */
  35
  36 #include "qemu/osdep.h"
  37 #include "hw/hw.h"
  38 #include "hw/block/block.h"
  39 #include "hw/block/flash.h"
  40 #include "qapi/error.h"
  41 #include "qemu/timer.h"
  42 #include "sysemu/block-backend.h"
  43 #include "qemu/host-utils.h"
  44 #include "qemu/module.h"
  45 #include "hw/sysbus.h"
  46 #include "trace.h"
  47
  48 #define PFLASH_DEBUG false
  49 #define DPRINTF(fmt, ...)                                  \
  50 do {                                                       \
  51     if (PFLASH_DEBUG) {                                    \
  52         fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__);   \
  53     }                                                      \
  54 } while (0)
  55
  56 #define PFLASH_LAZY_ROMD_THRESHOLD 42
  57
  58 /*
  59  * The size of the cfi_table indirectly depends on this and the start of the
  60  * PRI table directly depends on it. 4 is the maximum size (and also what
  61  * seems common) without changing the PRT table address.
  62  */
  63 #define PFLASH_MAX_ERASE_REGIONS 4
  64
  65 /* Special write cycles for CFI queries. */
  66 enum {
  67     WCYCLE_CFI              = 7,
  68     WCYCLE_AUTOSELECT_CFI   = 8,
  69 };
  70
  71 struct PFlashCFI02 {
  72     /*< private >*/
  73     SysBusDevice parent_obj;
  74     /*< public >*/
  75
  76     BlockBackend *blk;
  77     uint32_t uniform_nb_blocs;
  78     uint32_t uniform_sector_len;
  79     uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS];
  80     uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS];
  81     uint32_t chip_len;
  82     uint8_t mappings;
  83     uint8_t width;
  84     uint8_t be;
  85     int wcycle; /* if 0, the flash is read normally */
  86     int bypass;
  87     int ro;
  88     uint8_t cmd;
  89     uint8_t status;
  90     /* FIXME: implement array device properties */
  91     uint16_t ident0;
  92     uint16_t ident1;
  93     uint16_t ident2;
  94     uint16_t ident3;
  95     uint16_t unlock_addr0;
  96     uint16_t unlock_addr1;
  97     uint8_t cfi_table[0x4d];
  98     QEMUTimer timer;
  99     /* The device replicates the flash memory across its memory space.  Emulate
 100      * that by having a container (.mem) filled with an array of aliases
 101      * (.mem_mappings) pointing to the flash memory (.orig_mem).
 102      */
 103     MemoryRegion mem;
 104     MemoryRegion *mem_mappings;    /* array; one per mapping */
 105     MemoryRegion orig_mem;
 106     int rom_mode;
 107     int read_counter; /* used for lazy switch-back to rom mode */
 108     int sectors_to_erase;
 109     char *name;
 110     void *storage;
 111 };
 112
 113 /*
 114  * Toggle status bit DQ7.
 115  */
 116 static inline void toggle_dq7(PFlashCFI02 *pfl)
 117 {
 118     pfl->status ^= 0x80;
 119 }
 120
 121 /*
 122  * Set status bit DQ7 to bit 7 of value.
 123  */
 124 static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value)
 125 {
 126     pfl->status &= 0x7F;
 127     pfl->status |= value & 0x80;
 128 }
 129
 130 /*
 131  * Toggle status bit DQ6.
 132  */
 133 static inline void toggle_dq6(PFlashCFI02 *pfl)
 134 {
 135     pfl->status ^= 0x40;
 136 }
 137
 138 /*
 139  * Turn on DQ3.
 140  */
 141 static inline void assert_dq3(PFlashCFI02 *pfl)
 142 {
 143     pfl->status |= 0x08;
 144 }
 145
 146 /*
 147  * Turn off DQ3.
 148  */
 149 static inline void reset_dq3(PFlashCFI02 *pfl)
 150 {
 151     pfl->status &= ~0x08;
 152 }
 153
 154 /*
 155  * Set up replicated mappings of the same region.
 156  */
 157 static void pflash_setup_mappings(PFlashCFI02 *pfl)
 158 {
 159     unsigned i;
 160     hwaddr size = memory_region_size(&pfl->orig_mem);
 161
 162     memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
 163     pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
 164     for (i = 0; i < pfl->mappings; ++i) {
 165         memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
 166                                  "pflash-alias", &pfl->orig_mem, 0, size);
 167         memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
 168     }
 169 }
 170
 171 static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode)
 172 {
 173     memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode);
 174     pfl->rom_mode = rom_mode;
 175 }
 176
 177 static size_t pflash_regions_count(PFlashCFI02 *pfl)
 178 {
 179     return pfl->cfi_table[0x2c];
 180 }
 181
 182 static void pflash_timer(void *opaque)
 183 {
 184     PFlashCFI02 *pfl = opaque;
 185
 186     trace_pflash_timer_expired(pfl->cmd);
 187     if (pfl->cmd == 0x30) {
 188         /*
 189          * Sector erase. If DQ3 is 0 when the timer expires, then the 50
 190          * us erase timeout has expired so we need to start the timer for the
 191          * sector erase algorithm. Otherwise, the erase completed and we should
 192          * go back to read array mode.
 193          */
 194         if ((pfl->status & 0x08) == 0) {
 195             assert_dq3(pfl);
 196             /*
 197              * CFI address 0x21 is "Typical timeout per individual block erase
 198              * 2^N ms"
 199              */
 200             uint64_t timeout = ((1ULL << pfl->cfi_table[0x21]) *
 201                                 pfl->sectors_to_erase) * 1000000;
 202             timer_mod(&pfl->timer,
 203                       qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
 204             DPRINTF("%s: erase timeout fired; erasing %d sectors\n",
 205                     __func__, pfl->sectors_to_erase);
 206             return;
 207         }
 208         DPRINTF("%s: sector erase complete\n", __func__);
 209         pfl->sectors_to_erase = 0;
 210         reset_dq3(pfl);
 211     }
 212
 213     /* Reset flash */
 214     toggle_dq7(pfl);
 215     if (pfl->bypass) {
 216         pfl->wcycle = 2;
 217     } else {
 218         pflash_register_memory(pfl, 1);
 219         pfl->wcycle = 0;
 220     }
 221     pfl->cmd = 0;
 222 }
 223
 224 /*
 225  * Read data from flash.
 226  */
 227 static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset,
 228                                  unsigned int width)
 229 {
 230     uint8_t *p = (uint8_t *)pfl->storage + offset;
 231     uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width);
 232     trace_pflash_data_read(offset, width << 1, ret);
 233     return ret;
 234 }
 235
 236 /*
 237  * offset should be a byte offset of the QEMU device and _not_ a device
 238  * offset.
 239  */
 240 static uint32_t pflash_sector_len(PFlashCFI02 *pfl, hwaddr offset)
 241 {
 242     assert(offset < pfl->chip_len);
 243     hwaddr addr = 0;
 244     for (int i = 0; i < pflash_regions_count(pfl); ++i) {
 245         uint64_t region_size = (uint64_t)pfl->nb_blocs[i] * pfl->sector_len[i];
 246         if (addr <= offset && offset < addr + region_size) {
 247             return pfl->sector_len[i];
 248         }
 249         addr += region_size;
 250     }
 251     abort();
 252 }
 253
 254 static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
 255 {
 256     PFlashCFI02 *pfl = opaque;
 257     hwaddr boff;
 258     uint64_t ret;
 259
 260     ret = -1;
 261     /* Lazy reset to ROMD mode after a certain amount of read accesses */
 262     if (!pfl->rom_mode && pfl->wcycle == 0 &&
 263         ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
 264         pflash_register_memory(pfl, 1);
 265     }
 266     offset &= pfl->chip_len - 1;
 267     boff = offset & 0xFF;
 268     if (pfl->width == 2) {
 269         boff = boff >> 1;
 270     } else if (pfl->width == 4) {
 271         boff = boff >> 2;
 272     }
 273     switch (pfl->cmd) {
 274     default:
 275         /* This should never happen : reset state & treat it as a read*/
 276         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 277         pfl->wcycle = 0;
 278         pfl->cmd = 0;
 279         /* fall through to the read code */
 280     case 0x80:
 281         /* We accept reads during second unlock sequence... */
 282     case 0x00:
 283         /* Flash area read */
 284         ret = pflash_data_read(pfl, offset, width);
 285         break;
 286     case 0x90:
 287         /* flash ID read */
 288         switch (boff) {
 289         case 0x00:
 290         case 0x01:
 291             ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
 292             break;
 293         case 0x02:
 294             ret = 0x00; /* Pretend all sectors are unprotected */
 295             break;
 296         case 0x0E:
 297         case 0x0F:
 298             ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
 299             if (ret != (uint8_t)-1) {
 300                 break;
 301             }
 302             /* Fall through to data read. */
 303         default:
 304             ret = pflash_data_read(pfl, offset, width);
 305         }
 306         DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff, ret);
 307         break;
 308     case 0xA0:
 309     case 0x10:
 310     case 0x30:
 311         /* Status register read */
 312         ret = pfl->status;
 313         DPRINTF("%s: status %" PRIx64 "\n", __func__, ret);
 314         toggle_dq6(pfl);
 315         break;
 316     case 0x98:
 317         /* CFI query mode */
 318         if (boff < sizeof(pfl->cfi_table)) {
 319             ret = pfl->cfi_table[boff];
 320         } else {
 321             ret = 0;
 322         }
 323         break;
 324     }
 325     trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle);
 326
 327     return ret;
 328 }
 329
 330 /* update flash content on disk */
 331 static void pflash_update(PFlashCFI02 *pfl, int offset, int size)
 332 {
 333     int offset_end;
 334     if (pfl->blk) {
 335         offset_end = offset + size;
 336         /* widen to sector boundaries */
 337         offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
 338         offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
 339         blk_pwrite(pfl->blk, offset, pfl->storage + offset,
 340                    offset_end - offset, 0);
 341     }
 342 }
 343
 344 static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset)
 345 {
 346     uint64_t sector_len = pflash_sector_len(pfl, offset);
 347     offset &= ~(sector_len - 1);
 348     DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n",
 349             __func__, pfl->width * 2, offset,
 350             pfl->width * 2, offset + sector_len - 1);
 351     if (!pfl->ro) {
 352         uint8_t *p = pfl->storage;
 353         memset(p + offset, 0xff, sector_len);
 354         pflash_update(pfl, offset, sector_len);
 355     }
 356     set_dq7(pfl, 0x00);
 357     ++pfl->sectors_to_erase;
 358     /* Set (or reset) the 50 us timer for additional erase commands.  */
 359     timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000);
 360 }
 361
 362 static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
 363                          unsigned int width)
 364 {
 365     PFlashCFI02 *pfl = opaque;
 366     hwaddr boff;
 367     uint8_t *p;
 368     uint8_t cmd;
 369
 370     trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle);
 371     cmd = value;
 372     if (pfl->cmd != 0xA0) {
 373         /* Reset does nothing during chip erase and sector erase. */
 374         if (cmd == 0xF0 && pfl->cmd != 0x10 && pfl->cmd != 0x30) {
 375             if (pfl->wcycle == WCYCLE_AUTOSELECT_CFI) {
 376                 /* Return to autoselect mode. */
 377                 pfl->wcycle = 3;
 378                 pfl->cmd = 0x90;
 379                 return;
 380             }
 381             goto reset_flash;
 382         }
 383     }
 384     offset &= pfl->chip_len - 1;
 385
 386     boff = offset;
 387     if (pfl->width == 2) {
 388         boff = boff >> 1;
 389     } else if (pfl->width == 4) {
 390         boff = boff >> 2;
 391     }
 392     /* Only the least-significant 11 bits are used in most cases. */
 393     boff &= 0x7FF;
 394     switch (pfl->wcycle) {
 395     case 0:
 396         /* Set the device in I/O access mode if required */
 397         if (pfl->rom_mode)
 398             pflash_register_memory(pfl, 0);
 399         pfl->read_counter = 0;
 400         /* We're in read mode */
 401     check_unlock0:
 402         if (boff == 0x55 && cmd == 0x98) {
 403             /* Enter CFI query mode */
 404             pfl->wcycle = WCYCLE_CFI;
 405             pfl->cmd = 0x98;
 406             return;
 407         }
 408         if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
 409             DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
 410                     __func__, boff, cmd, pfl->unlock_addr0);
 411             goto reset_flash;
 412         }
 413         DPRINTF("%s: unlock sequence started\n", __func__);
 414         break;
 415     case 1:
 416         /* We started an unlock sequence */
 417     check_unlock1:
 418         if (boff != pfl->unlock_addr1 || cmd != 0x55) {
 419             DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
 420                     boff, cmd);
 421             goto reset_flash;
 422         }
 423         DPRINTF("%s: unlock sequence done\n", __func__);
 424         break;
 425     case 2:
 426         /* We finished an unlock sequence */
 427         if (!pfl->bypass && boff != pfl->unlock_addr0) {
 428             DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
 429                     boff, cmd);
 430             goto reset_flash;
 431         }
 432         switch (cmd) {
 433         case 0x20:
 434             pfl->bypass = 1;
 435             goto do_bypass;
 436         case 0x80:
 437         case 0x90:
 438         case 0xA0:
 439             pfl->cmd = cmd;
 440             DPRINTF("%s: starting command %02x\n", __func__, cmd);
 441             break;
 442         default:
 443             DPRINTF("%s: unknown command %02x\n", __func__, cmd);
 444             goto reset_flash;
 445         }
 446         break;
 447     case 3:
 448         switch (pfl->cmd) {
 449         case 0x80:
 450             /* We need another unlock sequence */
 451             goto check_unlock0;
 452         case 0xA0:
 453             trace_pflash_data_write(offset, width << 1, value, 0);
 454             if (!pfl->ro) {
 455                 p = (uint8_t *)pfl->storage + offset;
 456                 if (pfl->be) {
 457                     uint64_t current = ldn_be_p(p, width);
 458                     stn_be_p(p, width, current & value);
 459                 } else {
 460                     uint64_t current = ldn_le_p(p, width);
 461                     stn_le_p(p, width, current & value);
 462                 }
 463                 pflash_update(pfl, offset, width);
 464             }
 465             /*
 466              * While programming, status bit DQ7 should hold the opposite
 467              * value from how it was programmed.
 468              */
 469             set_dq7(pfl, ~value);
 470             /* Let's pretend write is immediate */
 471             if (pfl->bypass)
 472                 goto do_bypass;
 473             goto reset_flash;
 474         case 0x90:
 475             if (pfl->bypass && cmd == 0x00) {
 476                 /* Unlock bypass reset */
 477                 goto reset_flash;
 478             }
 479             /*
 480              * We can enter CFI query mode from autoselect mode, but we must
 481              * return to autoselect mode after a reset.
 482              */
 483             if (boff == 0x55 && cmd == 0x98) {
 484                 /* Enter autoselect CFI query mode */
 485                 pfl->wcycle = WCYCLE_AUTOSELECT_CFI;
 486                 pfl->cmd = 0x98;
 487                 return;
 488             }
 489             /* No break here */
 490         default:
 491             DPRINTF("%s: invalid write for command %02x\n",
 492                     __func__, pfl->cmd);
 493             goto reset_flash;
 494         }
 495     case 4:
 496         switch (pfl->cmd) {
 497         case 0xA0:
 498             /* Ignore writes while flash data write is occurring */
 499             /* As we suppose write is immediate, this should never happen */
 500             return;
 501         case 0x80:
 502             goto check_unlock1;
 503         default:
 504             /* Should never happen */
 505             DPRINTF("%s: invalid command state %02x (wc 4)\n",
 506                     __func__, pfl->cmd);
 507             goto reset_flash;
 508         }
 509         break;
 510     case 5:
 511         switch (cmd) {
 512         case 0x10:
 513             if (boff != pfl->unlock_addr0) {
 514                 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
 515                         __func__, offset);
 516                 goto reset_flash;
 517             }
 518             /* Chip erase */
 519             DPRINTF("%s: start chip erase\n", __func__);
 520             if (!pfl->ro) {
 521                 memset(pfl->storage, 0xff, pfl->chip_len);
 522                 pflash_update(pfl, 0, pfl->chip_len);
 523             }
 524             set_dq7(pfl, 0x00);
 525             /* Let's wait 5 seconds before chip erase is done */
 526             timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 527                       (NANOSECONDS_PER_SECOND * 5));
 528             break;
 529         case 0x30:
 530             /* Sector erase */
 531             pflash_sector_erase(pfl, offset);
 532             break;
 533         default:
 534             DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
 535             goto reset_flash;
 536         }
 537         pfl->cmd = cmd;
 538         break;
 539     case 6:
 540         switch (pfl->cmd) {
 541         case 0x10:
 542             /* Ignore writes during chip erase */
 543             return;
 544         case 0x30:
 545             /*
 546              * If DQ3 is 0, additional sector erase commands can be
 547              * written and anything else (other than an erase suspend) resets
 548              * the device.
 549              */
 550             if ((pfl->status & 0x08) == 0) {
 551                 if (cmd == 0x30) {
 552                     pflash_sector_erase(pfl, offset);
 553                 } else {
 554                     goto reset_flash;
 555                 }
 556             }
 557             /* Ignore writes during the actual erase. */
 558             return;
 559         default:
 560             /* Should never happen */
 561             DPRINTF("%s: invalid command state %02x (wc 6)\n",
 562                     __func__, pfl->cmd);
 563             goto reset_flash;
 564         }
 565         break;
 566     /* Special values for CFI queries */
 567     case WCYCLE_CFI:
 568     case WCYCLE_AUTOSELECT_CFI:
 569         DPRINTF("%s: invalid write in CFI query mode\n", __func__);
 570         goto reset_flash;
 571     default:
 572         /* Should never happen */
 573         DPRINTF("%s: invalid write state (wc 7)\n",  __func__);
 574         goto reset_flash;
 575     }
 576     pfl->wcycle++;
 577
 578     return;
 579
 580     /* Reset flash */
 581  reset_flash:
 582     trace_pflash_reset();
 583     pfl->bypass = 0;
 584     pfl->wcycle = 0;
 585     pfl->cmd = 0;
 586     return;
 587
 588  do_bypass:
 589     pfl->wcycle = 2;
 590     pfl->cmd = 0;
 591 }
 592
 593 static const MemoryRegionOps pflash_cfi02_ops = {
 594     .read = pflash_read,
 595     .write = pflash_write,
 596     .valid.min_access_size = 1,
 597     .valid.max_access_size = 4,
 598     .endianness = DEVICE_NATIVE_ENDIAN,
 599 };
 600
 601 static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
 602 {
 603     PFlashCFI02 *pfl = PFLASH_CFI02(dev);
 604     int ret;
 605     Error *local_err = NULL;
 606
 607     if (pfl->uniform_sector_len == 0 && pfl->sector_len[0] == 0) {
 608         error_setg(errp, "attribute \"sector-length\" not specified or zero.");
 609         return;
 610     }
 611     if (pfl->uniform_nb_blocs == 0 && pfl->nb_blocs[0] == 0) {
 612         error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
 613         return;
 614     }
 615     if (pfl->name == NULL) {
 616         error_setg(errp, "attribute \"name\" not specified.");
 617         return;
 618     }
 619
 620     int nb_regions;
 621     pfl->chip_len = 0;
 622     for (nb_regions = 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_regions) {
 623         if (pfl->nb_blocs[nb_regions] == 0) {
 624             break;
 625         }
 626         uint64_t sector_len_per_device = pfl->sector_len[nb_regions];
 627
 628         /*
 629          * The size of each flash sector must be a power of 2 and it must be
 630          * aligned at the same power of 2.
 631          */
 632         if (sector_len_per_device & 0xff ||
 633             sector_len_per_device >= (1 << 24) ||
 634             !is_power_of_2(sector_len_per_device))
 635         {
 636             error_setg(errp, "unsupported configuration: "
 637                        "sector length[%d] per device = %" PRIx64 ".",
 638                        nb_regions, sector_len_per_device);
 639             return;
 640         }
 641         if (pfl->chip_len & (sector_len_per_device - 1)) {
 642             error_setg(errp, "unsupported configuration: "
 643                        "flash region %d not correctly aligned.",
 644                        nb_regions);
 645             return;
 646         }
 647
 648         pfl->chip_len += (uint64_t)pfl->sector_len[nb_regions] *
 649                           pfl->nb_blocs[nb_regions];
 650     }
 651
 652     uint64_t uniform_len = (uint64_t)pfl->uniform_nb_blocs *
 653                            pfl->uniform_sector_len;
 654     if (nb_regions == 0) {
 655         nb_regions = 1;
 656         pfl->nb_blocs[0] = pfl->uniform_nb_blocs;
 657         pfl->sector_len[0] = pfl->uniform_sector_len;
 658         pfl->chip_len = uniform_len;
 659     } else if (uniform_len != 0 && uniform_len != pfl->chip_len) {
 660         error_setg(errp, "\"num-blocks\"*\"sector-length\" "
 661                    "different from \"num-blocks0\"*\'sector-length0\" + ... + "
 662                    "\"num-blocks3\"*\"sector-length3\"");
 663         return;
 664     }
 665
 666     memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl),
 667                                   &pflash_cfi02_ops, pfl, pfl->name,
 668                                   pfl->chip_len, &local_err);
 669     if (local_err) {
 670         error_propagate(errp, local_err);
 671         return;
 672     }
 673
 674     pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
 675
 676     if (pfl->blk) {
 677         uint64_t perm;
 678         pfl->ro = blk_is_read_only(pfl->blk);
 679         perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
 680         ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
 681         if (ret < 0) {
 682             return;
 683         }
 684     } else {
 685         pfl->ro = 0;
 686     }
 687
 688     if (pfl->blk) {
 689         if (!blk_check_size_and_read_all(pfl->blk, pfl->storage,
 690                                          pfl->chip_len, errp)) {
 691             vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
 692             return;
 693         }
 694     }
 695
 696     /* Only 11 bits are used in the comparison. */
 697     pfl->unlock_addr0 &= 0x7FF;
 698     pfl->unlock_addr1 &= 0x7FF;
 699
 700     pflash_setup_mappings(pfl);
 701     pfl->rom_mode = 1;
 702     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
 703
 704     timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
 705     pfl->wcycle = 0;
 706     pfl->cmd = 0;
 707     pfl->status = 0;
 708
 709     /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
 710     const uint16_t pri_ofs = 0x40;
 711     /* Standard "QRY" string */
 712     pfl->cfi_table[0x10] = 'Q';
 713     pfl->cfi_table[0x11] = 'R';
 714     pfl->cfi_table[0x12] = 'Y';
 715     /* Command set (AMD/Fujitsu) */
 716     pfl->cfi_table[0x13] = 0x02;
 717     pfl->cfi_table[0x14] = 0x00;
 718     /* Primary extended table address */
 719     pfl->cfi_table[0x15] = pri_ofs;
 720     pfl->cfi_table[0x16] = pri_ofs >> 8;
 721     /* Alternate command set (none) */
 722     pfl->cfi_table[0x17] = 0x00;
 723     pfl->cfi_table[0x18] = 0x00;
 724     /* Alternate extended table (none) */
 725     pfl->cfi_table[0x19] = 0x00;
 726     pfl->cfi_table[0x1A] = 0x00;
 727     /* Vcc min */
 728     pfl->cfi_table[0x1B] = 0x27;
 729     /* Vcc max */
 730     pfl->cfi_table[0x1C] = 0x36;
 731     /* Vpp min (no Vpp pin) */
 732     pfl->cfi_table[0x1D] = 0x00;
 733     /* Vpp max (no Vpp pin) */
 734     pfl->cfi_table[0x1E] = 0x00;
 735     /* Timeout per single byte/word write (128 ms) */
 736     pfl->cfi_table[0x1F] = 0x07;
 737     /* Timeout for min size buffer write (NA) */
 738     pfl->cfi_table[0x20] = 0x00;
 739     /* Typical timeout for block erase (512 ms) */
 740     pfl->cfi_table[0x21] = 0x09;
 741     /* Typical timeout for full chip erase (4096 ms) */
 742     pfl->cfi_table[0x22] = 0x0C;
 743     /* Reserved */
 744     pfl->cfi_table[0x23] = 0x01;
 745     /* Max timeout for buffer write (NA) */
 746     pfl->cfi_table[0x24] = 0x00;
 747     /* Max timeout for block erase */
 748     pfl->cfi_table[0x25] = 0x0A;
 749     /* Max timeout for chip erase */
 750     pfl->cfi_table[0x26] = 0x0D;
 751     /* Device size */
 752     pfl->cfi_table[0x27] = ctz32(pfl->chip_len);
 753     /* Flash device interface (8 & 16 bits) */
 754     pfl->cfi_table[0x28] = 0x02;
 755     pfl->cfi_table[0x29] = 0x00;
 756     /* Max number of bytes in multi-bytes write */
 757     /* XXX: disable buffered write as it's not supported */
 758     //    pfl->cfi_table[0x2A] = 0x05;
 759     pfl->cfi_table[0x2A] = 0x00;
 760     pfl->cfi_table[0x2B] = 0x00;
 761     /* Number of erase block regions */
 762     pfl->cfi_table[0x2c] = nb_regions;
 763     /* Erase block regions */
 764     for (int i = 0; i < nb_regions; ++i) {
 765         uint32_t sector_len_per_device = pfl->sector_len[i];
 766         pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1;
 767         pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8;
 768         pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8;
 769         pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16;
 770     }
 771     assert(0x2c + 4 * nb_regions < pri_ofs);
 772
 773     /* Extended */
 774     pfl->cfi_table[0x00 + pri_ofs] = 'P';
 775     pfl->cfi_table[0x01 + pri_ofs] = 'R';
 776     pfl->cfi_table[0x02 + pri_ofs] = 'I';
 777
 778     /* Extended version 1.0 */
 779     pfl->cfi_table[0x03 + pri_ofs] = '1';
 780     pfl->cfi_table[0x04 + pri_ofs] = '0';
 781
 782     /* Address sensitive unlock required. */
 783     pfl->cfi_table[0x05 + pri_ofs] = 0x00;
 784     /* Erase suspend not supported. */
 785     pfl->cfi_table[0x06 + pri_ofs] = 0x00;
 786     /* Sector protect not supported. */
 787     pfl->cfi_table[0x07 + pri_ofs] = 0x00;
 788     /* Temporary sector unprotect not supported. */
 789     pfl->cfi_table[0x08 + pri_ofs] = 0x00;
 790
 791     /* Sector protect/unprotect scheme. */
 792     pfl->cfi_table[0x09 + pri_ofs] = 0x00;
 793
 794     /* Simultaneous operation not supported. */
 795     pfl->cfi_table[0x0a + pri_ofs] = 0x00;
 796     /* Burst mode not supported. */
 797     pfl->cfi_table[0x0b + pri_ofs] = 0x00;
 798     /* Page mode not supported. */
 799     pfl->cfi_table[0x0c + pri_ofs] = 0x00;
 800     assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table));
 801 }
 802
 803 static Property pflash_cfi02_properties[] = {
 804     DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk),
 805     DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, uniform_nb_blocs, 0),
 806     DEFINE_PROP_UINT32("sector-length", PFlashCFI02, uniform_sector_len, 0),
 807     DEFINE_PROP_UINT32("num-blocks0", PFlashCFI02, nb_blocs[0], 0),
 808     DEFINE_PROP_UINT32("sector-length0", PFlashCFI02, sector_len[0], 0),
 809     DEFINE_PROP_UINT32("num-blocks1", PFlashCFI02, nb_blocs[1], 0),
 810     DEFINE_PROP_UINT32("sector-length1", PFlashCFI02, sector_len[1], 0),
 811     DEFINE_PROP_UINT32("num-blocks2", PFlashCFI02, nb_blocs[2], 0),
 812     DEFINE_PROP_UINT32("sector-length2", PFlashCFI02, sector_len[2], 0),
 813     DEFINE_PROP_UINT32("num-blocks3", PFlashCFI02, nb_blocs[3], 0),
 814     DEFINE_PROP_UINT32("sector-length3", PFlashCFI02, sector_len[3], 0),
 815     DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0),
 816     DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0),
 817     DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0),
 818     DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0),
 819     DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0),
 820     DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0),
 821     DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0),
 822     DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0),
 823     DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0),
 824     DEFINE_PROP_STRING("name", PFlashCFI02, name),
 825     DEFINE_PROP_END_OF_LIST(),
 826 };
 827
 828 static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp)
 829 {
 830     PFlashCFI02 *pfl = PFLASH_CFI02(dev);
 831     timer_del(&pfl->timer);
 832 }
 833
 834 static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
 835 {
 836     DeviceClass *dc = DEVICE_CLASS(klass);
 837
 838     dc->realize = pflash_cfi02_realize;
 839     dc->unrealize = pflash_cfi02_unrealize;
 840     dc->props = pflash_cfi02_properties;
 841     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 842 }
 843
 844 static const TypeInfo pflash_cfi02_info = {
 845     .name           = TYPE_PFLASH_CFI02,
 846     .parent         = TYPE_SYS_BUS_DEVICE,
 847     .instance_size  = sizeof(PFlashCFI02),
 848     .class_init     = pflash_cfi02_class_init,
 849 };
 850
 851 static void pflash_cfi02_register_types(void)
 852 {
 853     type_register_static(&pflash_cfi02_info);
 854 }
 855
 856 type_init(pflash_cfi02_register_types)
 857
 858 PFlashCFI02 *pflash_cfi02_register(hwaddr base,
 859                                    const char *name,
 860                                    hwaddr size,
 861                                    BlockBackend *blk,
 862                                    uint32_t sector_len,
 863                                    int nb_mappings, int width,
 864                                    uint16_t id0, uint16_t id1,
 865                                    uint16_t id2, uint16_t id3,
 866                                    uint16_t unlock_addr0,
 867                                    uint16_t unlock_addr1,
 868                                    int be)
 869 {
 870     DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02);
 871
 872     if (blk) {
 873         qdev_prop_set_drive(dev, "drive", blk, &error_abort);
 874     }
 875     assert(size % sector_len == 0);
 876     qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
 877     qdev_prop_set_uint32(dev, "sector-length", sector_len);
 878     qdev_prop_set_uint8(dev, "width", width);
 879     qdev_prop_set_uint8(dev, "mappings", nb_mappings);
 880     qdev_prop_set_uint8(dev, "big-endian", !!be);
 881     qdev_prop_set_uint16(dev, "id0", id0);
 882     qdev_prop_set_uint16(dev, "id1", id1);
 883     qdev_prop_set_uint16(dev, "id2", id2);
 884     qdev_prop_set_uint16(dev, "id3", id3);
 885     qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
 886     qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
 887     qdev_prop_set_string(dev, "name", name);
 888     qdev_init_nofail(dev);
 889
 890     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 891     return PFLASH_CFI02(dev);
 892 }