hw/block/pflash_cfi02.c

   1 /*
   2  *  CFI parallel flash with AMD command set emulation
   3  *
   4  *  Copyright (c) 2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /*
  21  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  22  * Supported commands/modes are:
  23  * - flash read
  24  * - flash write
  25  * - flash ID read
  26  * - sector erase
  27  * - chip erase
  28  * - unlock bypass command
  29  * - CFI queries
  30  *
  31  * It does not support flash interleaving.
  32  * It does not implement boot blocs with reduced size
  33  * It does not implement software data protection as found in many real chips
  34  * It does not implement erase suspend/resume commands
  35  * It does not implement multiple sectors erase
  36  */
  37
  38 #include "qemu/osdep.h"
  39 #include "hw/hw.h"
  40 #include "hw/block/flash.h"
  41 #include "qapi/error.h"
  42 #include "qemu/timer.h"
  43 #include "sysemu/block-backend.h"
  44 #include "qemu/host-utils.h"
  45 #include "hw/sysbus.h"
  46 #include "trace.h"
  47
  48 //#define PFLASH_DEBUG
  49 #ifdef PFLASH_DEBUG
  50 #define DPRINTF(fmt, ...)                                  \
  51 do {                                                       \
  52     fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__);       \
  53 } while (0)
  54 #else
  55 #define DPRINTF(fmt, ...) do { } while (0)
  56 #endif
  57
  58 #define PFLASH_LAZY_ROMD_THRESHOLD 42
  59
  60 #define PFLASH_CFI02(obj) \
  61     OBJECT_CHECK(PFlashCFI02, (obj), TYPE_PFLASH_CFI02)
  62
  63 struct PFlashCFI02 {
  64     /*< private >*/
  65     SysBusDevice parent_obj;
  66     /*< public >*/
  67
  68     BlockBackend *blk;
  69     uint32_t sector_len;
  70     uint32_t nb_blocs;
  71     uint32_t chip_len;
  72     uint8_t mappings;
  73     uint8_t width;
  74     uint8_t be;
  75     int wcycle; /* if 0, the flash is read normally */
  76     int bypass;
  77     int ro;
  78     uint8_t cmd;
  79     uint8_t status;
  80     /* FIXME: implement array device properties */
  81     uint16_t ident0;
  82     uint16_t ident1;
  83     uint16_t ident2;
  84     uint16_t ident3;
  85     uint16_t unlock_addr0;
  86     uint16_t unlock_addr1;
  87     uint8_t cfi_table[0x52];
  88     QEMUTimer timer;
  89     /* The device replicates the flash memory across its memory space.  Emulate
  90      * that by having a container (.mem) filled with an array of aliases
  91      * (.mem_mappings) pointing to the flash memory (.orig_mem).
  92      */
  93     MemoryRegion mem;
  94     MemoryRegion *mem_mappings;    /* array; one per mapping */
  95     MemoryRegion orig_mem;
  96     int rom_mode;
  97     int read_counter; /* used for lazy switch-back to rom mode */
  98     char *name;
  99     void *storage;
 100 };
 101
 102 /*
 103  * Set up replicated mappings of the same region.
 104  */
 105 static void pflash_setup_mappings(PFlashCFI02 *pfl)
 106 {
 107     unsigned i;
 108     hwaddr size = memory_region_size(&pfl->orig_mem);
 109
 110     memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
 111     pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
 112     for (i = 0; i < pfl->mappings; ++i) {
 113         memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
 114                                  "pflash-alias", &pfl->orig_mem, 0, size);
 115         memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
 116     }
 117 }
 118
 119 static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode)
 120 {
 121     memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode);
 122     pfl->rom_mode = rom_mode;
 123 }
 124
 125 static void pflash_timer (void *opaque)
 126 {
 127     PFlashCFI02 *pfl = opaque;
 128
 129     trace_pflash_timer_expired(pfl->cmd);
 130     /* Reset flash */
 131     pfl->status ^= 0x80;
 132     if (pfl->bypass) {
 133         pfl->wcycle = 2;
 134     } else {
 135         pflash_register_memory(pfl, 1);
 136         pfl->wcycle = 0;
 137     }
 138     pfl->cmd = 0;
 139 }
 140
 141 static uint32_t pflash_read(PFlashCFI02 *pfl, hwaddr offset,
 142                             int width, int be)
 143 {
 144     hwaddr boff;
 145     uint32_t ret;
 146     uint8_t *p;
 147
 148     ret = -1;
 149     trace_pflash_read(offset, pfl->cmd, width, pfl->wcycle);
 150     /* Lazy reset to ROMD mode after a certain amount of read accesses */
 151     if (!pfl->rom_mode && pfl->wcycle == 0 &&
 152         ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
 153         pflash_register_memory(pfl, 1);
 154     }
 155     offset &= pfl->chip_len - 1;
 156     boff = offset & 0xFF;
 157     if (pfl->width == 2)
 158         boff = boff >> 1;
 159     else if (pfl->width == 4)
 160         boff = boff >> 2;
 161     switch (pfl->cmd) {
 162     default:
 163         /* This should never happen : reset state & treat it as a read*/
 164         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 165         pfl->wcycle = 0;
 166         pfl->cmd = 0;
 167         /* fall through to the read code */
 168     case 0x80:
 169         /* We accept reads during second unlock sequence... */
 170     case 0x00:
 171     flash_read:
 172         /* Flash area read */
 173         p = pfl->storage;
 174         switch (width) {
 175         case 1:
 176             ret = p[offset];
 177             trace_pflash_data_read8(offset, ret);
 178             break;
 179         case 2:
 180             if (be) {
 181                 ret = p[offset] << 8;
 182                 ret |= p[offset + 1];
 183             } else {
 184                 ret = p[offset];
 185                 ret |= p[offset + 1] << 8;
 186             }
 187             trace_pflash_data_read16(offset, ret);
 188             break;
 189         case 4:
 190             if (be) {
 191                 ret = p[offset] << 24;
 192                 ret |= p[offset + 1] << 16;
 193                 ret |= p[offset + 2] << 8;
 194                 ret |= p[offset + 3];
 195             } else {
 196                 ret = p[offset];
 197                 ret |= p[offset + 1] << 8;
 198                 ret |= p[offset + 2] << 16;
 199                 ret |= p[offset + 3] << 24;
 200             }
 201             trace_pflash_data_read32(offset, ret);
 202             break;
 203         }
 204         break;
 205     case 0x90:
 206         /* flash ID read */
 207         switch (boff) {
 208         case 0x00:
 209         case 0x01:
 210             ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
 211             break;
 212         case 0x02:
 213             ret = 0x00; /* Pretend all sectors are unprotected */
 214             break;
 215         case 0x0E:
 216         case 0x0F:
 217             ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
 218             if (ret == (uint8_t)-1) {
 219                 goto flash_read;
 220             }
 221             break;
 222         default:
 223             goto flash_read;
 224         }
 225         DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret);
 226         break;
 227     case 0xA0:
 228     case 0x10:
 229     case 0x30:
 230         /* Status register read */
 231         ret = pfl->status;
 232         DPRINTF("%s: status %x\n", __func__, ret);
 233         /* Toggle bit 6 */
 234         pfl->status ^= 0x40;
 235         break;
 236     case 0x98:
 237         /* CFI query mode */
 238         if (boff < sizeof(pfl->cfi_table)) {
 239             ret = pfl->cfi_table[boff];
 240         } else {
 241             ret = 0;
 242         }
 243         break;
 244     }
 245
 246     return ret;
 247 }
 248
 249 /* update flash content on disk */
 250 static void pflash_update(PFlashCFI02 *pfl, int offset,
 251                           int size)
 252 {
 253     int offset_end;
 254     if (pfl->blk) {
 255         offset_end = offset + size;
 256         /* widen to sector boundaries */
 257         offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
 258         offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
 259         blk_pwrite(pfl->blk, offset, pfl->storage + offset,
 260                    offset_end - offset, 0);
 261     }
 262 }
 263
 264 static void pflash_write(PFlashCFI02 *pfl, hwaddr offset,
 265                          uint32_t value, int width, int be)
 266 {
 267     hwaddr boff;
 268     uint8_t *p;
 269     uint8_t cmd;
 270
 271     cmd = value;
 272     if (pfl->cmd != 0xA0 && cmd == 0xF0) {
 273 #if 0
 274         DPRINTF("%s: flash reset asked (%02x %02x)\n",
 275                 __func__, pfl->cmd, cmd);
 276 #endif
 277         goto reset_flash;
 278     }
 279     trace_pflash_write(offset, value, width, pfl->wcycle);
 280     offset &= pfl->chip_len - 1;
 281
 282     DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__,
 283             offset, value, width);
 284     boff = offset & (pfl->sector_len - 1);
 285     if (pfl->width == 2)
 286         boff = boff >> 1;
 287     else if (pfl->width == 4)
 288         boff = boff >> 2;
 289     switch (pfl->wcycle) {
 290     case 0:
 291         /* Set the device in I/O access mode if required */
 292         if (pfl->rom_mode)
 293             pflash_register_memory(pfl, 0);
 294         pfl->read_counter = 0;
 295         /* We're in read mode */
 296     check_unlock0:
 297         if (boff == 0x55 && cmd == 0x98) {
 298         enter_CFI_mode:
 299             /* Enter CFI query mode */
 300             pfl->wcycle = 7;
 301             pfl->cmd = 0x98;
 302             return;
 303         }
 304         if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
 305             DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
 306                     __func__, boff, cmd, pfl->unlock_addr0);
 307             goto reset_flash;
 308         }
 309         DPRINTF("%s: unlock sequence started\n", __func__);
 310         break;
 311     case 1:
 312         /* We started an unlock sequence */
 313     check_unlock1:
 314         if (boff != pfl->unlock_addr1 || cmd != 0x55) {
 315             DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
 316                     boff, cmd);
 317             goto reset_flash;
 318         }
 319         DPRINTF("%s: unlock sequence done\n", __func__);
 320         break;
 321     case 2:
 322         /* We finished an unlock sequence */
 323         if (!pfl->bypass && boff != pfl->unlock_addr0) {
 324             DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
 325                     boff, cmd);
 326             goto reset_flash;
 327         }
 328         switch (cmd) {
 329         case 0x20:
 330             pfl->bypass = 1;
 331             goto do_bypass;
 332         case 0x80:
 333         case 0x90:
 334         case 0xA0:
 335             pfl->cmd = cmd;
 336             DPRINTF("%s: starting command %02x\n", __func__, cmd);
 337             break;
 338         default:
 339             DPRINTF("%s: unknown command %02x\n", __func__, cmd);
 340             goto reset_flash;
 341         }
 342         break;
 343     case 3:
 344         switch (pfl->cmd) {
 345         case 0x80:
 346             /* We need another unlock sequence */
 347             goto check_unlock0;
 348         case 0xA0:
 349             trace_pflash_data_write(offset, value, width, 0);
 350             p = pfl->storage;
 351             if (!pfl->ro) {
 352                 switch (width) {
 353                 case 1:
 354                     p[offset] &= value;
 355                     pflash_update(pfl, offset, 1);
 356                     break;
 357                 case 2:
 358                     if (be) {
 359                         p[offset] &= value >> 8;
 360                         p[offset + 1] &= value;
 361                     } else {
 362                         p[offset] &= value;
 363                         p[offset + 1] &= value >> 8;
 364                     }
 365                     pflash_update(pfl, offset, 2);
 366                     break;
 367                 case 4:
 368                     if (be) {
 369                         p[offset] &= value >> 24;
 370                         p[offset + 1] &= value >> 16;
 371                         p[offset + 2] &= value >> 8;
 372                         p[offset + 3] &= value;
 373                     } else {
 374                         p[offset] &= value;
 375                         p[offset + 1] &= value >> 8;
 376                         p[offset + 2] &= value >> 16;
 377                         p[offset + 3] &= value >> 24;
 378                     }
 379                     pflash_update(pfl, offset, 4);
 380                     break;
 381                 }
 382             }
 383             pfl->status = 0x00 | ~(value & 0x80);
 384             /* Let's pretend write is immediate */
 385             if (pfl->bypass)
 386                 goto do_bypass;
 387             goto reset_flash;
 388         case 0x90:
 389             if (pfl->bypass && cmd == 0x00) {
 390                 /* Unlock bypass reset */
 391                 goto reset_flash;
 392             }
 393             /* We can enter CFI query mode from autoselect mode */
 394             if (boff == 0x55 && cmd == 0x98)
 395                 goto enter_CFI_mode;
 396             /* No break here */
 397         default:
 398             DPRINTF("%s: invalid write for command %02x\n",
 399                     __func__, pfl->cmd);
 400             goto reset_flash;
 401         }
 402     case 4:
 403         switch (pfl->cmd) {
 404         case 0xA0:
 405             /* Ignore writes while flash data write is occurring */
 406             /* As we suppose write is immediate, this should never happen */
 407             return;
 408         case 0x80:
 409             goto check_unlock1;
 410         default:
 411             /* Should never happen */
 412             DPRINTF("%s: invalid command state %02x (wc 4)\n",
 413                     __func__, pfl->cmd);
 414             goto reset_flash;
 415         }
 416         break;
 417     case 5:
 418         switch (cmd) {
 419         case 0x10:
 420             if (boff != pfl->unlock_addr0) {
 421                 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
 422                         __func__, offset);
 423                 goto reset_flash;
 424             }
 425             /* Chip erase */
 426             DPRINTF("%s: start chip erase\n", __func__);
 427             if (!pfl->ro) {
 428                 memset(pfl->storage, 0xFF, pfl->chip_len);
 429                 pflash_update(pfl, 0, pfl->chip_len);
 430             }
 431             pfl->status = 0x00;
 432             /* Let's wait 5 seconds before chip erase is done */
 433             timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 434                       (NANOSECONDS_PER_SECOND * 5));
 435             break;
 436         case 0x30:
 437             /* Sector erase */
 438             p = pfl->storage;
 439             offset &= ~(pfl->sector_len - 1);
 440             DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__,
 441                     offset);
 442             if (!pfl->ro) {
 443                 memset(p + offset, 0xFF, pfl->sector_len);
 444                 pflash_update(pfl, offset, pfl->sector_len);
 445             }
 446             pfl->status = 0x00;
 447             /* Let's wait 1/2 second before sector erase is done */
 448             timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 449                       (NANOSECONDS_PER_SECOND / 2));
 450             break;
 451         default:
 452             DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
 453             goto reset_flash;
 454         }
 455         pfl->cmd = cmd;
 456         break;
 457     case 6:
 458         switch (pfl->cmd) {
 459         case 0x10:
 460             /* Ignore writes during chip erase */
 461             return;
 462         case 0x30:
 463             /* Ignore writes during sector erase */
 464             return;
 465         default:
 466             /* Should never happen */
 467             DPRINTF("%s: invalid command state %02x (wc 6)\n",
 468                     __func__, pfl->cmd);
 469             goto reset_flash;
 470         }
 471         break;
 472     case 7: /* Special value for CFI queries */
 473         DPRINTF("%s: invalid write in CFI query mode\n", __func__);
 474         goto reset_flash;
 475     default:
 476         /* Should never happen */
 477         DPRINTF("%s: invalid write state (wc 7)\n",  __func__);
 478         goto reset_flash;
 479     }
 480     pfl->wcycle++;
 481
 482     return;
 483
 484     /* Reset flash */
 485  reset_flash:
 486     trace_pflash_reset();
 487     pfl->bypass = 0;
 488     pfl->wcycle = 0;
 489     pfl->cmd = 0;
 490     return;
 491
 492  do_bypass:
 493     pfl->wcycle = 2;
 494     pfl->cmd = 0;
 495 }
 496
 497 static uint64_t pflash_be_readfn(void *opaque, hwaddr addr, unsigned size)
 498 {
 499     return pflash_read(opaque, addr, size, 1);
 500 }
 501
 502 static void pflash_be_writefn(void *opaque, hwaddr addr,
 503                               uint64_t value, unsigned size)
 504 {
 505     pflash_write(opaque, addr, value, size, 1);
 506 }
 507
 508 static uint64_t pflash_le_readfn(void *opaque, hwaddr addr, unsigned size)
 509 {
 510     return pflash_read(opaque, addr, size, 0);
 511 }
 512
 513 static void pflash_le_writefn(void *opaque, hwaddr addr,
 514                               uint64_t value, unsigned size)
 515 {
 516     pflash_write(opaque, addr, value, size, 0);
 517 }
 518
 519 static const MemoryRegionOps pflash_cfi02_ops_be = {
 520     .read = pflash_be_readfn,
 521     .write = pflash_be_writefn,
 522     .valid.min_access_size = 1,
 523     .valid.max_access_size = 4,
 524     .endianness = DEVICE_NATIVE_ENDIAN,
 525 };
 526
 527 static const MemoryRegionOps pflash_cfi02_ops_le = {
 528     .read = pflash_le_readfn,
 529     .write = pflash_le_writefn,
 530     .valid.min_access_size = 1,
 531     .valid.max_access_size = 4,
 532     .endianness = DEVICE_NATIVE_ENDIAN,
 533 };
 534
 535 static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
 536 {
 537     PFlashCFI02 *pfl = PFLASH_CFI02(dev);
 538     uint32_t chip_len;
 539     int ret;
 540     Error *local_err = NULL;
 541
 542     if (pfl->sector_len == 0) {
 543         error_setg(errp, "attribute \"sector-length\" not specified or zero.");
 544         return;
 545     }
 546     if (pfl->nb_blocs == 0) {
 547         error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
 548         return;
 549     }
 550     if (pfl->name == NULL) {
 551         error_setg(errp, "attribute \"name\" not specified.");
 552         return;
 553     }
 554
 555     chip_len = pfl->sector_len * pfl->nb_blocs;
 556     /* XXX: to be fixed */
 557 #if 0
 558     if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
 559         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
 560         return NULL;
 561 #endif
 562
 563     memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), pfl->be ?
 564                                   &pflash_cfi02_ops_be : &pflash_cfi02_ops_le,
 565                                   pfl, pfl->name, chip_len, &local_err);
 566     if (local_err) {
 567         error_propagate(errp, local_err);
 568         return;
 569     }
 570
 571     pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
 572     pfl->chip_len = chip_len;
 573
 574     if (pfl->blk) {
 575         uint64_t perm;
 576         pfl->ro = blk_is_read_only(pfl->blk);
 577         perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
 578         ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
 579         if (ret < 0) {
 580             return;
 581         }
 582     } else {
 583         pfl->ro = 0;
 584     }
 585
 586     if (pfl->blk) {
 587         /* read the initial flash content */
 588         ret = blk_pread(pfl->blk, 0, pfl->storage, chip_len);
 589         if (ret < 0) {
 590             vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
 591             error_setg(errp, "failed to read the initial flash content");
 592             return;
 593         }
 594     }
 595
 596     pflash_setup_mappings(pfl);
 597     pfl->rom_mode = 1;
 598     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
 599
 600     timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
 601     pfl->wcycle = 0;
 602     pfl->cmd = 0;
 603     pfl->status = 0;
 604     /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
 605     /* Standard "QRY" string */
 606     pfl->cfi_table[0x10] = 'Q';
 607     pfl->cfi_table[0x11] = 'R';
 608     pfl->cfi_table[0x12] = 'Y';
 609     /* Command set (AMD/Fujitsu) */
 610     pfl->cfi_table[0x13] = 0x02;
 611     pfl->cfi_table[0x14] = 0x00;
 612     /* Primary extended table address */
 613     pfl->cfi_table[0x15] = 0x31;
 614     pfl->cfi_table[0x16] = 0x00;
 615     /* Alternate command set (none) */
 616     pfl->cfi_table[0x17] = 0x00;
 617     pfl->cfi_table[0x18] = 0x00;
 618     /* Alternate extended table (none) */
 619     pfl->cfi_table[0x19] = 0x00;
 620     pfl->cfi_table[0x1A] = 0x00;
 621     /* Vcc min */
 622     pfl->cfi_table[0x1B] = 0x27;
 623     /* Vcc max */
 624     pfl->cfi_table[0x1C] = 0x36;
 625     /* Vpp min (no Vpp pin) */
 626     pfl->cfi_table[0x1D] = 0x00;
 627     /* Vpp max (no Vpp pin) */
 628     pfl->cfi_table[0x1E] = 0x00;
 629     /* Reserved */
 630     pfl->cfi_table[0x1F] = 0x07;
 631     /* Timeout for min size buffer write (NA) */
 632     pfl->cfi_table[0x20] = 0x00;
 633     /* Typical timeout for block erase (512 ms) */
 634     pfl->cfi_table[0x21] = 0x09;
 635     /* Typical timeout for full chip erase (4096 ms) */
 636     pfl->cfi_table[0x22] = 0x0C;
 637     /* Reserved */
 638     pfl->cfi_table[0x23] = 0x01;
 639     /* Max timeout for buffer write (NA) */
 640     pfl->cfi_table[0x24] = 0x00;
 641     /* Max timeout for block erase */
 642     pfl->cfi_table[0x25] = 0x0A;
 643     /* Max timeout for chip erase */
 644     pfl->cfi_table[0x26] = 0x0D;
 645     /* Device size */
 646     pfl->cfi_table[0x27] = ctz32(chip_len);
 647     /* Flash device interface (8 & 16 bits) */
 648     pfl->cfi_table[0x28] = 0x02;
 649     pfl->cfi_table[0x29] = 0x00;
 650     /* Max number of bytes in multi-bytes write */
 651     /* XXX: disable buffered write as it's not supported */
 652     //    pfl->cfi_table[0x2A] = 0x05;
 653     pfl->cfi_table[0x2A] = 0x00;
 654     pfl->cfi_table[0x2B] = 0x00;
 655     /* Number of erase block regions (uniform) */
 656     pfl->cfi_table[0x2C] = 0x01;
 657     /* Erase block region 1 */
 658     pfl->cfi_table[0x2D] = pfl->nb_blocs - 1;
 659     pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8;
 660     pfl->cfi_table[0x2F] = pfl->sector_len >> 8;
 661     pfl->cfi_table[0x30] = pfl->sector_len >> 16;
 662
 663     /* Extended */
 664     pfl->cfi_table[0x31] = 'P';
 665     pfl->cfi_table[0x32] = 'R';
 666     pfl->cfi_table[0x33] = 'I';
 667
 668     pfl->cfi_table[0x34] = '1';
 669     pfl->cfi_table[0x35] = '0';
 670
 671     pfl->cfi_table[0x36] = 0x00;
 672     pfl->cfi_table[0x37] = 0x00;
 673     pfl->cfi_table[0x38] = 0x00;
 674     pfl->cfi_table[0x39] = 0x00;
 675
 676     pfl->cfi_table[0x3a] = 0x00;
 677
 678     pfl->cfi_table[0x3b] = 0x00;
 679     pfl->cfi_table[0x3c] = 0x00;
 680 }
 681
 682 static Property pflash_cfi02_properties[] = {
 683     DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk),
 684     DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, nb_blocs, 0),
 685     DEFINE_PROP_UINT32("sector-length", PFlashCFI02, sector_len, 0),
 686     DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0),
 687     DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0),
 688     DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0),
 689     DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0),
 690     DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0),
 691     DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0),
 692     DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0),
 693     DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0),
 694     DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0),
 695     DEFINE_PROP_STRING("name", PFlashCFI02, name),
 696     DEFINE_PROP_END_OF_LIST(),
 697 };
 698
 699 static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp)
 700 {
 701     PFlashCFI02 *pfl = PFLASH_CFI02(dev);
 702     timer_del(&pfl->timer);
 703 }
 704
 705 static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
 706 {
 707     DeviceClass *dc = DEVICE_CLASS(klass);
 708
 709     dc->realize = pflash_cfi02_realize;
 710     dc->unrealize = pflash_cfi02_unrealize;
 711     dc->props = pflash_cfi02_properties;
 712     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 713 }
 714
 715 static const TypeInfo pflash_cfi02_info = {
 716     .name           = TYPE_PFLASH_CFI02,
 717     .parent         = TYPE_SYS_BUS_DEVICE,
 718     .instance_size  = sizeof(PFlashCFI02),
 719     .class_init     = pflash_cfi02_class_init,
 720 };
 721
 722 static void pflash_cfi02_register_types(void)
 723 {
 724     type_register_static(&pflash_cfi02_info);
 725 }
 726
 727 type_init(pflash_cfi02_register_types)
 728
 729 PFlashCFI02 *pflash_cfi02_register(hwaddr base,
 730                                    DeviceState *qdev, const char *name,
 731                                    hwaddr size,
 732                                    BlockBackend *blk,
 733                                    uint32_t sector_len, int nb_blocs,
 734                                    int nb_mappings, int width,
 735                                    uint16_t id0, uint16_t id1,
 736                                    uint16_t id2, uint16_t id3,
 737                                    uint16_t unlock_addr0,
 738                                    uint16_t unlock_addr1,
 739                                    int be)
 740 {
 741     DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02);
 742
 743     if (blk) {
 744         qdev_prop_set_drive(dev, "drive", blk, &error_abort);
 745     }
 746     qdev_prop_set_uint32(dev, "num-blocks", nb_blocs);
 747     qdev_prop_set_uint32(dev, "sector-length", sector_len);
 748     qdev_prop_set_uint8(dev, "width", width);
 749     qdev_prop_set_uint8(dev, "mappings", nb_mappings);
 750     qdev_prop_set_uint8(dev, "big-endian", !!be);
 751     qdev_prop_set_uint16(dev, "id0", id0);
 752     qdev_prop_set_uint16(dev, "id1", id1);
 753     qdev_prop_set_uint16(dev, "id2", id2);
 754     qdev_prop_set_uint16(dev, "id3", id3);
 755     qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
 756     qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
 757     qdev_prop_set_string(dev, "name", name);
 758     qdev_init_nofail(dev);
 759
 760     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 761     return PFLASH_CFI02(dev);
 762 }