hw/char/digic-uart.c

   1 /*
   2  * QEMU model of the Canon DIGIC UART block.
   3  *
   4  * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
   5  *
   6  * This model is based on reverse engineering efforts
   7  * made by CHDK (http://chdk.wikia.com) and
   8  * Magic Lantern (http://www.magiclantern.fm) projects
   9  * contributors.
  10  *
  11  * See "Serial terminal" docs here:
  12  *   http://magiclantern.wikia.com/wiki/Register_Map#Misc_Registers
  13  *
  14  * The QEMU model of the Milkymist UART block by Michael Walle
  15  * is used as a template.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License as published by
  19  * the Free Software Foundation; either version 2 of the License, or
  20  * (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25  * GNU General Public License for more details.
  26  *
  27  */
  28
  29 #include "qemu/osdep.h"
  30 #include "hw/hw.h"
  31 #include "hw/sysbus.h"
  32 #include "sysemu/char.h"
  33
  34 #include "hw/char/digic-uart.h"
  35
  36 enum {
  37     ST_RX_RDY = (1 << 0),
  38     ST_TX_RDY = (1 << 1),
  39 };
  40
  41 static uint64_t digic_uart_read(void *opaque, hwaddr addr,
  42                                 unsigned size)
  43 {
  44     DigicUartState *s = opaque;
  45     uint64_t ret = 0;
  46
  47     addr >>= 2;
  48
  49     switch (addr) {
  50     case R_RX:
  51         s->reg_st &= ~(ST_RX_RDY);
  52         ret = s->reg_rx;
  53         break;
  54
  55     case R_ST:
  56         ret = s->reg_st;
  57         break;
  58
  59     default:
  60         qemu_log_mask(LOG_UNIMP,
  61                       "digic-uart: read access to unknown register 0x"
  62                       TARGET_FMT_plx, addr << 2);
  63     }
  64
  65     return ret;
  66 }
  67
  68 static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value,
  69                              unsigned size)
  70 {
  71     DigicUartState *s = opaque;
  72     unsigned char ch = value;
  73
  74     addr >>= 2;
  75
  76     switch (addr) {
  77     case R_TX:
  78         if (s->chr) {
  79             qemu_chr_fe_write_all(s->chr, &ch, 1);
  80         }
  81         break;
  82
  83     case R_ST:
  84         /*
  85          * Ignore write to R_ST.
  86          *
  87          * The point is that this register is actively used
  88          * during receiving and transmitting symbols,
  89          * but we don't know the function of most of bits.
  90          *
  91          * Ignoring writes to R_ST is only a simplification
  92          * of the model. It has no perceptible side effects
  93          * for existing guests.
  94          */
  95         break;
  96
  97     default:
  98         qemu_log_mask(LOG_UNIMP,
  99                       "digic-uart: write access to unknown register 0x"
 100                       TARGET_FMT_plx, addr << 2);
 101     }
 102 }
 103
 104 static const MemoryRegionOps uart_mmio_ops = {
 105     .read = digic_uart_read,
 106     .write = digic_uart_write,
 107     .valid = {
 108         .min_access_size = 4,
 109         .max_access_size = 4,
 110     },
 111     .endianness = DEVICE_NATIVE_ENDIAN,
 112 };
 113
 114 static int uart_can_rx(void *opaque)
 115 {
 116     DigicUartState *s = opaque;
 117
 118     return !(s->reg_st & ST_RX_RDY);
 119 }
 120
 121 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 122 {
 123     DigicUartState *s = opaque;
 124
 125     assert(uart_can_rx(opaque));
 126
 127     s->reg_st |= ST_RX_RDY;
 128     s->reg_rx = *buf;
 129 }
 130
 131 static void uart_event(void *opaque, int event)
 132 {
 133 }
 134
 135 static void digic_uart_reset(DeviceState *d)
 136 {
 137     DigicUartState *s = DIGIC_UART(d);
 138
 139     s->reg_rx = 0;
 140     s->reg_st = ST_TX_RDY;
 141 }
 142
 143 static void digic_uart_realize(DeviceState *dev, Error **errp)
 144 {
 145     DigicUartState *s = DIGIC_UART(dev);
 146
 147     /* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
 148     s->chr = qemu_char_get_next_serial();
 149     if (s->chr) {
 150         qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
 151     }
 152 }
 153
 154 static void digic_uart_init(Object *obj)
 155 {
 156     DigicUartState *s = DIGIC_UART(obj);
 157
 158     memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
 159                           TYPE_DIGIC_UART, 0x18);
 160     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->regs_region);
 161 }
 162
 163 static const VMStateDescription vmstate_digic_uart = {
 164     .name = "digic-uart",
 165     .version_id = 1,
 166     .minimum_version_id = 1,
 167     .fields = (VMStateField[]) {
 168         VMSTATE_UINT32(reg_rx, DigicUartState),
 169         VMSTATE_UINT32(reg_st, DigicUartState),
 170         VMSTATE_END_OF_LIST()
 171     }
 172 };
 173
 174 static void digic_uart_class_init(ObjectClass *klass, void *data)
 175 {
 176     DeviceClass *dc = DEVICE_CLASS(klass);
 177
 178     dc->realize = digic_uart_realize;
 179     dc->reset = digic_uart_reset;
 180     dc->vmsd = &vmstate_digic_uart;
 181     /* Reason: realize() method uses qemu_char_get_next_serial() */
 182     dc->cannot_instantiate_with_device_add_yet = true;
 183 }
 184
 185 static const TypeInfo digic_uart_info = {
 186     .name = TYPE_DIGIC_UART,
 187     .parent = TYPE_SYS_BUS_DEVICE,
 188     .instance_size = sizeof(DigicUartState),
 189     .instance_init = digic_uart_init,
 190     .class_init = digic_uart_class_init,
 191 };
 192
 193 static void digic_uart_register_types(void)
 194 {
 195     type_register_static(&digic_uart_info);
 196 }
 197
 198 type_init(digic_uart_register_types)