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1 /*
2 * QEMU ESCC (Z8030/Z8530/Z85C30/SCC/ESCC) serial port emulation
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/hw.h"
27 #include "hw/irq.h"
28 #include "hw/sysbus.h"
29 #include "qemu/module.h"
30 #include "hw/char/escc.h"
31 #include "ui/console.h"
32 #include "trace.h"
33
34 /*
35 * Chipset docs:
36 * "Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual",
37 * http://www.zilog.com/docs/serial/scc_escc_um.pdf
38 *
39 * On Sparc32 this is the serial port, mouse and keyboard part of chip STP2001
40 * (Slave I/O), also produced as NCR89C105. See
41 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
42 *
43 * The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
44 * mouse and keyboard ports don't implement all functions and they are
45 * only asynchronous. There is no DMA.
46 *
47 * Z85C30 is also used on PowerMacs. There are some small differences
48 * between Sparc version (sunzilog) and PowerMac (pmac):
49 * Offset between control and data registers
50 * There is some kind of lockup bug, but we can ignore it
51 * CTS is inverted
52 * DMA on pmac using DBDMA chip
53 * pmac can do IRDA and faster rates, sunzilog can only do 38400
54 * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz
55 */
56
57 /*
58 * Modifications:
59 * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented
60 * serial mouse queue.
61 * Implemented serial mouse protocol.
62 *
63 * 2010-May-23 Artyom Tarasenko: Reworked IUS logic
64 */
65
66 #define CHN_C(s) ((s)->chn == escc_chn_b ? 'b' : 'a')
67
68 #define SERIAL_CTRL 0
69 #define SERIAL_DATA 1
70
71 #define W_CMD 0
72 #define CMD_PTR_MASK 0x07
73 #define CMD_CMD_MASK 0x38
74 #define CMD_HI 0x08
75 #define CMD_CLR_TXINT 0x28
76 #define CMD_CLR_IUS 0x38
77 #define W_INTR 1
78 #define INTR_INTALL 0x01
79 #define INTR_TXINT 0x02
80 #define INTR_RXMODEMSK 0x18
81 #define INTR_RXINT1ST 0x08
82 #define INTR_RXINTALL 0x10
83 #define W_IVEC 2
84 #define W_RXCTRL 3
85 #define RXCTRL_RXEN 0x01
86 #define W_TXCTRL1 4
87 #define TXCTRL1_PAREN 0x01
88 #define TXCTRL1_PAREV 0x02
89 #define TXCTRL1_1STOP 0x04
90 #define TXCTRL1_1HSTOP 0x08
91 #define TXCTRL1_2STOP 0x0c
92 #define TXCTRL1_STPMSK 0x0c
93 #define TXCTRL1_CLK1X 0x00
94 #define TXCTRL1_CLK16X 0x40
95 #define TXCTRL1_CLK32X 0x80
96 #define TXCTRL1_CLK64X 0xc0
97 #define TXCTRL1_CLKMSK 0xc0
98 #define W_TXCTRL2 5
99 #define TXCTRL2_TXEN 0x08
100 #define TXCTRL2_BITMSK 0x60
101 #define TXCTRL2_5BITS 0x00
102 #define TXCTRL2_7BITS 0x20
103 #define TXCTRL2_6BITS 0x40
104 #define TXCTRL2_8BITS 0x60
105 #define W_SYNC1 6
106 #define W_SYNC2 7
107 #define W_TXBUF 8
108 #define W_MINTR 9
109 #define MINTR_STATUSHI 0x10
110 #define MINTR_RST_MASK 0xc0
111 #define MINTR_RST_B 0x40
112 #define MINTR_RST_A 0x80
113 #define MINTR_RST_ALL 0xc0
114 #define W_MISC1 10
115 #define W_CLOCK 11
116 #define CLOCK_TRXC 0x08
117 #define W_BRGLO 12
118 #define W_BRGHI 13
119 #define W_MISC2 14
120 #define MISC2_PLLDIS 0x30
121 #define W_EXTINT 15
122 #define EXTINT_DCD 0x08
123 #define EXTINT_SYNCINT 0x10
124 #define EXTINT_CTSINT 0x20
125 #define EXTINT_TXUNDRN 0x40
126 #define EXTINT_BRKINT 0x80
127
128 #define R_STATUS 0
129 #define STATUS_RXAV 0x01
130 #define STATUS_ZERO 0x02
131 #define STATUS_TXEMPTY 0x04
132 #define STATUS_DCD 0x08
133 #define STATUS_SYNC 0x10
134 #define STATUS_CTS 0x20
135 #define STATUS_TXUNDRN 0x40
136 #define STATUS_BRK 0x80
137 #define R_SPEC 1
138 #define SPEC_ALLSENT 0x01
139 #define SPEC_BITS8 0x06
140 #define R_IVEC 2
141 #define IVEC_TXINTB 0x00
142 #define IVEC_LONOINT 0x06
143 #define IVEC_LORXINTA 0x0c
144 #define IVEC_LORXINTB 0x04
145 #define IVEC_LOTXINTA 0x08
146 #define IVEC_HINOINT 0x60
147 #define IVEC_HIRXINTA 0x30
148 #define IVEC_HIRXINTB 0x20
149 #define IVEC_HITXINTA 0x10
150 #define R_INTR 3
151 #define INTR_EXTINTB 0x01
152 #define INTR_TXINTB 0x02
153 #define INTR_RXINTB 0x04
154 #define INTR_EXTINTA 0x08
155 #define INTR_TXINTA 0x10
156 #define INTR_RXINTA 0x20
157 #define R_IPEN 4
158 #define R_TXCTRL1 5
159 #define R_TXCTRL2 6
160 #define R_BC 7
161 #define R_RXBUF 8
162 #define R_RXCTRL 9
163 #define R_MISC 10
164 #define R_MISC1 11
165 #define R_BRGLO 12
166 #define R_BRGHI 13
167 #define R_MISC1I 14
168 #define R_EXTINT 15
169
170 static void handle_kbd_command(ESCCChannelState *s, int val);
171 static int serial_can_receive(void *opaque);
172 static void serial_receive_byte(ESCCChannelState *s, int ch);
173
174 static void clear_queue(void *opaque)
175 {
176 ESCCChannelState *s = opaque;
177 ESCCSERIOQueue *q = &s->queue;
178 q->rptr = q->wptr = q->count = 0;
179 }
180
181 static void put_queue(void *opaque, int b)
182 {
183 ESCCChannelState *s = opaque;
184 ESCCSERIOQueue *q = &s->queue;
185
186 trace_escc_put_queue(CHN_C(s), b);
187 if (q->count >= ESCC_SERIO_QUEUE_SIZE) {
188 return;
189 }
190 q->data[q->wptr] = b;
191 if (++q->wptr == ESCC_SERIO_QUEUE_SIZE) {
192 q->wptr = 0;
193 }
194 q->count++;
195 serial_receive_byte(s, 0);
196 }
197
198 static uint32_t get_queue(void *opaque)
199 {
200 ESCCChannelState *s = opaque;
201 ESCCSERIOQueue *q = &s->queue;
202 int val;
203
204 if (q->count == 0) {
205 return 0;
206 } else {
207 val = q->data[q->rptr];
208 if (++q->rptr == ESCC_SERIO_QUEUE_SIZE) {
209 q->rptr = 0;
210 }
211 q->count--;
212 }
213 trace_escc_get_queue(CHN_C(s), val);
214 if (q->count > 0)
215 serial_receive_byte(s, 0);
216 return val;
217 }
218
219 static int escc_update_irq_chn(ESCCChannelState *s)
220 {
221 if ((((s->wregs[W_INTR] & INTR_TXINT) && (s->txint == 1)) ||
222 // tx ints enabled, pending
223 ((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) ||
224 ((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) &&
225 s->rxint == 1) || // rx ints enabled, pending
226 ((s->wregs[W_EXTINT] & EXTINT_BRKINT) &&
227 (s->rregs[R_STATUS] & STATUS_BRK)))) { // break int e&p
228 return 1;
229 }
230 return 0;
231 }
232
233 static void escc_update_irq(ESCCChannelState *s)
234 {
235 int irq;
236
237 irq = escc_update_irq_chn(s);
238 irq |= escc_update_irq_chn(s->otherchn);
239
240 trace_escc_update_irq(irq);
241 qemu_set_irq(s->irq, irq);
242 }
243
244 static void escc_reset_chn(ESCCChannelState *s)
245 {
246 int i;
247
248 s->reg = 0;
249 for (i = 0; i < ESCC_SERIAL_REGS; i++) {
250 s->rregs[i] = 0;
251 s->wregs[i] = 0;
252 }
253 s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; // 1X divisor, 1 stop bit, no parity
254 s->wregs[W_MINTR] = MINTR_RST_ALL;
255 s->wregs[W_CLOCK] = CLOCK_TRXC; // Synch mode tx clock = TRxC
256 s->wregs[W_MISC2] = MISC2_PLLDIS; // PLL disabled
257 s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |
258 EXTINT_TXUNDRN | EXTINT_BRKINT; // Enable most interrupts
259 if (s->disabled)
260 s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC |
261 STATUS_CTS | STATUS_TXUNDRN;
262 else
263 s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN;
264 s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT;
265
266 s->rx = s->tx = 0;
267 s->rxint = s->txint = 0;
268 s->rxint_under_svc = s->txint_under_svc = 0;
269 s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0;
270 clear_queue(s);
271 }
272
273 static void escc_reset(DeviceState *d)
274 {
275 ESCCState *s = ESCC(d);
276
277 escc_reset_chn(&s->chn[0]);
278 escc_reset_chn(&s->chn[1]);
279 }
280
281 static inline void set_rxint(ESCCChannelState *s)
282 {
283 s->rxint = 1;
284 /* XXX: missing daisy chainnig: escc_chn_b rx should have a lower priority
285 than chn_a rx/tx/special_condition service*/
286 s->rxint_under_svc = 1;
287 if (s->chn == escc_chn_a) {
288 s->rregs[R_INTR] |= INTR_RXINTA;
289 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
290 s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA;
291 else
292 s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA;
293 } else {
294 s->otherchn->rregs[R_INTR] |= INTR_RXINTB;
295 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
296 s->rregs[R_IVEC] = IVEC_HIRXINTB;
297 else
298 s->rregs[R_IVEC] = IVEC_LORXINTB;
299 }
300 escc_update_irq(s);
301 }
302
303 static inline void set_txint(ESCCChannelState *s)
304 {
305 s->txint = 1;
306 if (!s->rxint_under_svc) {
307 s->txint_under_svc = 1;
308 if (s->chn == escc_chn_a) {
309 if (s->wregs[W_INTR] & INTR_TXINT) {
310 s->rregs[R_INTR] |= INTR_TXINTA;
311 }
312 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
313 s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA;
314 else
315 s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA;
316 } else {
317 s->rregs[R_IVEC] = IVEC_TXINTB;
318 if (s->wregs[W_INTR] & INTR_TXINT) {
319 s->otherchn->rregs[R_INTR] |= INTR_TXINTB;
320 }
321 }
322 escc_update_irq(s);
323 }
324 }
325
326 static inline void clr_rxint(ESCCChannelState *s)
327 {
328 s->rxint = 0;
329 s->rxint_under_svc = 0;
330 if (s->chn == escc_chn_a) {
331 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
332 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT;
333 else
334 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT;
335 s->rregs[R_INTR] &= ~INTR_RXINTA;
336 } else {
337 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
338 s->rregs[R_IVEC] = IVEC_HINOINT;
339 else
340 s->rregs[R_IVEC] = IVEC_LONOINT;
341 s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB;
342 }
343 if (s->txint)
344 set_txint(s);
345 escc_update_irq(s);
346 }
347
348 static inline void clr_txint(ESCCChannelState *s)
349 {
350 s->txint = 0;
351 s->txint_under_svc = 0;
352 if (s->chn == escc_chn_a) {
353 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
354 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT;
355 else
356 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT;
357 s->rregs[R_INTR] &= ~INTR_TXINTA;
358 } else {
359 s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB;
360 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
361 s->rregs[R_IVEC] = IVEC_HINOINT;
362 else
363 s->rregs[R_IVEC] = IVEC_LONOINT;
364 s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB;
365 }
366 if (s->rxint)
367 set_rxint(s);
368 escc_update_irq(s);
369 }
370
371 static void escc_update_parameters(ESCCChannelState *s)
372 {
373 int speed, parity, data_bits, stop_bits;
374 QEMUSerialSetParams ssp;
375
376 if (!qemu_chr_fe_backend_connected(&s->chr) || s->type != escc_serial)
377 return;
378
379 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) {
380 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV)
381 parity = 'E';
382 else
383 parity = 'O';
384 } else {
385 parity = 'N';
386 }
387 if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP)
388 stop_bits = 2;
389 else
390 stop_bits = 1;
391 switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) {
392 case TXCTRL2_5BITS:
393 data_bits = 5;
394 break;
395 case TXCTRL2_7BITS:
396 data_bits = 7;
397 break;
398 case TXCTRL2_6BITS:
399 data_bits = 6;
400 break;
401 default:
402 case TXCTRL2_8BITS:
403 data_bits = 8;
404 break;
405 }
406 speed = s->clock / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2);
407 switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) {
408 case TXCTRL1_CLK1X:
409 break;
410 case TXCTRL1_CLK16X:
411 speed /= 16;
412 break;
413 case TXCTRL1_CLK32X:
414 speed /= 32;
415 break;
416 default:
417 case TXCTRL1_CLK64X:
418 speed /= 64;
419 break;
420 }
421 ssp.speed = speed;
422 ssp.parity = parity;
423 ssp.data_bits = data_bits;
424 ssp.stop_bits = stop_bits;
425 trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits);
426 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
427 }
428
429 static void escc_mem_write(void *opaque, hwaddr addr,
430 uint64_t val, unsigned size)
431 {
432 ESCCState *serial = opaque;
433 ESCCChannelState *s;
434 uint32_t saddr;
435 int newreg, channel;
436
437 val &= 0xff;
438 saddr = (addr >> serial->it_shift) & 1;
439 channel = (addr >> (serial->it_shift + 1)) & 1;
440 s = &serial->chn[channel];
441 switch (saddr) {
442 case SERIAL_CTRL:
443 trace_escc_mem_writeb_ctrl(CHN_C(s), s->reg, val & 0xff);
444 newreg = 0;
445 switch (s->reg) {
446 case W_CMD:
447 newreg = val & CMD_PTR_MASK;
448 val &= CMD_CMD_MASK;
449 switch (val) {
450 case CMD_HI:
451 newreg |= CMD_HI;
452 break;
453 case CMD_CLR_TXINT:
454 clr_txint(s);
455 break;
456 case CMD_CLR_IUS:
457 if (s->rxint_under_svc) {
458 s->rxint_under_svc = 0;
459 if (s->txint) {
460 set_txint(s);
461 }
462 } else if (s->txint_under_svc) {
463 s->txint_under_svc = 0;
464 }
465 escc_update_irq(s);
466 break;
467 default:
468 break;
469 }
470 break;
471 case W_INTR ... W_RXCTRL:
472 case W_SYNC1 ... W_TXBUF:
473 case W_MISC1 ... W_CLOCK:
474 case W_MISC2 ... W_EXTINT:
475 s->wregs[s->reg] = val;
476 break;
477 case W_TXCTRL1:
478 case W_TXCTRL2:
479 s->wregs[s->reg] = val;
480 escc_update_parameters(s);
481 break;
482 case W_BRGLO:
483 case W_BRGHI:
484 s->wregs[s->reg] = val;
485 s->rregs[s->reg] = val;
486 escc_update_parameters(s);
487 break;
488 case W_MINTR:
489 switch (val & MINTR_RST_MASK) {
490 case 0:
491 default:
492 break;
493 case MINTR_RST_B:
494 escc_reset_chn(&serial->chn[0]);
495 return;
496 case MINTR_RST_A:
497 escc_reset_chn(&serial->chn[1]);
498 return;
499 case MINTR_RST_ALL:
500 escc_reset(DEVICE(serial));
501 return;
502 }
503 break;
504 default:
505 break;
506 }
507 if (s->reg == 0)
508 s->reg = newreg;
509 else
510 s->reg = 0;
511 break;
512 case SERIAL_DATA:
513 trace_escc_mem_writeb_data(CHN_C(s), val);
514 /*
515 * Lower the irq when data is written to the Tx buffer and no other
516 * interrupts are currently pending. The irq will be raised again once
517 * the Tx buffer becomes empty below.
518 */
519 s->txint = 0;
520 escc_update_irq(s);
521 s->tx = val;
522 if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled
523 if (qemu_chr_fe_backend_connected(&s->chr)) {
524 /* XXX this blocks entire thread. Rewrite to use
525 * qemu_chr_fe_write and background I/O callbacks */
526 qemu_chr_fe_write_all(&s->chr, &s->tx, 1);
527 } else if (s->type == escc_kbd && !s->disabled) {
528 handle_kbd_command(s, val);
529 }
530 }
531 s->rregs[R_STATUS] |= STATUS_TXEMPTY; // Tx buffer empty
532 s->rregs[R_SPEC] |= SPEC_ALLSENT; // All sent
533 set_txint(s);
534 break;
535 default:
536 break;
537 }
538 }
539
540 static uint64_t escc_mem_read(void *opaque, hwaddr addr,
541 unsigned size)
542 {
543 ESCCState *serial = opaque;
544 ESCCChannelState *s;
545 uint32_t saddr;
546 uint32_t ret;
547 int channel;
548
549 saddr = (addr >> serial->it_shift) & 1;
550 channel = (addr >> (serial->it_shift + 1)) & 1;
551 s = &serial->chn[channel];
552 switch (saddr) {
553 case SERIAL_CTRL:
554 trace_escc_mem_readb_ctrl(CHN_C(s), s->reg, s->rregs[s->reg]);
555 ret = s->rregs[s->reg];
556 s->reg = 0;
557 return ret;
558 case SERIAL_DATA:
559 s->rregs[R_STATUS] &= ~STATUS_RXAV;
560 clr_rxint(s);
561 if (s->type == escc_kbd || s->type == escc_mouse) {
562 ret = get_queue(s);
563 } else {
564 ret = s->rx;
565 }
566 trace_escc_mem_readb_data(CHN_C(s), ret);
567 qemu_chr_fe_accept_input(&s->chr);
568 return ret;
569 default:
570 break;
571 }
572 return 0;
573 }
574
575 static const MemoryRegionOps escc_mem_ops = {
576 .read = escc_mem_read,
577 .write = escc_mem_write,
578 .endianness = DEVICE_NATIVE_ENDIAN,
579 .valid = {
580 .min_access_size = 1,
581 .max_access_size = 1,
582 },
583 };
584
585 static int serial_can_receive(void *opaque)
586 {
587 ESCCChannelState *s = opaque;
588 int ret;
589
590 if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) // Rx not enabled
591 || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV))
592 // char already available
593 ret = 0;
594 else
595 ret = 1;
596 return ret;
597 }
598
599 static void serial_receive_byte(ESCCChannelState *s, int ch)
600 {
601 trace_escc_serial_receive_byte(CHN_C(s), ch);
602 s->rregs[R_STATUS] |= STATUS_RXAV;
603 s->rx = ch;
604 set_rxint(s);
605 }
606
607 static void serial_receive_break(ESCCChannelState *s)
608 {
609 s->rregs[R_STATUS] |= STATUS_BRK;
610 escc_update_irq(s);
611 }
612
613 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
614 {
615 ESCCChannelState *s = opaque;
616 serial_receive_byte(s, buf[0]);
617 }
618
619 static void serial_event(void *opaque, int event)
620 {
621 ESCCChannelState *s = opaque;
622 if (event == CHR_EVENT_BREAK)
623 serial_receive_break(s);
624 }
625
626 static const VMStateDescription vmstate_escc_chn = {
627 .name ="escc_chn",
628 .version_id = 2,
629 .minimum_version_id = 1,
630 .fields = (VMStateField[]) {
631 VMSTATE_UINT32(vmstate_dummy, ESCCChannelState),
632 VMSTATE_UINT32(reg, ESCCChannelState),
633 VMSTATE_UINT32(rxint, ESCCChannelState),
634 VMSTATE_UINT32(txint, ESCCChannelState),
635 VMSTATE_UINT32(rxint_under_svc, ESCCChannelState),
636 VMSTATE_UINT32(txint_under_svc, ESCCChannelState),
637 VMSTATE_UINT8(rx, ESCCChannelState),
638 VMSTATE_UINT8(tx, ESCCChannelState),
639 VMSTATE_BUFFER(wregs, ESCCChannelState),
640 VMSTATE_BUFFER(rregs, ESCCChannelState),
641 VMSTATE_END_OF_LIST()
642 }
643 };
644
645 static const VMStateDescription vmstate_escc = {
646 .name ="escc",
647 .version_id = 2,
648 .minimum_version_id = 1,
649 .fields = (VMStateField[]) {
650 VMSTATE_STRUCT_ARRAY(chn, ESCCState, 2, 2, vmstate_escc_chn,
651 ESCCChannelState),
652 VMSTATE_END_OF_LIST()
653 }
654 };
655
656 static void sunkbd_handle_event(DeviceState *dev, QemuConsole *src,
657 InputEvent *evt)
658 {
659 ESCCChannelState *s = (ESCCChannelState *)dev;
660 int qcode, keycode;
661 InputKeyEvent *key;
662
663 assert(evt->type == INPUT_EVENT_KIND_KEY);
664 key = evt->u.key.data;
665 qcode = qemu_input_key_value_to_qcode(key->key);
666 trace_escc_sunkbd_event_in(qcode, QKeyCode_str(qcode),
667 key->down);
668
669 if (qcode == Q_KEY_CODE_CAPS_LOCK) {
670 if (key->down) {
671 s->caps_lock_mode ^= 1;
672 if (s->caps_lock_mode == 2) {
673 return; /* Drop second press */
674 }
675 } else {
676 s->caps_lock_mode ^= 2;
677 if (s->caps_lock_mode == 3) {
678 return; /* Drop first release */
679 }
680 }
681 }
682
683 if (qcode == Q_KEY_CODE_NUM_LOCK) {
684 if (key->down) {
685 s->num_lock_mode ^= 1;
686 if (s->num_lock_mode == 2) {
687 return; /* Drop second press */
688 }
689 } else {
690 s->num_lock_mode ^= 2;
691 if (s->num_lock_mode == 3) {
692 return; /* Drop first release */
693 }
694 }
695 }
696
697 if (qcode > qemu_input_map_qcode_to_sun_len) {
698 return;
699 }
700
701 keycode = qemu_input_map_qcode_to_sun[qcode];
702 if (!key->down) {
703 keycode |= 0x80;
704 }
705 trace_escc_sunkbd_event_out(keycode);
706 put_queue(s, keycode);
707 }
708
709 static QemuInputHandler sunkbd_handler = {
710 .name = "sun keyboard",
711 .mask = INPUT_EVENT_MASK_KEY,
712 .event = sunkbd_handle_event,
713 };
714
715 static void handle_kbd_command(ESCCChannelState *s, int val)
716 {
717 trace_escc_kbd_command(val);
718 if (s->led_mode) { // Ignore led byte
719 s->led_mode = 0;
720 return;
721 }
722 switch (val) {
723 case 1: // Reset, return type code
724 clear_queue(s);
725 put_queue(s, 0xff);
726 put_queue(s, 4); // Type 4
727 put_queue(s, 0x7f);
728 break;
729 case 0xe: // Set leds
730 s->led_mode = 1;
731 break;
732 case 7: // Query layout
733 case 0xf:
734 clear_queue(s);
735 put_queue(s, 0xfe);
736 put_queue(s, 0x21); /* en-us layout */
737 break;
738 default:
739 break;
740 }
741 }
742
743 static void sunmouse_event(void *opaque,
744 int dx, int dy, int dz, int buttons_state)
745 {
746 ESCCChannelState *s = opaque;
747 int ch;
748
749 trace_escc_sunmouse_event(dx, dy, buttons_state);
750 ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */
751
752 if (buttons_state & MOUSE_EVENT_LBUTTON)
753 ch ^= 0x4;
754 if (buttons_state & MOUSE_EVENT_MBUTTON)
755 ch ^= 0x2;
756 if (buttons_state & MOUSE_EVENT_RBUTTON)
757 ch ^= 0x1;
758
759 put_queue(s, ch);
760
761 ch = dx;
762
763 if (ch > 127)
764 ch = 127;
765 else if (ch < -127)
766 ch = -127;
767
768 put_queue(s, ch & 0xff);
769
770 ch = -dy;
771
772 if (ch > 127)
773 ch = 127;
774 else if (ch < -127)
775 ch = -127;
776
777 put_queue(s, ch & 0xff);
778
779 // MSC protocol specify two extra motion bytes
780
781 put_queue(s, 0);
782 put_queue(s, 0);
783 }
784
785 static void escc_init1(Object *obj)
786 {
787 ESCCState *s = ESCC(obj);
788 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
789 unsigned int i;
790
791 for (i = 0; i < 2; i++) {
792 sysbus_init_irq(dev, &s->chn[i].irq);
793 s->chn[i].chn = 1 - i;
794 }
795 s->chn[0].otherchn = &s->chn[1];
796 s->chn[1].otherchn = &s->chn[0];
797
798 sysbus_init_mmio(dev, &s->mmio);
799 }
800
801 static void escc_realize(DeviceState *dev, Error **errp)
802 {
803 ESCCState *s = ESCC(dev);
804 unsigned int i;
805
806 s->chn[0].disabled = s->disabled;
807 s->chn[1].disabled = s->disabled;
808
809 memory_region_init_io(&s->mmio, OBJECT(dev), &escc_mem_ops, s, "escc",
810 ESCC_SIZE << s->it_shift);
811
812 for (i = 0; i < 2; i++) {
813 if (qemu_chr_fe_backend_connected(&s->chn[i].chr)) {
814 s->chn[i].clock = s->frequency / 2;
815 qemu_chr_fe_set_handlers(&s->chn[i].chr, serial_can_receive,
816 serial_receive1, serial_event, NULL,
817 &s->chn[i], NULL, true);
818 }
819 }
820
821 if (s->chn[0].type == escc_mouse) {
822 qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0,
823 "QEMU Sun Mouse");
824 }
825 if (s->chn[1].type == escc_kbd) {
826 s->chn[1].hs = qemu_input_handler_register((DeviceState *)(&s->chn[1]),
827 &sunkbd_handler);
828 }
829 }
830
831 static Property escc_properties[] = {
832 DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0),
833 DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0),
834 DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0),
835 DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0),
836 DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0),
837 DEFINE_PROP_CHR("chrB", ESCCState, chn[0].chr),
838 DEFINE_PROP_CHR("chrA", ESCCState, chn[1].chr),
839 DEFINE_PROP_END_OF_LIST(),
840 };
841
842 static void escc_class_init(ObjectClass *klass, void *data)
843 {
844 DeviceClass *dc = DEVICE_CLASS(klass);
845
846 dc->reset = escc_reset;
847 dc->realize = escc_realize;
848 dc->vmsd = &vmstate_escc;
849 dc->props = escc_properties;
850 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
851 }
852
853 static const TypeInfo escc_info = {
854 .name = TYPE_ESCC,
855 .parent = TYPE_SYS_BUS_DEVICE,
856 .instance_size = sizeof(ESCCState),
857 .instance_init = escc_init1,
858 .class_init = escc_class_init,
859 };
860
861 static void escc_register_types(void)
862 {
863 type_register_static(&escc_info);
864 }
865
866 type_init(escc_register_types)