2 * QEMU ESCC (Z8030/Z8530/Z85C30/SCC/ESCC) serial port emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
28 #include "hw/sysbus.h"
29 #include "qemu/module.h"
30 #include "hw/char/escc.h"
31 #include "ui/console.h"
36 * "Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual",
37 * http://www.zilog.com/docs/serial/scc_escc_um.pdf
39 * On Sparc32 this is the serial port, mouse and keyboard part of chip STP2001
40 * (Slave I/O), also produced as NCR89C105. See
41 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
43 * The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
44 * mouse and keyboard ports don't implement all functions and they are
45 * only asynchronous. There is no DMA.
47 * Z85C30 is also used on PowerMacs. There are some small differences
48 * between Sparc version (sunzilog) and PowerMac (pmac):
49 * Offset between control and data registers
50 * There is some kind of lockup bug, but we can ignore it
52 * DMA on pmac using DBDMA chip
53 * pmac can do IRDA and faster rates, sunzilog can only do 38400
54 * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz
59 * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented
61 * Implemented serial mouse protocol.
63 * 2010-May-23 Artyom Tarasenko: Reworked IUS logic
66 #define CHN_C(s) ((s)->chn == escc_chn_b ? 'b' : 'a')
72 #define CMD_PTR_MASK 0x07
73 #define CMD_CMD_MASK 0x38
75 #define CMD_CLR_TXINT 0x28
76 #define CMD_CLR_IUS 0x38
78 #define INTR_INTALL 0x01
79 #define INTR_TXINT 0x02
80 #define INTR_RXMODEMSK 0x18
81 #define INTR_RXINT1ST 0x08
82 #define INTR_RXINTALL 0x10
85 #define RXCTRL_RXEN 0x01
87 #define TXCTRL1_PAREN 0x01
88 #define TXCTRL1_PAREV 0x02
89 #define TXCTRL1_1STOP 0x04
90 #define TXCTRL1_1HSTOP 0x08
91 #define TXCTRL1_2STOP 0x0c
92 #define TXCTRL1_STPMSK 0x0c
93 #define TXCTRL1_CLK1X 0x00
94 #define TXCTRL1_CLK16X 0x40
95 #define TXCTRL1_CLK32X 0x80
96 #define TXCTRL1_CLK64X 0xc0
97 #define TXCTRL1_CLKMSK 0xc0
99 #define TXCTRL2_TXEN 0x08
100 #define TXCTRL2_BITMSK 0x60
101 #define TXCTRL2_5BITS 0x00
102 #define TXCTRL2_7BITS 0x20
103 #define TXCTRL2_6BITS 0x40
104 #define TXCTRL2_8BITS 0x60
109 #define MINTR_STATUSHI 0x10
110 #define MINTR_RST_MASK 0xc0
111 #define MINTR_RST_B 0x40
112 #define MINTR_RST_A 0x80
113 #define MINTR_RST_ALL 0xc0
116 #define CLOCK_TRXC 0x08
120 #define MISC2_PLLDIS 0x30
122 #define EXTINT_DCD 0x08
123 #define EXTINT_SYNCINT 0x10
124 #define EXTINT_CTSINT 0x20
125 #define EXTINT_TXUNDRN 0x40
126 #define EXTINT_BRKINT 0x80
129 #define STATUS_RXAV 0x01
130 #define STATUS_ZERO 0x02
131 #define STATUS_TXEMPTY 0x04
132 #define STATUS_DCD 0x08
133 #define STATUS_SYNC 0x10
134 #define STATUS_CTS 0x20
135 #define STATUS_TXUNDRN 0x40
136 #define STATUS_BRK 0x80
138 #define SPEC_ALLSENT 0x01
139 #define SPEC_BITS8 0x06
141 #define IVEC_TXINTB 0x00
142 #define IVEC_LONOINT 0x06
143 #define IVEC_LORXINTA 0x0c
144 #define IVEC_LORXINTB 0x04
145 #define IVEC_LOTXINTA 0x08
146 #define IVEC_HINOINT 0x60
147 #define IVEC_HIRXINTA 0x30
148 #define IVEC_HIRXINTB 0x20
149 #define IVEC_HITXINTA 0x10
151 #define INTR_EXTINTB 0x01
152 #define INTR_TXINTB 0x02
153 #define INTR_RXINTB 0x04
154 #define INTR_EXTINTA 0x08
155 #define INTR_TXINTA 0x10
156 #define INTR_RXINTA 0x20
170 static void handle_kbd_command(ESCCChannelState
*s
, int val
);
171 static int serial_can_receive(void *opaque
);
172 static void serial_receive_byte(ESCCChannelState
*s
, int ch
);
174 static void clear_queue(void *opaque
)
176 ESCCChannelState
*s
= opaque
;
177 ESCCSERIOQueue
*q
= &s
->queue
;
178 q
->rptr
= q
->wptr
= q
->count
= 0;
181 static void put_queue(void *opaque
, int b
)
183 ESCCChannelState
*s
= opaque
;
184 ESCCSERIOQueue
*q
= &s
->queue
;
186 trace_escc_put_queue(CHN_C(s
), b
);
187 if (q
->count
>= ESCC_SERIO_QUEUE_SIZE
) {
190 q
->data
[q
->wptr
] = b
;
191 if (++q
->wptr
== ESCC_SERIO_QUEUE_SIZE
) {
195 serial_receive_byte(s
, 0);
198 static uint32_t get_queue(void *opaque
)
200 ESCCChannelState
*s
= opaque
;
201 ESCCSERIOQueue
*q
= &s
->queue
;
207 val
= q
->data
[q
->rptr
];
208 if (++q
->rptr
== ESCC_SERIO_QUEUE_SIZE
) {
213 trace_escc_get_queue(CHN_C(s
), val
);
215 serial_receive_byte(s
, 0);
219 static int escc_update_irq_chn(ESCCChannelState
*s
)
221 if ((((s
->wregs
[W_INTR
] & INTR_TXINT
) && (s
->txint
== 1)) ||
222 // tx ints enabled, pending
223 ((((s
->wregs
[W_INTR
] & INTR_RXMODEMSK
) == INTR_RXINT1ST
) ||
224 ((s
->wregs
[W_INTR
] & INTR_RXMODEMSK
) == INTR_RXINTALL
)) &&
225 s
->rxint
== 1) || // rx ints enabled, pending
226 ((s
->wregs
[W_EXTINT
] & EXTINT_BRKINT
) &&
227 (s
->rregs
[R_STATUS
] & STATUS_BRK
)))) { // break int e&p
233 static void escc_update_irq(ESCCChannelState
*s
)
237 irq
= escc_update_irq_chn(s
);
238 irq
|= escc_update_irq_chn(s
->otherchn
);
240 trace_escc_update_irq(irq
);
241 qemu_set_irq(s
->irq
, irq
);
244 static void escc_reset_chn(ESCCChannelState
*s
)
249 for (i
= 0; i
< ESCC_SERIAL_REGS
; i
++) {
253 s
->wregs
[W_TXCTRL1
] = TXCTRL1_1STOP
; // 1X divisor, 1 stop bit, no parity
254 s
->wregs
[W_MINTR
] = MINTR_RST_ALL
;
255 s
->wregs
[W_CLOCK
] = CLOCK_TRXC
; // Synch mode tx clock = TRxC
256 s
->wregs
[W_MISC2
] = MISC2_PLLDIS
; // PLL disabled
257 s
->wregs
[W_EXTINT
] = EXTINT_DCD
| EXTINT_SYNCINT
| EXTINT_CTSINT
|
258 EXTINT_TXUNDRN
| EXTINT_BRKINT
; // Enable most interrupts
260 s
->rregs
[R_STATUS
] = STATUS_TXEMPTY
| STATUS_DCD
| STATUS_SYNC
|
261 STATUS_CTS
| STATUS_TXUNDRN
;
263 s
->rregs
[R_STATUS
] = STATUS_TXEMPTY
| STATUS_TXUNDRN
;
264 s
->rregs
[R_SPEC
] = SPEC_BITS8
| SPEC_ALLSENT
;
267 s
->rxint
= s
->txint
= 0;
268 s
->rxint_under_svc
= s
->txint_under_svc
= 0;
269 s
->e0_mode
= s
->led_mode
= s
->caps_lock_mode
= s
->num_lock_mode
= 0;
273 static void escc_reset(DeviceState
*d
)
275 ESCCState
*s
= ESCC(d
);
277 escc_reset_chn(&s
->chn
[0]);
278 escc_reset_chn(&s
->chn
[1]);
281 static inline void set_rxint(ESCCChannelState
*s
)
284 /* XXX: missing daisy chainnig: escc_chn_b rx should have a lower priority
285 than chn_a rx/tx/special_condition service*/
286 s
->rxint_under_svc
= 1;
287 if (s
->chn
== escc_chn_a
) {
288 s
->rregs
[R_INTR
] |= INTR_RXINTA
;
289 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
290 s
->otherchn
->rregs
[R_IVEC
] = IVEC_HIRXINTA
;
292 s
->otherchn
->rregs
[R_IVEC
] = IVEC_LORXINTA
;
294 s
->otherchn
->rregs
[R_INTR
] |= INTR_RXINTB
;
295 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
296 s
->rregs
[R_IVEC
] = IVEC_HIRXINTB
;
298 s
->rregs
[R_IVEC
] = IVEC_LORXINTB
;
303 static inline void set_txint(ESCCChannelState
*s
)
306 if (!s
->rxint_under_svc
) {
307 s
->txint_under_svc
= 1;
308 if (s
->chn
== escc_chn_a
) {
309 if (s
->wregs
[W_INTR
] & INTR_TXINT
) {
310 s
->rregs
[R_INTR
] |= INTR_TXINTA
;
312 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
313 s
->otherchn
->rregs
[R_IVEC
] = IVEC_HITXINTA
;
315 s
->otherchn
->rregs
[R_IVEC
] = IVEC_LOTXINTA
;
317 s
->rregs
[R_IVEC
] = IVEC_TXINTB
;
318 if (s
->wregs
[W_INTR
] & INTR_TXINT
) {
319 s
->otherchn
->rregs
[R_INTR
] |= INTR_TXINTB
;
326 static inline void clr_rxint(ESCCChannelState
*s
)
329 s
->rxint_under_svc
= 0;
330 if (s
->chn
== escc_chn_a
) {
331 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
332 s
->otherchn
->rregs
[R_IVEC
] = IVEC_HINOINT
;
334 s
->otherchn
->rregs
[R_IVEC
] = IVEC_LONOINT
;
335 s
->rregs
[R_INTR
] &= ~INTR_RXINTA
;
337 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
338 s
->rregs
[R_IVEC
] = IVEC_HINOINT
;
340 s
->rregs
[R_IVEC
] = IVEC_LONOINT
;
341 s
->otherchn
->rregs
[R_INTR
] &= ~INTR_RXINTB
;
348 static inline void clr_txint(ESCCChannelState
*s
)
351 s
->txint_under_svc
= 0;
352 if (s
->chn
== escc_chn_a
) {
353 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
354 s
->otherchn
->rregs
[R_IVEC
] = IVEC_HINOINT
;
356 s
->otherchn
->rregs
[R_IVEC
] = IVEC_LONOINT
;
357 s
->rregs
[R_INTR
] &= ~INTR_TXINTA
;
359 s
->otherchn
->rregs
[R_INTR
] &= ~INTR_TXINTB
;
360 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
361 s
->rregs
[R_IVEC
] = IVEC_HINOINT
;
363 s
->rregs
[R_IVEC
] = IVEC_LONOINT
;
364 s
->otherchn
->rregs
[R_INTR
] &= ~INTR_TXINTB
;
371 static void escc_update_parameters(ESCCChannelState
*s
)
373 int speed
, parity
, data_bits
, stop_bits
;
374 QEMUSerialSetParams ssp
;
376 if (!qemu_chr_fe_backend_connected(&s
->chr
) || s
->type
!= escc_serial
)
379 if (s
->wregs
[W_TXCTRL1
] & TXCTRL1_PAREN
) {
380 if (s
->wregs
[W_TXCTRL1
] & TXCTRL1_PAREV
)
387 if ((s
->wregs
[W_TXCTRL1
] & TXCTRL1_STPMSK
) == TXCTRL1_2STOP
)
391 switch (s
->wregs
[W_TXCTRL2
] & TXCTRL2_BITMSK
) {
406 speed
= s
->clock
/ ((s
->wregs
[W_BRGLO
] | (s
->wregs
[W_BRGHI
] << 8)) + 2);
407 switch (s
->wregs
[W_TXCTRL1
] & TXCTRL1_CLKMSK
) {
423 ssp
.data_bits
= data_bits
;
424 ssp
.stop_bits
= stop_bits
;
425 trace_escc_update_parameters(CHN_C(s
), speed
, parity
, data_bits
, stop_bits
);
426 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
429 static void escc_mem_write(void *opaque
, hwaddr addr
,
430 uint64_t val
, unsigned size
)
432 ESCCState
*serial
= opaque
;
438 saddr
= (addr
>> serial
->it_shift
) & 1;
439 channel
= (addr
>> (serial
->it_shift
+ 1)) & 1;
440 s
= &serial
->chn
[channel
];
443 trace_escc_mem_writeb_ctrl(CHN_C(s
), s
->reg
, val
& 0xff);
447 newreg
= val
& CMD_PTR_MASK
;
457 if (s
->rxint_under_svc
) {
458 s
->rxint_under_svc
= 0;
462 } else if (s
->txint_under_svc
) {
463 s
->txint_under_svc
= 0;
471 case W_INTR
... W_RXCTRL
:
472 case W_SYNC1
... W_TXBUF
:
473 case W_MISC1
... W_CLOCK
:
474 case W_MISC2
... W_EXTINT
:
475 s
->wregs
[s
->reg
] = val
;
479 s
->wregs
[s
->reg
] = val
;
480 escc_update_parameters(s
);
484 s
->wregs
[s
->reg
] = val
;
485 s
->rregs
[s
->reg
] = val
;
486 escc_update_parameters(s
);
489 switch (val
& MINTR_RST_MASK
) {
494 escc_reset_chn(&serial
->chn
[0]);
497 escc_reset_chn(&serial
->chn
[1]);
500 escc_reset(DEVICE(serial
));
513 trace_escc_mem_writeb_data(CHN_C(s
), val
);
515 * Lower the irq when data is written to the Tx buffer and no other
516 * interrupts are currently pending. The irq will be raised again once
517 * the Tx buffer becomes empty below.
522 if (s
->wregs
[W_TXCTRL2
] & TXCTRL2_TXEN
) { // tx enabled
523 if (qemu_chr_fe_backend_connected(&s
->chr
)) {
524 /* XXX this blocks entire thread. Rewrite to use
525 * qemu_chr_fe_write and background I/O callbacks */
526 qemu_chr_fe_write_all(&s
->chr
, &s
->tx
, 1);
527 } else if (s
->type
== escc_kbd
&& !s
->disabled
) {
528 handle_kbd_command(s
, val
);
531 s
->rregs
[R_STATUS
] |= STATUS_TXEMPTY
; // Tx buffer empty
532 s
->rregs
[R_SPEC
] |= SPEC_ALLSENT
; // All sent
540 static uint64_t escc_mem_read(void *opaque
, hwaddr addr
,
543 ESCCState
*serial
= opaque
;
549 saddr
= (addr
>> serial
->it_shift
) & 1;
550 channel
= (addr
>> (serial
->it_shift
+ 1)) & 1;
551 s
= &serial
->chn
[channel
];
554 trace_escc_mem_readb_ctrl(CHN_C(s
), s
->reg
, s
->rregs
[s
->reg
]);
555 ret
= s
->rregs
[s
->reg
];
559 s
->rregs
[R_STATUS
] &= ~STATUS_RXAV
;
561 if (s
->type
== escc_kbd
|| s
->type
== escc_mouse
) {
566 trace_escc_mem_readb_data(CHN_C(s
), ret
);
567 qemu_chr_fe_accept_input(&s
->chr
);
575 static const MemoryRegionOps escc_mem_ops
= {
576 .read
= escc_mem_read
,
577 .write
= escc_mem_write
,
578 .endianness
= DEVICE_NATIVE_ENDIAN
,
580 .min_access_size
= 1,
581 .max_access_size
= 1,
585 static int serial_can_receive(void *opaque
)
587 ESCCChannelState
*s
= opaque
;
590 if (((s
->wregs
[W_RXCTRL
] & RXCTRL_RXEN
) == 0) // Rx not enabled
591 || ((s
->rregs
[R_STATUS
] & STATUS_RXAV
) == STATUS_RXAV
))
592 // char already available
599 static void serial_receive_byte(ESCCChannelState
*s
, int ch
)
601 trace_escc_serial_receive_byte(CHN_C(s
), ch
);
602 s
->rregs
[R_STATUS
] |= STATUS_RXAV
;
607 static void serial_receive_break(ESCCChannelState
*s
)
609 s
->rregs
[R_STATUS
] |= STATUS_BRK
;
613 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
)
615 ESCCChannelState
*s
= opaque
;
616 serial_receive_byte(s
, buf
[0]);
619 static void serial_event(void *opaque
, int event
)
621 ESCCChannelState
*s
= opaque
;
622 if (event
== CHR_EVENT_BREAK
)
623 serial_receive_break(s
);
626 static const VMStateDescription vmstate_escc_chn
= {
629 .minimum_version_id
= 1,
630 .fields
= (VMStateField
[]) {
631 VMSTATE_UINT32(vmstate_dummy
, ESCCChannelState
),
632 VMSTATE_UINT32(reg
, ESCCChannelState
),
633 VMSTATE_UINT32(rxint
, ESCCChannelState
),
634 VMSTATE_UINT32(txint
, ESCCChannelState
),
635 VMSTATE_UINT32(rxint_under_svc
, ESCCChannelState
),
636 VMSTATE_UINT32(txint_under_svc
, ESCCChannelState
),
637 VMSTATE_UINT8(rx
, ESCCChannelState
),
638 VMSTATE_UINT8(tx
, ESCCChannelState
),
639 VMSTATE_BUFFER(wregs
, ESCCChannelState
),
640 VMSTATE_BUFFER(rregs
, ESCCChannelState
),
641 VMSTATE_END_OF_LIST()
645 static const VMStateDescription vmstate_escc
= {
648 .minimum_version_id
= 1,
649 .fields
= (VMStateField
[]) {
650 VMSTATE_STRUCT_ARRAY(chn
, ESCCState
, 2, 2, vmstate_escc_chn
,
652 VMSTATE_END_OF_LIST()
656 static void sunkbd_handle_event(DeviceState
*dev
, QemuConsole
*src
,
659 ESCCChannelState
*s
= (ESCCChannelState
*)dev
;
663 assert(evt
->type
== INPUT_EVENT_KIND_KEY
);
664 key
= evt
->u
.key
.data
;
665 qcode
= qemu_input_key_value_to_qcode(key
->key
);
666 trace_escc_sunkbd_event_in(qcode
, QKeyCode_str(qcode
),
669 if (qcode
== Q_KEY_CODE_CAPS_LOCK
) {
671 s
->caps_lock_mode
^= 1;
672 if (s
->caps_lock_mode
== 2) {
673 return; /* Drop second press */
676 s
->caps_lock_mode
^= 2;
677 if (s
->caps_lock_mode
== 3) {
678 return; /* Drop first release */
683 if (qcode
== Q_KEY_CODE_NUM_LOCK
) {
685 s
->num_lock_mode
^= 1;
686 if (s
->num_lock_mode
== 2) {
687 return; /* Drop second press */
690 s
->num_lock_mode
^= 2;
691 if (s
->num_lock_mode
== 3) {
692 return; /* Drop first release */
697 if (qcode
> qemu_input_map_qcode_to_sun_len
) {
701 keycode
= qemu_input_map_qcode_to_sun
[qcode
];
705 trace_escc_sunkbd_event_out(keycode
);
706 put_queue(s
, keycode
);
709 static QemuInputHandler sunkbd_handler
= {
710 .name
= "sun keyboard",
711 .mask
= INPUT_EVENT_MASK_KEY
,
712 .event
= sunkbd_handle_event
,
715 static void handle_kbd_command(ESCCChannelState
*s
, int val
)
717 trace_escc_kbd_command(val
);
718 if (s
->led_mode
) { // Ignore led byte
723 case 1: // Reset, return type code
726 put_queue(s
, 4); // Type 4
729 case 0xe: // Set leds
732 case 7: // Query layout
736 put_queue(s
, 0x21); /* en-us layout */
743 static void sunmouse_event(void *opaque
,
744 int dx
, int dy
, int dz
, int buttons_state
)
746 ESCCChannelState
*s
= opaque
;
749 trace_escc_sunmouse_event(dx
, dy
, buttons_state
);
750 ch
= 0x80 | 0x7; /* protocol start byte, no buttons pressed */
752 if (buttons_state
& MOUSE_EVENT_LBUTTON
)
754 if (buttons_state
& MOUSE_EVENT_MBUTTON
)
756 if (buttons_state
& MOUSE_EVENT_RBUTTON
)
768 put_queue(s
, ch
& 0xff);
777 put_queue(s
, ch
& 0xff);
779 // MSC protocol specify two extra motion bytes
785 static void escc_init1(Object
*obj
)
787 ESCCState
*s
= ESCC(obj
);
788 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
791 for (i
= 0; i
< 2; i
++) {
792 sysbus_init_irq(dev
, &s
->chn
[i
].irq
);
793 s
->chn
[i
].chn
= 1 - i
;
795 s
->chn
[0].otherchn
= &s
->chn
[1];
796 s
->chn
[1].otherchn
= &s
->chn
[0];
798 sysbus_init_mmio(dev
, &s
->mmio
);
801 static void escc_realize(DeviceState
*dev
, Error
**errp
)
803 ESCCState
*s
= ESCC(dev
);
806 s
->chn
[0].disabled
= s
->disabled
;
807 s
->chn
[1].disabled
= s
->disabled
;
809 memory_region_init_io(&s
->mmio
, OBJECT(dev
), &escc_mem_ops
, s
, "escc",
810 ESCC_SIZE
<< s
->it_shift
);
812 for (i
= 0; i
< 2; i
++) {
813 if (qemu_chr_fe_backend_connected(&s
->chn
[i
].chr
)) {
814 s
->chn
[i
].clock
= s
->frequency
/ 2;
815 qemu_chr_fe_set_handlers(&s
->chn
[i
].chr
, serial_can_receive
,
816 serial_receive1
, serial_event
, NULL
,
817 &s
->chn
[i
], NULL
, true);
821 if (s
->chn
[0].type
== escc_mouse
) {
822 qemu_add_mouse_event_handler(sunmouse_event
, &s
->chn
[0], 0,
825 if (s
->chn
[1].type
== escc_kbd
) {
826 s
->chn
[1].hs
= qemu_input_handler_register((DeviceState
*)(&s
->chn
[1]),
831 static Property escc_properties
[] = {
832 DEFINE_PROP_UINT32("frequency", ESCCState
, frequency
, 0),
833 DEFINE_PROP_UINT32("it_shift", ESCCState
, it_shift
, 0),
834 DEFINE_PROP_UINT32("disabled", ESCCState
, disabled
, 0),
835 DEFINE_PROP_UINT32("chnBtype", ESCCState
, chn
[0].type
, 0),
836 DEFINE_PROP_UINT32("chnAtype", ESCCState
, chn
[1].type
, 0),
837 DEFINE_PROP_CHR("chrB", ESCCState
, chn
[0].chr
),
838 DEFINE_PROP_CHR("chrA", ESCCState
, chn
[1].chr
),
839 DEFINE_PROP_END_OF_LIST(),
842 static void escc_class_init(ObjectClass
*klass
, void *data
)
844 DeviceClass
*dc
= DEVICE_CLASS(klass
);
846 dc
->reset
= escc_reset
;
847 dc
->realize
= escc_realize
;
848 dc
->vmsd
= &vmstate_escc
;
849 dc
->props
= escc_properties
;
850 set_bit(DEVICE_CATEGORY_INPUT
, dc
->categories
);
853 static const TypeInfo escc_info
= {
855 .parent
= TYPE_SYS_BUS_DEVICE
,
856 .instance_size
= sizeof(ESCCState
),
857 .instance_init
= escc_init1
,
858 .class_init
= escc_class_init
,
861 static void escc_register_types(void)
863 type_register_static(&escc_info
);
866 type_init(escc_register_types
)