hw/char/ipoctal232.c

   1 /*
   2  * QEMU GE IP-Octal 232 IndustryPack emulation
   3  *
   4  * Copyright (C) 2012 Igalia, S.L.
   5  * Author: Alberto Garcia <agarcia@igalia.com>
   6  *
   7  * This code is licensed under the GNU GPL v2 or (at your option) any
   8  * later version.
   9  */
  10
  11 #include "hw/ipack/ipack.h"
  12 #include "qemu/bitops.h"
  13 #include "sysemu/char.h"
  14
  15 /* #define DEBUG_IPOCTAL */
  16
  17 #ifdef DEBUG_IPOCTAL
  18 #define DPRINTF2(fmt, ...) \
  19     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  20 #else
  21 #define DPRINTF2(fmt, ...) do { } while (0)
  22 #endif
  23
  24 #define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__)
  25
  26 #define RX_FIFO_SIZE 3
  27
  28 /* The IP-Octal has 8 channels (a-h)
  29    divided into 4 blocks (A-D) */
  30 #define N_CHANNELS 8
  31 #define N_BLOCKS   4
  32
  33 #define REG_MRa  0x01
  34 #define REG_MRb  0x11
  35 #define REG_SRa  0x03
  36 #define REG_SRb  0x13
  37 #define REG_CSRa 0x03
  38 #define REG_CSRb 0x13
  39 #define REG_CRa  0x05
  40 #define REG_CRb  0x15
  41 #define REG_RHRa 0x07
  42 #define REG_RHRb 0x17
  43 #define REG_THRa 0x07
  44 #define REG_THRb 0x17
  45 #define REG_ACR  0x09
  46 #define REG_ISR  0x0B
  47 #define REG_IMR  0x0B
  48 #define REG_OPCR 0x1B
  49
  50 #define CR_ENABLE_RX    BIT(0)
  51 #define CR_DISABLE_RX   BIT(1)
  52 #define CR_ENABLE_TX    BIT(2)
  53 #define CR_DISABLE_TX   BIT(3)
  54 #define CR_CMD(cr)      ((cr) >> 4)
  55 #define CR_NO_OP        0
  56 #define CR_RESET_MR     1
  57 #define CR_RESET_RX     2
  58 #define CR_RESET_TX     3
  59 #define CR_RESET_ERR    4
  60 #define CR_RESET_BRKINT 5
  61 #define CR_START_BRK    6
  62 #define CR_STOP_BRK     7
  63 #define CR_ASSERT_RTSN  8
  64 #define CR_NEGATE_RTSN  9
  65 #define CR_TIMEOUT_ON   10
  66 #define CR_TIMEOUT_OFF  12
  67
  68 #define SR_RXRDY   BIT(0)
  69 #define SR_FFULL   BIT(1)
  70 #define SR_TXRDY   BIT(2)
  71 #define SR_TXEMT   BIT(3)
  72 #define SR_OVERRUN BIT(4)
  73 #define SR_PARITY  BIT(5)
  74 #define SR_FRAMING BIT(6)
  75 #define SR_BREAK   BIT(7)
  76
  77 #define ISR_TXRDYA BIT(0)
  78 #define ISR_RXRDYA BIT(1)
  79 #define ISR_BREAKA BIT(2)
  80 #define ISR_CNTRDY BIT(3)
  81 #define ISR_TXRDYB BIT(4)
  82 #define ISR_RXRDYB BIT(5)
  83 #define ISR_BREAKB BIT(6)
  84 #define ISR_MPICHG BIT(7)
  85 #define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0))
  86 #define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1))
  87 #define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2))
  88
  89 typedef struct IPOctalState IPOctalState;
  90 typedef struct SCC2698Channel SCC2698Channel;
  91 typedef struct SCC2698Block SCC2698Block;
  92
  93 struct SCC2698Channel {
  94     IPOctalState *ipoctal;
  95     CharDriverState *dev;
  96     bool rx_enabled;
  97     uint8_t mr[2];
  98     uint8_t mr_idx;
  99     uint8_t sr;
 100     uint8_t rhr[RX_FIFO_SIZE];
 101     uint8_t rhr_idx;
 102     uint8_t rx_pending;
 103 };
 104
 105 struct SCC2698Block {
 106     uint8_t imr;
 107     uint8_t isr;
 108 };
 109
 110 struct IPOctalState {
 111     IPackDevice parent_obj;
 112
 113     SCC2698Channel ch[N_CHANNELS];
 114     SCC2698Block blk[N_BLOCKS];
 115     uint8_t irq_vector;
 116 };
 117
 118 #define TYPE_IPOCTAL "ipoctal232"
 119
 120 #define IPOCTAL(obj) \
 121     OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL)
 122
 123 static const VMStateDescription vmstate_scc2698_channel = {
 124     .name = "scc2698_channel",
 125     .version_id = 1,
 126     .minimum_version_id = 1,
 127     .minimum_version_id_old = 1,
 128     .fields      = (VMStateField[]) {
 129         VMSTATE_BOOL(rx_enabled, SCC2698Channel),
 130         VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2),
 131         VMSTATE_UINT8(mr_idx, SCC2698Channel),
 132         VMSTATE_UINT8(sr, SCC2698Channel),
 133         VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE),
 134         VMSTATE_UINT8(rhr_idx, SCC2698Channel),
 135         VMSTATE_UINT8(rx_pending, SCC2698Channel),
 136         VMSTATE_END_OF_LIST()
 137     }
 138 };
 139
 140 static const VMStateDescription vmstate_scc2698_block = {
 141     .name = "scc2698_block",
 142     .version_id = 1,
 143     .minimum_version_id = 1,
 144     .minimum_version_id_old = 1,
 145     .fields      = (VMStateField[]) {
 146         VMSTATE_UINT8(imr, SCC2698Block),
 147         VMSTATE_UINT8(isr, SCC2698Block),
 148         VMSTATE_END_OF_LIST()
 149     }
 150 };
 151
 152 static const VMStateDescription vmstate_ipoctal = {
 153     .name = "ipoctal232",
 154     .version_id = 1,
 155     .minimum_version_id = 1,
 156     .minimum_version_id_old = 1,
 157     .fields      = (VMStateField[]) {
 158         VMSTATE_IPACK_DEVICE(parent_obj, IPOctalState),
 159         VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1,
 160                              vmstate_scc2698_channel, SCC2698Channel),
 161         VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1,
 162                              vmstate_scc2698_block, SCC2698Block),
 163         VMSTATE_UINT8(irq_vector, IPOctalState),
 164         VMSTATE_END_OF_LIST()
 165     }
 166 };
 167
 168 /* data[10] is 0x0C, not 0x0B as the doc says */
 169 static const uint8_t id_prom_data[] = {
 170     0x49, 0x50, 0x41, 0x43, 0xF0, 0x22,
 171     0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC
 172 };
 173
 174 static void update_irq(IPOctalState *dev, unsigned block)
 175 {
 176     IPackDevice *idev = IPACK_DEVICE(dev);
 177     /* Blocks A and B interrupt on INT0#, C and D on INT1#.
 178        Thus, to get the status we have to check two blocks. */
 179     SCC2698Block *blk0 = &dev->blk[block];
 180     SCC2698Block *blk1 = &dev->blk[block^1];
 181     unsigned intno = block / 2;
 182
 183     if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) {
 184         qemu_irq_raise(idev->irq[intno]);
 185     } else {
 186         qemu_irq_lower(idev->irq[intno]);
 187     }
 188 }
 189
 190 static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val)
 191 {
 192     SCC2698Channel *ch = &dev->ch[channel];
 193     SCC2698Block *blk = &dev->blk[channel / 2];
 194
 195     DPRINTF("Write CR%c %u: ", channel + 'a', val);
 196
 197     /* The lower 4 bits are used to enable and disable Tx and Rx */
 198     if (val & CR_ENABLE_RX) {
 199         DPRINTF2("Rx on, ");
 200         ch->rx_enabled = true;
 201     }
 202     if (val & CR_DISABLE_RX) {
 203         DPRINTF2("Rx off, ");
 204         ch->rx_enabled = false;
 205     }
 206     if (val & CR_ENABLE_TX) {
 207         DPRINTF2("Tx on, ");
 208         ch->sr |= SR_TXRDY | SR_TXEMT;
 209         blk->isr |= ISR_TXRDY(channel);
 210     }
 211     if (val & CR_DISABLE_TX) {
 212         DPRINTF2("Tx off, ");
 213         ch->sr &= ~(SR_TXRDY | SR_TXEMT);
 214         blk->isr &= ~ISR_TXRDY(channel);
 215     }
 216
 217     DPRINTF2("cmd: ");
 218
 219     /* The rest of the bits implement different commands */
 220     switch (CR_CMD(val)) {
 221     case CR_NO_OP:
 222         DPRINTF2("none");
 223         break;
 224     case CR_RESET_MR:
 225         DPRINTF2("reset MR");
 226         ch->mr_idx = 0;
 227         break;
 228     case CR_RESET_RX:
 229         DPRINTF2("reset Rx");
 230         ch->rx_enabled = false;
 231         ch->rx_pending = 0;
 232         ch->sr &= ~SR_RXRDY;
 233         blk->isr &= ~ISR_RXRDY(channel);
 234         break;
 235     case CR_RESET_TX:
 236         DPRINTF2("reset Tx");
 237         ch->sr &= ~(SR_TXRDY | SR_TXEMT);
 238         blk->isr &= ~ISR_TXRDY(channel);
 239         break;
 240     case CR_RESET_ERR:
 241         DPRINTF2("reset err");
 242         ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK);
 243         break;
 244     case CR_RESET_BRKINT:
 245         DPRINTF2("reset brk ch int");
 246         blk->isr &= ~(ISR_BREAKA | ISR_BREAKB);
 247         break;
 248     default:
 249         DPRINTF2("unsupported 0x%x", CR_CMD(val));
 250     }
 251
 252     DPRINTF2("\n");
 253 }
 254
 255 static uint16_t io_read(IPackDevice *ip, uint8_t addr)
 256 {
 257     IPOctalState *dev = IPOCTAL(ip);
 258     uint16_t ret = 0;
 259     /* addr[7:6]: block   (A-D)
 260        addr[7:5]: channel (a-h)
 261        addr[5:0]: register */
 262     unsigned block = addr >> 5;
 263     unsigned channel = addr >> 4;
 264     /* Big endian, accessed using 8-bit bytes at odd locations */
 265     unsigned offset = (addr & 0x1F) ^ 1;
 266     SCC2698Channel *ch = &dev->ch[channel];
 267     SCC2698Block *blk = &dev->blk[block];
 268     uint8_t old_isr = blk->isr;
 269
 270     switch (offset) {
 271
 272     case REG_MRa:
 273     case REG_MRb:
 274         ret = ch->mr[ch->mr_idx];
 275         DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret);
 276         ch->mr_idx = 1;
 277         break;
 278
 279     case REG_SRa:
 280     case REG_SRb:
 281         ret = ch->sr;
 282         DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret);
 283         break;
 284
 285     case REG_RHRa:
 286     case REG_RHRb:
 287         ret = ch->rhr[ch->rhr_idx];
 288         if (ch->rx_pending > 0) {
 289             ch->rx_pending--;
 290             if (ch->rx_pending == 0) {
 291                 ch->sr &= ~SR_RXRDY;
 292                 blk->isr &= ~ISR_RXRDY(channel);
 293                 if (ch->dev) {
 294                     qemu_chr_accept_input(ch->dev);
 295                 }
 296             } else {
 297                 ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
 298             }
 299             if (ch->sr & SR_BREAK) {
 300                 ch->sr &= ~SR_BREAK;
 301                 blk->isr |= ISR_BREAK(channel);
 302             }
 303         }
 304         DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret);
 305         break;
 306
 307     case REG_ISR:
 308         ret = blk->isr;
 309         DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret);
 310         break;
 311
 312     default:
 313         DPRINTF("Read unknown/unsupported register 0x%02x\n", offset);
 314     }
 315
 316     if (old_isr != blk->isr) {
 317         update_irq(dev, block);
 318     }
 319
 320     return ret;
 321 }
 322
 323 static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
 324 {
 325     IPOctalState *dev = IPOCTAL(ip);
 326     unsigned reg = val & 0xFF;
 327     /* addr[7:6]: block   (A-D)
 328        addr[7:5]: channel (a-h)
 329        addr[5:0]: register */
 330     unsigned block = addr >> 5;
 331     unsigned channel = addr >> 4;
 332     /* Big endian, accessed using 8-bit bytes at odd locations */
 333     unsigned offset = (addr & 0x1F) ^ 1;
 334     SCC2698Channel *ch = &dev->ch[channel];
 335     SCC2698Block *blk = &dev->blk[block];
 336     uint8_t old_isr = blk->isr;
 337     uint8_t old_imr = blk->imr;
 338
 339     switch (offset) {
 340
 341     case REG_MRa:
 342     case REG_MRb:
 343         ch->mr[ch->mr_idx] = reg;
 344         DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg);
 345         ch->mr_idx = 1;
 346         break;
 347
 348     /* Not implemented */
 349     case REG_CSRa:
 350     case REG_CSRb:
 351         DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg);
 352         break;
 353
 354     case REG_CRa:
 355     case REG_CRb:
 356         write_cr(dev, channel, reg);
 357         break;
 358
 359     case REG_THRa:
 360     case REG_THRb:
 361         if (ch->sr & SR_TXRDY) {
 362             DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
 363             if (ch->dev) {
 364                 uint8_t thr = reg;
 365                 qemu_chr_fe_write(ch->dev, &thr, 1);
 366             }
 367         } else {
 368             DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
 369         }
 370         break;
 371
 372     /* Not implemented */
 373     case REG_ACR:
 374         DPRINTF("Write ACR%c 0x%x\n", block + 'A', val);
 375         break;
 376
 377     case REG_IMR:
 378         DPRINTF("Write IMR%c 0x%x\n", block + 'A', val);
 379         blk->imr = reg;
 380         break;
 381
 382     /* Not implemented */
 383     case REG_OPCR:
 384         DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val);
 385         break;
 386
 387     default:
 388         DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val);
 389     }
 390
 391     if (old_isr != blk->isr || old_imr != blk->imr) {
 392         update_irq(dev, block);
 393     }
 394 }
 395
 396 static uint16_t id_read(IPackDevice *ip, uint8_t addr)
 397 {
 398     uint16_t ret = 0;
 399     unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */
 400
 401     if (pos < ARRAY_SIZE(id_prom_data)) {
 402         ret = id_prom_data[pos];
 403     } else {
 404         DPRINTF("Attempt to read unavailable PROM data at 0x%x\n",  addr);
 405     }
 406
 407     return ret;
 408 }
 409
 410 static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val)
 411 {
 412     IPOctalState *dev = IPOCTAL(ip);
 413     if (addr == 1) {
 414         DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
 415         dev->irq_vector = val; /* Undocumented, but the hw works like that */
 416     } else {
 417         DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
 418     }
 419 }
 420
 421 static uint16_t int_read(IPackDevice *ip, uint8_t addr)
 422 {
 423     IPOctalState *dev = IPOCTAL(ip);
 424     /* Read address 0 to ACK INT0# and address 2 to ACK INT1# */
 425     if (addr != 0 && addr != 2) {
 426         DPRINTF("Attempt to read from 0x%x\n", addr);
 427         return 0;
 428     } else {
 429         /* Update interrupts if necessary */
 430         update_irq(dev, addr);
 431         return dev->irq_vector;
 432     }
 433 }
 434
 435 static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val)
 436 {
 437     DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
 438 }
 439
 440 static uint16_t mem_read16(IPackDevice *ip, uint32_t addr)
 441 {
 442     DPRINTF("Attempt to read from 0x%x\n", addr);
 443     return 0;
 444 }
 445
 446 static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val)
 447 {
 448     DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
 449 }
 450
 451 static uint8_t mem_read8(IPackDevice *ip, uint32_t addr)
 452 {
 453     DPRINTF("Attempt to read from 0x%x\n", addr);
 454     return 0;
 455 }
 456
 457 static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val)
 458 {
 459     IPOctalState *dev = IPOCTAL(ip);
 460     if (addr == 1) {
 461         DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
 462         dev->irq_vector = val;
 463     } else {
 464         DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
 465     }
 466 }
 467
 468 static int hostdev_can_receive(void *opaque)
 469 {
 470     SCC2698Channel *ch = opaque;
 471     int available_bytes = RX_FIFO_SIZE - ch->rx_pending;
 472     return ch->rx_enabled ? available_bytes : 0;
 473 }
 474
 475 static void hostdev_receive(void *opaque, const uint8_t *buf, int size)
 476 {
 477     SCC2698Channel *ch = opaque;
 478     IPOctalState *dev = ch->ipoctal;
 479     unsigned pos = ch->rhr_idx + ch->rx_pending;
 480     int i;
 481
 482     assert(size + ch->rx_pending <= RX_FIFO_SIZE);
 483
 484     /* Copy data to the RxFIFO */
 485     for (i = 0; i < size; i++) {
 486         pos %= RX_FIFO_SIZE;
 487         ch->rhr[pos++] = buf[i];
 488     }
 489
 490     ch->rx_pending += size;
 491
 492     /* If the RxFIFO was empty raise an interrupt */
 493     if (!(ch->sr & SR_RXRDY)) {
 494         unsigned block, channel = 0;
 495         /* Find channel number to update the ISR register */
 496         while (&dev->ch[channel] != ch) {
 497             channel++;
 498         }
 499         block = channel / 2;
 500         dev->blk[block].isr |= ISR_RXRDY(channel);
 501         ch->sr |= SR_RXRDY;
 502         update_irq(dev, block);
 503     }
 504 }
 505
 506 static void hostdev_event(void *opaque, int event)
 507 {
 508     SCC2698Channel *ch = opaque;
 509     switch (event) {
 510     case CHR_EVENT_OPENED:
 511         DPRINTF("Device %s opened\n", ch->dev->label);
 512         break;
 513     case CHR_EVENT_BREAK: {
 514         uint8_t zero = 0;
 515         DPRINTF("Device %s received break\n", ch->dev->label);
 516
 517         if (!(ch->sr & SR_BREAK)) {
 518             IPOctalState *dev = ch->ipoctal;
 519             unsigned block, channel = 0;
 520
 521             while (&dev->ch[channel] != ch) {
 522                 channel++;
 523             }
 524             block = channel / 2;
 525
 526             ch->sr |= SR_BREAK;
 527             dev->blk[block].isr |= ISR_BREAK(channel);
 528         }
 529
 530         /* Put a zero character in the buffer */
 531         hostdev_receive(ch, &zero, 1);
 532     }
 533         break;
 534     default:
 535         DPRINTF("Device %s received event %d\n", ch->dev->label, event);
 536     }
 537 }
 538
 539 static void ipoctal_realize(DeviceState *dev, Error **errp)
 540 {
 541     IPOctalState *s = IPOCTAL(dev);
 542     unsigned i;
 543
 544     for (i = 0; i < N_CHANNELS; i++) {
 545         SCC2698Channel *ch = &s->ch[i];
 546         ch->ipoctal = s;
 547
 548         /* Redirect IP-Octal channels to host character devices */
 549         if (ch->dev) {
 550             qemu_chr_add_handlers(ch->dev, hostdev_can_receive,
 551                                   hostdev_receive, hostdev_event, ch);
 552             DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label);
 553         } else {
 554             DPRINTF("Could not redirect channel %u, no chardev set\n", i);
 555         }
 556     }
 557 }
 558
 559 static Property ipoctal_properties[] = {
 560     DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev),
 561     DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev),
 562     DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev),
 563     DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev),
 564     DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev),
 565     DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev),
 566     DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev),
 567     DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev),
 568     DEFINE_PROP_END_OF_LIST(),
 569 };
 570
 571 static void ipoctal_class_init(ObjectClass *klass, void *data)
 572 {
 573     DeviceClass *dc = DEVICE_CLASS(klass);
 574     IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass);
 575
 576     ic->realize     = ipoctal_realize;
 577     ic->io_read     = io_read;
 578     ic->io_write    = io_write;
 579     ic->id_read     = id_read;
 580     ic->id_write    = id_write;
 581     ic->int_read    = int_read;
 582     ic->int_write   = int_write;
 583     ic->mem_read16  = mem_read16;
 584     ic->mem_write16 = mem_write16;
 585     ic->mem_read8   = mem_read8;
 586     ic->mem_write8  = mem_write8;
 587
 588     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 589     dc->desc    = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
 590     dc->props   = ipoctal_properties;
 591     dc->vmsd    = &vmstate_ipoctal;
 592 }
 593
 594 static const TypeInfo ipoctal_info = {
 595     .name          = TYPE_IPOCTAL,
 596     .parent        = TYPE_IPACK_DEVICE,
 597     .instance_size = sizeof(IPOctalState),
 598     .class_init    = ipoctal_class_init,
 599 };
 600
 601 static void ipoctal_register_types(void)
 602 {
 603     type_register_static(&ipoctal_info);
 604 }
 605
 606 type_init(ipoctal_register_types)