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x86: Clean up includes
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1 /*
2 * QEMU 16550A UART emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 /* see docs/specs/pci-serial.txt */
27
28 #include "qemu/osdep.h"
29 #include "hw/char/serial.h"
30 #include "hw/pci/pci.h"
31
32 #define PCI_SERIAL_MAX_PORTS 4
33
34 typedef struct PCISerialState {
35 PCIDevice dev;
36 SerialState state;
37 uint8_t prog_if;
38 } PCISerialState;
39
40 typedef struct PCIMultiSerialState {
41 PCIDevice dev;
42 MemoryRegion iobar;
43 uint32_t ports;
44 char *name[PCI_SERIAL_MAX_PORTS];
45 SerialState state[PCI_SERIAL_MAX_PORTS];
46 uint32_t level[PCI_SERIAL_MAX_PORTS];
47 qemu_irq *irqs;
48 uint8_t prog_if;
49 } PCIMultiSerialState;
50
51 static void multi_serial_pci_exit(PCIDevice *dev);
52
53 static void serial_pci_realize(PCIDevice *dev, Error **errp)
54 {
55 PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
56 SerialState *s = &pci->state;
57 Error *err = NULL;
58
59 s->baudbase = 115200;
60 serial_realize_core(s, &err);
61 if (err != NULL) {
62 error_propagate(errp, err);
63 return;
64 }
65
66 pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
67 pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
68 s->irq = pci_allocate_irq(&pci->dev);
69
70 memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
71 pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
72 }
73
74 static void multi_serial_irq_mux(void *opaque, int n, int level)
75 {
76 PCIMultiSerialState *pci = opaque;
77 int i, pending = 0;
78
79 pci->level[n] = level;
80 for (i = 0; i < pci->ports; i++) {
81 if (pci->level[i]) {
82 pending = 1;
83 }
84 }
85 pci_set_irq(&pci->dev, pending);
86 }
87
88 static void multi_serial_pci_realize(PCIDevice *dev, Error **errp)
89 {
90 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
91 PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
92 SerialState *s;
93 Error *err = NULL;
94 int i, nr_ports = 0;
95
96 switch (pc->device_id) {
97 case 0x0003:
98 nr_ports = 2;
99 break;
100 case 0x0004:
101 nr_ports = 4;
102 break;
103 }
104 assert(nr_ports > 0);
105 assert(nr_ports <= PCI_SERIAL_MAX_PORTS);
106
107 pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
108 pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
109 memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports);
110 pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
111 pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
112 nr_ports);
113
114 for (i = 0; i < nr_ports; i++) {
115 s = pci->state + i;
116 s->baudbase = 115200;
117 serial_realize_core(s, &err);
118 if (err != NULL) {
119 error_propagate(errp, err);
120 multi_serial_pci_exit(dev);
121 return;
122 }
123 s->irq = pci->irqs[i];
124 pci->name[i] = g_strdup_printf("uart #%d", i+1);
125 memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
126 pci->name[i], 8);
127 memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
128 pci->ports++;
129 }
130 }
131
132 static void serial_pci_exit(PCIDevice *dev)
133 {
134 PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
135 SerialState *s = &pci->state;
136
137 serial_exit_core(s);
138 qemu_free_irq(s->irq);
139 }
140
141 static void multi_serial_pci_exit(PCIDevice *dev)
142 {
143 PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
144 SerialState *s;
145 int i;
146
147 for (i = 0; i < pci->ports; i++) {
148 s = pci->state + i;
149 serial_exit_core(s);
150 memory_region_del_subregion(&pci->iobar, &s->io);
151 g_free(pci->name[i]);
152 }
153 qemu_free_irqs(pci->irqs, pci->ports);
154 }
155
156 static const VMStateDescription vmstate_pci_serial = {
157 .name = "pci-serial",
158 .version_id = 1,
159 .minimum_version_id = 1,
160 .fields = (VMStateField[]) {
161 VMSTATE_PCI_DEVICE(dev, PCISerialState),
162 VMSTATE_STRUCT(state, PCISerialState, 0, vmstate_serial, SerialState),
163 VMSTATE_END_OF_LIST()
164 }
165 };
166
167 static const VMStateDescription vmstate_pci_multi_serial = {
168 .name = "pci-serial-multi",
169 .version_id = 1,
170 .minimum_version_id = 1,
171 .fields = (VMStateField[]) {
172 VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
173 VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
174 0, vmstate_serial, SerialState),
175 VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
176 VMSTATE_END_OF_LIST()
177 }
178 };
179
180 static Property serial_pci_properties[] = {
181 DEFINE_PROP_CHR("chardev", PCISerialState, state.chr),
182 DEFINE_PROP_UINT8("prog_if", PCISerialState, prog_if, 0x02),
183 DEFINE_PROP_END_OF_LIST(),
184 };
185
186 static Property multi_2x_serial_pci_properties[] = {
187 DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
188 DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
189 DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
190 DEFINE_PROP_END_OF_LIST(),
191 };
192
193 static Property multi_4x_serial_pci_properties[] = {
194 DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
195 DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
196 DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr),
197 DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr),
198 DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
199 DEFINE_PROP_END_OF_LIST(),
200 };
201
202 static void serial_pci_class_initfn(ObjectClass *klass, void *data)
203 {
204 DeviceClass *dc = DEVICE_CLASS(klass);
205 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
206 pc->realize = serial_pci_realize;
207 pc->exit = serial_pci_exit;
208 pc->vendor_id = PCI_VENDOR_ID_REDHAT;
209 pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL;
210 pc->revision = 1;
211 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
212 dc->vmsd = &vmstate_pci_serial;
213 dc->props = serial_pci_properties;
214 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
215 }
216
217 static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data)
218 {
219 DeviceClass *dc = DEVICE_CLASS(klass);
220 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
221 pc->realize = multi_serial_pci_realize;
222 pc->exit = multi_serial_pci_exit;
223 pc->vendor_id = PCI_VENDOR_ID_REDHAT;
224 pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
225 pc->revision = 1;
226 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
227 dc->vmsd = &vmstate_pci_multi_serial;
228 dc->props = multi_2x_serial_pci_properties;
229 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
230 }
231
232 static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
233 {
234 DeviceClass *dc = DEVICE_CLASS(klass);
235 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
236 pc->realize = multi_serial_pci_realize;
237 pc->exit = multi_serial_pci_exit;
238 pc->vendor_id = PCI_VENDOR_ID_REDHAT;
239 pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
240 pc->revision = 1;
241 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
242 dc->vmsd = &vmstate_pci_multi_serial;
243 dc->props = multi_4x_serial_pci_properties;
244 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
245 }
246
247 static const TypeInfo serial_pci_info = {
248 .name = "pci-serial",
249 .parent = TYPE_PCI_DEVICE,
250 .instance_size = sizeof(PCISerialState),
251 .class_init = serial_pci_class_initfn,
252 };
253
254 static const TypeInfo multi_2x_serial_pci_info = {
255 .name = "pci-serial-2x",
256 .parent = TYPE_PCI_DEVICE,
257 .instance_size = sizeof(PCIMultiSerialState),
258 .class_init = multi_2x_serial_pci_class_initfn,
259 };
260
261 static const TypeInfo multi_4x_serial_pci_info = {
262 .name = "pci-serial-4x",
263 .parent = TYPE_PCI_DEVICE,
264 .instance_size = sizeof(PCIMultiSerialState),
265 .class_init = multi_4x_serial_pci_class_initfn,
266 };
267
268 static void serial_pci_register_types(void)
269 {
270 type_register_static(&serial_pci_info);
271 type_register_static(&multi_2x_serial_pci_info);
272 type_register_static(&multi_4x_serial_pci_info);
273 }
274
275 type_init(serial_pci_register_types)