hw/char/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/char/serial.h"
  28 #include "chardev/char-serial.h"
  29 #include "qapi/error.h"
  30 #include "qemu/timer.h"
  31 #include "sysemu/reset.h"
  32 #include "qemu/error-report.h"
  33 #include "trace.h"
  34
  35 //#define DEBUG_SERIAL
  36
  37 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  38
  39 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  40 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  41 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  42 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  43
  44 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  45 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  46
  47 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  48 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  49 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  50 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  51 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  52
  53 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  54 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  55
  56 /*
  57  * These are the definitions for the Modem Control Register
  58  */
  59 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  60 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  61 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  62 #define UART_MCR_RTS    0x02    /* RTS complement */
  63 #define UART_MCR_DTR    0x01    /* DTR complement */
  64
  65 /*
  66  * These are the definitions for the Modem Status Register
  67  */
  68 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  69 #define UART_MSR_RI     0x40    /* Ring Indicator */
  70 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  71 #define UART_MSR_CTS    0x10    /* Clear to Send */
  72 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  73 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  74 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  75 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  76 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  77
  78 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  79 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  80 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  81 #define UART_LSR_FE     0x08    /* Frame error indicator */
  82 #define UART_LSR_PE     0x04    /* Parity error indicator */
  83 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  84 #define UART_LSR_DR     0x01    /* Receiver data ready */
  85 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  86
  87 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  88
  89 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  90 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  91 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  92 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  93
  94 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  95 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  96 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  97 #define UART_FCR_FE         0x01    /* FIFO Enable */
  98
  99 #define MAX_XMIT_RETRY      4
 100
 101 #ifdef DEBUG_SERIAL
 102 #define DPRINTF(fmt, ...) \
 103 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
 104 #else
 105 #define DPRINTF(fmt, ...) \
 106 do {} while (0)
 107 #endif
 108
 109 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 110 static void serial_xmit(SerialState *s);
 111
 112 static inline void recv_fifo_put(SerialState *s, uint8_t chr)
 113 {
 114     /* Receive overruns do not overwrite FIFO contents. */
 115     if (!fifo8_is_full(&s->recv_fifo)) {
 116         fifo8_push(&s->recv_fifo, chr);
 117     } else {
 118         s->lsr |= UART_LSR_OE;
 119     }
 120 }
 121
 122 static void serial_update_irq(SerialState *s)
 123 {
 124     uint8_t tmp_iir = UART_IIR_NO_INT;
 125
 126     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 127         tmp_iir = UART_IIR_RLSI;
 128     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 129         /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 130          * this is not in the specification but is observed on existing
 131          * hardware.  */
 132         tmp_iir = UART_IIR_CTI;
 133     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
 134                (!(s->fcr & UART_FCR_FE) ||
 135                 s->recv_fifo.num >= s->recv_fifo_itl)) {
 136         tmp_iir = UART_IIR_RDI;
 137     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 138         tmp_iir = UART_IIR_THRI;
 139     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 140         tmp_iir = UART_IIR_MSI;
 141     }
 142
 143     s->iir = tmp_iir | (s->iir & 0xF0);
 144
 145     if (tmp_iir != UART_IIR_NO_INT) {
 146         qemu_irq_raise(s->irq);
 147     } else {
 148         qemu_irq_lower(s->irq);
 149     }
 150 }
 151
 152 static void serial_update_parameters(SerialState *s)
 153 {
 154     float speed;
 155     int parity, data_bits, stop_bits, frame_size;
 156     QEMUSerialSetParams ssp;
 157
 158     /* Start bit. */
 159     frame_size = 1;
 160     if (s->lcr & 0x08) {
 161         /* Parity bit. */
 162         frame_size++;
 163         if (s->lcr & 0x10)
 164             parity = 'E';
 165         else
 166             parity = 'O';
 167     } else {
 168             parity = 'N';
 169     }
 170     if (s->lcr & 0x04) {
 171         stop_bits = 2;
 172     } else {
 173         stop_bits = 1;
 174     }
 175
 176     data_bits = (s->lcr & 0x03) + 5;
 177     frame_size += data_bits + stop_bits;
 178     /* Zero divisor should give about 3500 baud */
 179     speed = (s->divider == 0) ? 3500 : (float) s->baudbase / s->divider;
 180     ssp.speed = speed;
 181     ssp.parity = parity;
 182     ssp.data_bits = data_bits;
 183     ssp.stop_bits = stop_bits;
 184     s->char_transmit_time =  (NANOSECONDS_PER_SECOND / speed) * frame_size;
 185     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 186
 187     DPRINTF("speed=%.2f parity=%c data=%d stop=%d\n",
 188            speed, parity, data_bits, stop_bits);
 189 }
 190
 191 static void serial_update_msl(SerialState *s)
 192 {
 193     uint8_t omsr;
 194     int flags;
 195
 196     timer_del(s->modem_status_poll);
 197
 198     if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM,
 199                           &flags) == -ENOTSUP) {
 200         s->poll_msl = -1;
 201         return;
 202     }
 203
 204     omsr = s->msr;
 205
 206     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 207     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 208     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 209     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 210
 211     if (s->msr != omsr) {
 212          /* Set delta bits */
 213          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 214          /* UART_MSR_TERI only if change was from 1 -> 0 */
 215          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 216              s->msr &= ~UART_MSR_TERI;
 217          serial_update_irq(s);
 218     }
 219
 220     /* The real 16550A apparently has a 250ns response latency to line status changes.
 221        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 222
 223     if (s->poll_msl) {
 224         timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 225                   NANOSECONDS_PER_SECOND / 100);
 226     }
 227 }
 228
 229 static gboolean serial_watch_cb(GIOChannel *chan, GIOCondition cond,
 230                                 void *opaque)
 231 {
 232     SerialState *s = opaque;
 233     s->watch_tag = 0;
 234     serial_xmit(s);
 235     return FALSE;
 236 }
 237
 238 static void serial_xmit(SerialState *s)
 239 {
 240     do {
 241         assert(!(s->lsr & UART_LSR_TEMT));
 242         if (s->tsr_retry == 0) {
 243             assert(!(s->lsr & UART_LSR_THRE));
 244
 245             if (s->fcr & UART_FCR_FE) {
 246                 assert(!fifo8_is_empty(&s->xmit_fifo));
 247                 s->tsr = fifo8_pop(&s->xmit_fifo);
 248                 if (!s->xmit_fifo.num) {
 249                     s->lsr |= UART_LSR_THRE;
 250                 }
 251             } else {
 252                 s->tsr = s->thr;
 253                 s->lsr |= UART_LSR_THRE;
 254             }
 255             if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) {
 256                 s->thr_ipending = 1;
 257                 serial_update_irq(s);
 258             }
 259         }
 260
 261         if (s->mcr & UART_MCR_LOOP) {
 262             /* in loopback mode, say that we just received a char */
 263             serial_receive1(s, &s->tsr, 1);
 264         } else {
 265             int rc = qemu_chr_fe_write(&s->chr, &s->tsr, 1);
 266
 267             if ((rc == 0 ||
 268                  (rc == -1 && errno == EAGAIN)) &&
 269                 s->tsr_retry < MAX_XMIT_RETRY) {
 270                 assert(s->watch_tag == 0);
 271                 s->watch_tag =
 272                     qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 273                                           serial_watch_cb, s);
 274                 if (s->watch_tag > 0) {
 275                     s->tsr_retry++;
 276                     return;
 277                 }
 278             }
 279         }
 280         s->tsr_retry = 0;
 281
 282         /* Transmit another byte if it is already available. It is only
 283            possible when FIFO is enabled and not empty. */
 284     } while (!(s->lsr & UART_LSR_THRE));
 285
 286     s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 287     s->lsr |= UART_LSR_TEMT;
 288 }
 289
 290 /* Setter for FCR.
 291    is_load flag means, that value is set while loading VM state
 292    and interrupt should not be invoked */
 293 static void serial_write_fcr(SerialState *s, uint8_t val)
 294 {
 295     /* Set fcr - val only has the bits that are supposed to "stick" */
 296     s->fcr = val;
 297
 298     if (val & UART_FCR_FE) {
 299         s->iir |= UART_IIR_FE;
 300         /* Set recv_fifo trigger Level */
 301         switch (val & 0xC0) {
 302         case UART_FCR_ITL_1:
 303             s->recv_fifo_itl = 1;
 304             break;
 305         case UART_FCR_ITL_2:
 306             s->recv_fifo_itl = 4;
 307             break;
 308         case UART_FCR_ITL_3:
 309             s->recv_fifo_itl = 8;
 310             break;
 311         case UART_FCR_ITL_4:
 312             s->recv_fifo_itl = 14;
 313             break;
 314         }
 315     } else {
 316         s->iir &= ~UART_IIR_FE;
 317     }
 318 }
 319
 320 static void serial_update_tiocm(SerialState *s)
 321 {
 322     int flags;
 323
 324     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 325
 326     flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 327
 328     if (s->mcr & UART_MCR_RTS) {
 329         flags |= CHR_TIOCM_RTS;
 330     }
 331     if (s->mcr & UART_MCR_DTR) {
 332         flags |= CHR_TIOCM_DTR;
 333     }
 334
 335     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 336 }
 337
 338 static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
 339                                 unsigned size)
 340 {
 341     SerialState *s = opaque;
 342
 343     addr &= 7;
 344     trace_serial_ioport_write(addr, val);
 345     switch(addr) {
 346     default:
 347     case 0:
 348         if (s->lcr & UART_LCR_DLAB) {
 349             if (size == 1) {
 350                 s->divider = (s->divider & 0xff00) | val;
 351             } else {
 352                 s->divider = val;
 353             }
 354             serial_update_parameters(s);
 355         } else {
 356             s->thr = (uint8_t) val;
 357             if(s->fcr & UART_FCR_FE) {
 358                 /* xmit overruns overwrite data, so make space if needed */
 359                 if (fifo8_is_full(&s->xmit_fifo)) {
 360                     fifo8_pop(&s->xmit_fifo);
 361                 }
 362                 fifo8_push(&s->xmit_fifo, s->thr);
 363             }
 364             s->thr_ipending = 0;
 365             s->lsr &= ~UART_LSR_THRE;
 366             s->lsr &= ~UART_LSR_TEMT;
 367             serial_update_irq(s);
 368             if (s->tsr_retry == 0) {
 369                 serial_xmit(s);
 370             }
 371         }
 372         break;
 373     case 1:
 374         if (s->lcr & UART_LCR_DLAB) {
 375             s->divider = (s->divider & 0x00ff) | (val << 8);
 376             serial_update_parameters(s);
 377         } else {
 378             uint8_t changed = (s->ier ^ val) & 0x0f;
 379             s->ier = val & 0x0f;
 380             /* If the backend device is a real serial port, turn polling of the modem
 381              * status lines on physical port on or off depending on UART_IER_MSI state.
 382              */
 383             if ((changed & UART_IER_MSI) && s->poll_msl >= 0) {
 384                 if (s->ier & UART_IER_MSI) {
 385                      s->poll_msl = 1;
 386                      serial_update_msl(s);
 387                 } else {
 388                      timer_del(s->modem_status_poll);
 389                      s->poll_msl = 0;
 390                 }
 391             }
 392
 393             /* Turning on the THRE interrupt on IER can trigger the interrupt
 394              * if LSR.THRE=1, even if it had been masked before by reading IIR.
 395              * This is not in the datasheet, but Windows relies on it.  It is
 396              * unclear if THRE has to be resampled every time THRI becomes
 397              * 1, or only on the rising edge.  Bochs does the latter, and Windows
 398              * always toggles IER to all zeroes and back to all ones, so do the
 399              * same.
 400              *
 401              * If IER.THRI is zero, thr_ipending is not used.  Set it to zero
 402              * so that the thr_ipending subsection is not migrated.
 403              */
 404             if (changed & UART_IER_THRI) {
 405                 if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) {
 406                     s->thr_ipending = 1;
 407                 } else {
 408                     s->thr_ipending = 0;
 409                 }
 410             }
 411
 412             if (changed) {
 413                 serial_update_irq(s);
 414             }
 415         }
 416         break;
 417     case 2:
 418         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 419         if ((val ^ s->fcr) & UART_FCR_FE) {
 420             val |= UART_FCR_XFR | UART_FCR_RFR;
 421         }
 422
 423         /* FIFO clear */
 424
 425         if (val & UART_FCR_RFR) {
 426             s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 427             timer_del(s->fifo_timeout_timer);
 428             s->timeout_ipending = 0;
 429             fifo8_reset(&s->recv_fifo);
 430         }
 431
 432         if (val & UART_FCR_XFR) {
 433             s->lsr |= UART_LSR_THRE;
 434             s->thr_ipending = 1;
 435             fifo8_reset(&s->xmit_fifo);
 436         }
 437
 438         serial_write_fcr(s, val & 0xC9);
 439         serial_update_irq(s);
 440         break;
 441     case 3:
 442         {
 443             int break_enable;
 444             s->lcr = val;
 445             serial_update_parameters(s);
 446             break_enable = (val >> 6) & 1;
 447             if (break_enable != s->last_break_enable) {
 448                 s->last_break_enable = break_enable;
 449                 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 450                                   &break_enable);
 451             }
 452         }
 453         break;
 454     case 4:
 455         {
 456             int old_mcr = s->mcr;
 457             s->mcr = val & 0x1f;
 458             if (val & UART_MCR_LOOP)
 459                 break;
 460
 461             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 462                 serial_update_tiocm(s);
 463                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 464                    from the device/computer at the other end of the serial line */
 465                 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time);
 466             }
 467         }
 468         break;
 469     case 5:
 470         break;
 471     case 6:
 472         break;
 473     case 7:
 474         s->scr = val;
 475         break;
 476     }
 477 }
 478
 479 static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
 480 {
 481     SerialState *s = opaque;
 482     uint32_t ret;
 483
 484     addr &= 7;
 485     switch(addr) {
 486     default:
 487     case 0:
 488         if (s->lcr & UART_LCR_DLAB) {
 489             ret = s->divider & 0xff;
 490         } else {
 491             if(s->fcr & UART_FCR_FE) {
 492                 ret = fifo8_is_empty(&s->recv_fifo) ?
 493                             0 : fifo8_pop(&s->recv_fifo);
 494                 if (s->recv_fifo.num == 0) {
 495                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 496                 } else {
 497                     timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
 498                 }
 499                 s->timeout_ipending = 0;
 500             } else {
 501                 ret = s->rbr;
 502                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 503             }
 504             serial_update_irq(s);
 505             if (!(s->mcr & UART_MCR_LOOP)) {
 506                 /* in loopback mode, don't receive any data */
 507                 qemu_chr_fe_accept_input(&s->chr);
 508             }
 509         }
 510         break;
 511     case 1:
 512         if (s->lcr & UART_LCR_DLAB) {
 513             ret = (s->divider >> 8) & 0xff;
 514         } else {
 515             ret = s->ier;
 516         }
 517         break;
 518     case 2:
 519         ret = s->iir;
 520         if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
 521             s->thr_ipending = 0;
 522             serial_update_irq(s);
 523         }
 524         break;
 525     case 3:
 526         ret = s->lcr;
 527         break;
 528     case 4:
 529         ret = s->mcr;
 530         break;
 531     case 5:
 532         ret = s->lsr;
 533         /* Clear break and overrun interrupts */
 534         if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
 535             s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
 536             serial_update_irq(s);
 537         }
 538         break;
 539     case 6:
 540         if (s->mcr & UART_MCR_LOOP) {
 541             /* in loopback, the modem output pins are connected to the
 542                inputs */
 543             ret = (s->mcr & 0x0c) << 4;
 544             ret |= (s->mcr & 0x02) << 3;
 545             ret |= (s->mcr & 0x01) << 5;
 546         } else {
 547             if (s->poll_msl >= 0)
 548                 serial_update_msl(s);
 549             ret = s->msr;
 550             /* Clear delta bits & msr int after read, if they were set */
 551             if (s->msr & UART_MSR_ANY_DELTA) {
 552                 s->msr &= 0xF0;
 553                 serial_update_irq(s);
 554             }
 555         }
 556         break;
 557     case 7:
 558         ret = s->scr;
 559         break;
 560     }
 561     trace_serial_ioport_read(addr, ret);
 562     return ret;
 563 }
 564
 565 static int serial_can_receive(SerialState *s)
 566 {
 567     if(s->fcr & UART_FCR_FE) {
 568         if (s->recv_fifo.num < UART_FIFO_LENGTH) {
 569             /*
 570              * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
 571              * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
 572              * effect will be to almost always fill the fifo completely before
 573              * the guest has a chance to respond, effectively overriding the ITL
 574              * that the guest has set.
 575              */
 576             return (s->recv_fifo.num <= s->recv_fifo_itl) ?
 577                         s->recv_fifo_itl - s->recv_fifo.num : 1;
 578         } else {
 579             return 0;
 580         }
 581     } else {
 582         return !(s->lsr & UART_LSR_DR);
 583     }
 584 }
 585
 586 static void serial_receive_break(SerialState *s)
 587 {
 588     s->rbr = 0;
 589     /* When the LSR_DR is set a null byte is pushed into the fifo */
 590     recv_fifo_put(s, '\0');
 591     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 592     serial_update_irq(s);
 593 }
 594
 595 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 596 static void fifo_timeout_int (void *opaque) {
 597     SerialState *s = opaque;
 598     if (s->recv_fifo.num) {
 599         s->timeout_ipending = 1;
 600         serial_update_irq(s);
 601     }
 602 }
 603
 604 static int serial_can_receive1(void *opaque)
 605 {
 606     SerialState *s = opaque;
 607     return serial_can_receive(s);
 608 }
 609
 610 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 611 {
 612     SerialState *s = opaque;
 613
 614     if (s->wakeup) {
 615         qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER, NULL);
 616     }
 617     if(s->fcr & UART_FCR_FE) {
 618         int i;
 619         for (i = 0; i < size; i++) {
 620             recv_fifo_put(s, buf[i]);
 621         }
 622         s->lsr |= UART_LSR_DR;
 623         /* call the timeout receive callback in 4 char transmit time */
 624         timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
 625     } else {
 626         if (s->lsr & UART_LSR_DR)
 627             s->lsr |= UART_LSR_OE;
 628         s->rbr = buf[0];
 629         s->lsr |= UART_LSR_DR;
 630     }
 631     serial_update_irq(s);
 632 }
 633
 634 static void serial_event(void *opaque, int event)
 635 {
 636     SerialState *s = opaque;
 637     DPRINTF("event %x\n", event);
 638     if (event == CHR_EVENT_BREAK)
 639         serial_receive_break(s);
 640 }
 641
 642 static int serial_pre_save(void *opaque)
 643 {
 644     SerialState *s = opaque;
 645     s->fcr_vmstate = s->fcr;
 646
 647     return 0;
 648 }
 649
 650 static int serial_pre_load(void *opaque)
 651 {
 652     SerialState *s = opaque;
 653     s->thr_ipending = -1;
 654     s->poll_msl = -1;
 655     return 0;
 656 }
 657
 658 static int serial_post_load(void *opaque, int version_id)
 659 {
 660     SerialState *s = opaque;
 661
 662     if (version_id < 3) {
 663         s->fcr_vmstate = 0;
 664     }
 665     if (s->thr_ipending == -1) {
 666         s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
 667     }
 668
 669     if (s->tsr_retry > 0) {
 670         /* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty).  */
 671         if (s->lsr & UART_LSR_TEMT) {
 672             error_report("inconsistent state in serial device "
 673                          "(tsr empty, tsr_retry=%d", s->tsr_retry);
 674             return -1;
 675         }
 676
 677         if (s->tsr_retry > MAX_XMIT_RETRY) {
 678             s->tsr_retry = MAX_XMIT_RETRY;
 679         }
 680
 681         assert(s->watch_tag == 0);
 682         s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 683                                              serial_watch_cb, s);
 684     } else {
 685         /* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty).  */
 686         if (!(s->lsr & UART_LSR_TEMT)) {
 687             error_report("inconsistent state in serial device "
 688                          "(tsr not empty, tsr_retry=0");
 689             return -1;
 690         }
 691     }
 692
 693     s->last_break_enable = (s->lcr >> 6) & 1;
 694     /* Initialize fcr via setter to perform essential side-effects */
 695     serial_write_fcr(s, s->fcr_vmstate);
 696     serial_update_parameters(s);
 697     return 0;
 698 }
 699
 700 static bool serial_thr_ipending_needed(void *opaque)
 701 {
 702     SerialState *s = opaque;
 703
 704     if (s->ier & UART_IER_THRI) {
 705         bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
 706         return s->thr_ipending != expected_value;
 707     } else {
 708         /* LSR.THRE will be sampled again when the interrupt is
 709          * enabled.  thr_ipending is not used in this case, do
 710          * not migrate it.
 711          */
 712         return false;
 713     }
 714 }
 715
 716 static const VMStateDescription vmstate_serial_thr_ipending = {
 717     .name = "serial/thr_ipending",
 718     .version_id = 1,
 719     .minimum_version_id = 1,
 720     .needed = serial_thr_ipending_needed,
 721     .fields = (VMStateField[]) {
 722         VMSTATE_INT32(thr_ipending, SerialState),
 723         VMSTATE_END_OF_LIST()
 724     }
 725 };
 726
 727 static bool serial_tsr_needed(void *opaque)
 728 {
 729     SerialState *s = (SerialState *)opaque;
 730     return s->tsr_retry != 0;
 731 }
 732
 733 static const VMStateDescription vmstate_serial_tsr = {
 734     .name = "serial/tsr",
 735     .version_id = 1,
 736     .minimum_version_id = 1,
 737     .needed = serial_tsr_needed,
 738     .fields = (VMStateField[]) {
 739         VMSTATE_UINT32(tsr_retry, SerialState),
 740         VMSTATE_UINT8(thr, SerialState),
 741         VMSTATE_UINT8(tsr, SerialState),
 742         VMSTATE_END_OF_LIST()
 743     }
 744 };
 745
 746 static bool serial_recv_fifo_needed(void *opaque)
 747 {
 748     SerialState *s = (SerialState *)opaque;
 749     return !fifo8_is_empty(&s->recv_fifo);
 750
 751 }
 752
 753 static const VMStateDescription vmstate_serial_recv_fifo = {
 754     .name = "serial/recv_fifo",
 755     .version_id = 1,
 756     .minimum_version_id = 1,
 757     .needed = serial_recv_fifo_needed,
 758     .fields = (VMStateField[]) {
 759         VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
 760         VMSTATE_END_OF_LIST()
 761     }
 762 };
 763
 764 static bool serial_xmit_fifo_needed(void *opaque)
 765 {
 766     SerialState *s = (SerialState *)opaque;
 767     return !fifo8_is_empty(&s->xmit_fifo);
 768 }
 769
 770 static const VMStateDescription vmstate_serial_xmit_fifo = {
 771     .name = "serial/xmit_fifo",
 772     .version_id = 1,
 773     .minimum_version_id = 1,
 774     .needed = serial_xmit_fifo_needed,
 775     .fields = (VMStateField[]) {
 776         VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
 777         VMSTATE_END_OF_LIST()
 778     }
 779 };
 780
 781 static bool serial_fifo_timeout_timer_needed(void *opaque)
 782 {
 783     SerialState *s = (SerialState *)opaque;
 784     return timer_pending(s->fifo_timeout_timer);
 785 }
 786
 787 static const VMStateDescription vmstate_serial_fifo_timeout_timer = {
 788     .name = "serial/fifo_timeout_timer",
 789     .version_id = 1,
 790     .minimum_version_id = 1,
 791     .needed = serial_fifo_timeout_timer_needed,
 792     .fields = (VMStateField[]) {
 793         VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState),
 794         VMSTATE_END_OF_LIST()
 795     }
 796 };
 797
 798 static bool serial_timeout_ipending_needed(void *opaque)
 799 {
 800     SerialState *s = (SerialState *)opaque;
 801     return s->timeout_ipending != 0;
 802 }
 803
 804 static const VMStateDescription vmstate_serial_timeout_ipending = {
 805     .name = "serial/timeout_ipending",
 806     .version_id = 1,
 807     .minimum_version_id = 1,
 808     .needed = serial_timeout_ipending_needed,
 809     .fields = (VMStateField[]) {
 810         VMSTATE_INT32(timeout_ipending, SerialState),
 811         VMSTATE_END_OF_LIST()
 812     }
 813 };
 814
 815 static bool serial_poll_needed(void *opaque)
 816 {
 817     SerialState *s = (SerialState *)opaque;
 818     return s->poll_msl >= 0;
 819 }
 820
 821 static const VMStateDescription vmstate_serial_poll = {
 822     .name = "serial/poll",
 823     .version_id = 1,
 824     .needed = serial_poll_needed,
 825     .minimum_version_id = 1,
 826     .fields = (VMStateField[]) {
 827         VMSTATE_INT32(poll_msl, SerialState),
 828         VMSTATE_TIMER_PTR(modem_status_poll, SerialState),
 829         VMSTATE_END_OF_LIST()
 830     }
 831 };
 832
 833 const VMStateDescription vmstate_serial = {
 834     .name = "serial",
 835     .version_id = 3,
 836     .minimum_version_id = 2,
 837     .pre_save = serial_pre_save,
 838     .pre_load = serial_pre_load,
 839     .post_load = serial_post_load,
 840     .fields = (VMStateField[]) {
 841         VMSTATE_UINT16_V(divider, SerialState, 2),
 842         VMSTATE_UINT8(rbr, SerialState),
 843         VMSTATE_UINT8(ier, SerialState),
 844         VMSTATE_UINT8(iir, SerialState),
 845         VMSTATE_UINT8(lcr, SerialState),
 846         VMSTATE_UINT8(mcr, SerialState),
 847         VMSTATE_UINT8(lsr, SerialState),
 848         VMSTATE_UINT8(msr, SerialState),
 849         VMSTATE_UINT8(scr, SerialState),
 850         VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 851         VMSTATE_END_OF_LIST()
 852     },
 853     .subsections = (const VMStateDescription*[]) {
 854         &vmstate_serial_thr_ipending,
 855         &vmstate_serial_tsr,
 856         &vmstate_serial_recv_fifo,
 857         &vmstate_serial_xmit_fifo,
 858         &vmstate_serial_fifo_timeout_timer,
 859         &vmstate_serial_timeout_ipending,
 860         &vmstate_serial_poll,
 861         NULL
 862     }
 863 };
 864
 865 static void serial_reset(void *opaque)
 866 {
 867     SerialState *s = opaque;
 868
 869     if (s->watch_tag > 0) {
 870         g_source_remove(s->watch_tag);
 871         s->watch_tag = 0;
 872     }
 873
 874     s->rbr = 0;
 875     s->ier = 0;
 876     s->iir = UART_IIR_NO_INT;
 877     s->lcr = 0;
 878     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 879     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 880     /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
 881     s->divider = 0x0C;
 882     s->mcr = UART_MCR_OUT2;
 883     s->scr = 0;
 884     s->tsr_retry = 0;
 885     s->char_transmit_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
 886     s->poll_msl = 0;
 887
 888     s->timeout_ipending = 0;
 889     timer_del(s->fifo_timeout_timer);
 890     timer_del(s->modem_status_poll);
 891
 892     fifo8_reset(&s->recv_fifo);
 893     fifo8_reset(&s->xmit_fifo);
 894
 895     s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 896
 897     s->thr_ipending = 0;
 898     s->last_break_enable = 0;
 899     qemu_irq_lower(s->irq);
 900
 901     serial_update_msl(s);
 902     s->msr &= ~UART_MSR_ANY_DELTA;
 903 }
 904
 905 static int serial_be_change(void *opaque)
 906 {
 907     SerialState *s = opaque;
 908
 909     qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1,
 910                              serial_event, serial_be_change, s, NULL, true);
 911
 912     serial_update_parameters(s);
 913
 914     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 915                       &s->last_break_enable);
 916
 917     s->poll_msl = (s->ier & UART_IER_MSI) ? 1 : 0;
 918     serial_update_msl(s);
 919
 920     if (s->poll_msl >= 0 && !(s->mcr & UART_MCR_LOOP)) {
 921         serial_update_tiocm(s);
 922     }
 923
 924     if (s->watch_tag > 0) {
 925         g_source_remove(s->watch_tag);
 926         s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 927                                              serial_watch_cb, s);
 928     }
 929
 930     return 0;
 931 }
 932
 933 void serial_realize_core(SerialState *s, Error **errp)
 934 {
 935     s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s);
 936
 937     s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
 938     qemu_register_reset(serial_reset, s);
 939
 940     qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1,
 941                              serial_event, serial_be_change, s, NULL, true);
 942     fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
 943     fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
 944     serial_reset(s);
 945 }
 946
 947 void serial_exit_core(SerialState *s)
 948 {
 949     qemu_chr_fe_deinit(&s->chr, false);
 950
 951     timer_del(s->modem_status_poll);
 952     timer_free(s->modem_status_poll);
 953
 954     timer_del(s->fifo_timeout_timer);
 955     timer_free(s->fifo_timeout_timer);
 956
 957     fifo8_destroy(&s->recv_fifo);
 958     fifo8_destroy(&s->xmit_fifo);
 959
 960     qemu_unregister_reset(serial_reset, s);
 961 }
 962
 963 /* Change the main reference oscillator frequency. */
 964 void serial_set_frequency(SerialState *s, uint32_t frequency)
 965 {
 966     s->baudbase = frequency;
 967     serial_update_parameters(s);
 968 }
 969
 970 const MemoryRegionOps serial_io_ops = {
 971     .read = serial_ioport_read,
 972     .write = serial_ioport_write,
 973     .impl = {
 974         .min_access_size = 1,
 975         .max_access_size = 1,
 976     },
 977     .endianness = DEVICE_LITTLE_ENDIAN,
 978 };
 979
 980 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 981                          Chardev *chr, MemoryRegion *system_io)
 982 {
 983     SerialState *s;
 984
 985     s = g_malloc0(sizeof(SerialState));
 986
 987     s->irq = irq;
 988     s->baudbase = baudbase;
 989     qemu_chr_fe_init(&s->chr, chr, &error_abort);
 990     serial_realize_core(s, &error_fatal);
 991
 992     vmstate_register(NULL, base, &vmstate_serial, s);
 993
 994     memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
 995     memory_region_add_subregion(system_io, base, &s->io);
 996
 997     return s;
 998 }
 999
1000 /* Memory mapped interface */
1001 static uint64_t serial_mm_read(void *opaque, hwaddr addr,
1002                                unsigned size)
1003 {
1004     SerialState *s = opaque;
1005     return serial_ioport_read(s, addr >> s->it_shift, 1);
1006 }
1007
1008 static void serial_mm_write(void *opaque, hwaddr addr,
1009                             uint64_t value, unsigned size)
1010 {
1011     SerialState *s = opaque;
1012     value &= 255;
1013     serial_ioport_write(s, addr >> s->it_shift, value, 1);
1014 }
1015
1016 static const MemoryRegionOps serial_mm_ops[3] = {
1017     [DEVICE_NATIVE_ENDIAN] = {
1018         .read = serial_mm_read,
1019         .write = serial_mm_write,
1020         .endianness = DEVICE_NATIVE_ENDIAN,
1021         .valid.max_access_size = 8,
1022         .impl.max_access_size = 8,
1023     },
1024     [DEVICE_LITTLE_ENDIAN] = {
1025         .read = serial_mm_read,
1026         .write = serial_mm_write,
1027         .endianness = DEVICE_LITTLE_ENDIAN,
1028         .valid.max_access_size = 8,
1029         .impl.max_access_size = 8,
1030     },
1031     [DEVICE_BIG_ENDIAN] = {
1032         .read = serial_mm_read,
1033         .write = serial_mm_write,
1034         .endianness = DEVICE_BIG_ENDIAN,
1035         .valid.max_access_size = 8,
1036         .impl.max_access_size = 8,
1037     },
1038 };
1039
1040 SerialState *serial_mm_init(MemoryRegion *address_space,
1041                             hwaddr base, int it_shift,
1042                             qemu_irq irq, int baudbase,
1043                             Chardev *chr, enum device_endian end)
1044 {
1045     SerialState *s;
1046
1047     s = g_malloc0(sizeof(SerialState));
1048
1049     s->it_shift = it_shift;
1050     s->irq = irq;
1051     s->baudbase = baudbase;
1052     qemu_chr_fe_init(&s->chr, chr, &error_abort);
1053
1054     serial_realize_core(s, &error_fatal);
1055     vmstate_register(NULL, base, &vmstate_serial, s);
1056
1057     memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
1058                           "serial", 8 << it_shift);
1059     memory_region_add_subregion(address_space, base, &s->io);
1060     return s;
1061 }