2 * QEMU Cirrus CLGD 54xx VGA Emulator.
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
34 * - destination write mask support not complete (bits 5..7)
35 * - optimize linear mappings
36 * - optimize bitblt functions
39 //#define DEBUG_CIRRUS
40 //#define DEBUG_BITBLT
42 /***************************************
46 ***************************************/
48 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
51 #define CIRRUS_ID_CLGD5422 (0x23<<2)
52 #define CIRRUS_ID_CLGD5426 (0x24<<2)
53 #define CIRRUS_ID_CLGD5424 (0x25<<2)
54 #define CIRRUS_ID_CLGD5428 (0x26<<2)
55 #define CIRRUS_ID_CLGD5430 (0x28<<2)
56 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
57 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
58 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
61 #define CIRRUS_SR7_BPP_VGA 0x00
62 #define CIRRUS_SR7_BPP_SVGA 0x01
63 #define CIRRUS_SR7_BPP_MASK 0x0e
64 #define CIRRUS_SR7_BPP_8 0x00
65 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
66 #define CIRRUS_SR7_BPP_24 0x04
67 #define CIRRUS_SR7_BPP_16 0x06
68 #define CIRRUS_SR7_BPP_32 0x08
69 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
72 #define CIRRUS_MEMSIZE_512k 0x08
73 #define CIRRUS_MEMSIZE_1M 0x10
74 #define CIRRUS_MEMSIZE_2M 0x18
75 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
78 #define CIRRUS_CURSOR_SHOW 0x01
79 #define CIRRUS_CURSOR_HIDDENPEL 0x02
80 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
83 #define CIRRUS_BUSTYPE_VLBFAST 0x10
84 #define CIRRUS_BUSTYPE_PCI 0x20
85 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
86 #define CIRRUS_BUSTYPE_ISA 0x38
87 #define CIRRUS_MMIO_ENABLE 0x04
88 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
89 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
92 #define CIRRUS_BANKING_DUAL 0x01
93 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
96 #define CIRRUS_BLTMODE_BACKWARDS 0x01
97 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
98 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
99 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
100 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
101 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
102 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
103 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
104 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
105 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
106 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
109 #define CIRRUS_BLT_BUSY 0x01
110 #define CIRRUS_BLT_START 0x02
111 #define CIRRUS_BLT_RESET 0x04
112 #define CIRRUS_BLT_FIFOUSED 0x10
113 #define CIRRUS_BLT_AUTOSTART 0x80
116 #define CIRRUS_ROP_0 0x00
117 #define CIRRUS_ROP_SRC_AND_DST 0x05
118 #define CIRRUS_ROP_NOP 0x06
119 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
120 #define CIRRUS_ROP_NOTDST 0x0b
121 #define CIRRUS_ROP_SRC 0x0d
122 #define CIRRUS_ROP_1 0x0e
123 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
124 #define CIRRUS_ROP_SRC_XOR_DST 0x59
125 #define CIRRUS_ROP_SRC_OR_DST 0x6d
126 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
127 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
128 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
129 #define CIRRUS_ROP_NOTSRC 0xd0
130 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
131 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
133 #define CIRRUS_ROP_NOP_INDEX 2
134 #define CIRRUS_ROP_SRC_INDEX 5
137 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
138 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
139 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
142 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
143 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
144 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
145 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
146 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
147 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
148 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
149 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
150 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
151 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
152 #define CIRRUS_MMIO_BLTROP 0x1a // byte
153 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
154 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
155 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
156 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
157 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
158 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
159 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
160 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
161 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
162 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
164 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
165 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
166 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
167 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
168 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
169 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
170 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
172 // PCI 0x00: vendor, 0x02: device
173 #define PCI_VENDOR_CIRRUS 0x1013
174 #define PCI_DEVICE_CLGD5462 0x00d0
175 #define PCI_DEVICE_CLGD5465 0x00d6
177 // PCI 0x04: command(word), 0x06(word): status
178 #define PCI_COMMAND_IOACCESS 0x0001
179 #define PCI_COMMAND_MEMACCESS 0x0002
180 #define PCI_COMMAND_BUSMASTER 0x0004
181 #define PCI_COMMAND_SPECIALCYCLE 0x0008
182 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
183 #define PCI_COMMAND_PALETTESNOOPING 0x0020
184 #define PCI_COMMAND_PARITYDETECTION 0x0040
185 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
186 #define PCI_COMMAND_SERR 0x0100
187 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
188 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
189 #define PCI_CLASS_BASE_DISPLAY 0x03
190 // PCI 0x08, 0x00ff0000
191 #define PCI_CLASS_SUB_VGA 0x00
192 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
193 #define PCI_CLASS_HEADERTYPE_00h 0x00
194 // 0x10-0x3f (headertype 00h)
195 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
196 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
197 #define PCI_MAP_MEM 0x0
198 #define PCI_MAP_IO 0x1
199 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
200 #define PCI_MAP_IO_ADDR_MASK (~0x3)
201 #define PCI_MAP_MEMFLAGS_32BIT 0x0
202 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
203 #define PCI_MAP_MEMFLAGS_64BIT 0x4
204 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
205 // PCI 0x28: cardbus CIS pointer
206 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
207 // PCI 0x30: expansion ROM base address
208 #define PCI_ROMBIOS_ENABLED 0x1
209 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
210 // PCI 0x38: reserved
211 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
213 #define CIRRUS_PNPMMIO_SIZE 0x1000
216 /* I/O and memory hook */
217 #define CIRRUS_HOOK_NOT_HANDLED 0
218 #define CIRRUS_HOOK_HANDLED 1
220 struct CirrusVGAState
;
221 typedef void (*cirrus_bitblt_rop_t
) (struct CirrusVGAState
*s
,
222 uint8_t * dst
, const uint8_t * src
,
223 int dstpitch
, int srcpitch
,
224 int bltwidth
, int bltheight
);
225 typedef void (*cirrus_fill_t
)(struct CirrusVGAState
*s
,
226 uint8_t *dst
, int dst_pitch
, int width
, int height
);
228 typedef struct CirrusVGAState
{
231 int cirrus_linear_io_addr
;
232 int cirrus_linear_bitblt_io_addr
;
233 int cirrus_mmio_io_addr
;
234 uint32_t cirrus_addr_mask
;
235 uint32_t linear_mmio_mask
;
236 uint8_t cirrus_shadow_gr0
;
237 uint8_t cirrus_shadow_gr1
;
238 uint8_t cirrus_hidden_dac_lockindex
;
239 uint8_t cirrus_hidden_dac_data
;
240 uint32_t cirrus_bank_base
[2];
241 uint32_t cirrus_bank_limit
[2];
242 uint8_t cirrus_hidden_palette
[48];
243 uint32_t hw_cursor_x
;
244 uint32_t hw_cursor_y
;
245 int cirrus_blt_pixelwidth
;
246 int cirrus_blt_width
;
247 int cirrus_blt_height
;
248 int cirrus_blt_dstpitch
;
249 int cirrus_blt_srcpitch
;
250 uint32_t cirrus_blt_fgcol
;
251 uint32_t cirrus_blt_bgcol
;
252 uint32_t cirrus_blt_dstaddr
;
253 uint32_t cirrus_blt_srcaddr
;
254 uint8_t cirrus_blt_mode
;
255 uint8_t cirrus_blt_modeext
;
256 cirrus_bitblt_rop_t cirrus_rop
;
257 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
258 uint8_t cirrus_bltbuf
[CIRRUS_BLTBUFSIZE
];
259 uint8_t *cirrus_srcptr
;
260 uint8_t *cirrus_srcptr_end
;
261 uint32_t cirrus_srccounter
;
262 /* hwcursor display state */
263 int last_hw_cursor_size
;
264 int last_hw_cursor_x
;
265 int last_hw_cursor_y
;
266 int last_hw_cursor_y_start
;
267 int last_hw_cursor_y_end
;
268 int real_vram_size
; /* XXX: suppress that */
269 CPUWriteMemoryFunc
**cirrus_linear_write
;
272 typedef struct PCICirrusVGAState
{
274 CirrusVGAState cirrus_vga
;
277 static uint8_t rop_to_index
[256];
279 /***************************************
283 ***************************************/
286 static void cirrus_bitblt_reset(CirrusVGAState
*s
);
287 static void cirrus_update_memory_access(CirrusVGAState
*s
);
289 /***************************************
293 ***************************************/
295 static void cirrus_bitblt_rop_nop(CirrusVGAState
*s
,
296 uint8_t *dst
,const uint8_t *src
,
297 int dstpitch
,int srcpitch
,
298 int bltwidth
,int bltheight
)
302 static void cirrus_bitblt_fill_nop(CirrusVGAState
*s
,
304 int dstpitch
, int bltwidth
,int bltheight
)
309 #define ROP_OP(d, s) d = 0
310 #include "cirrus_vga_rop.h"
312 #define ROP_NAME src_and_dst
313 #define ROP_OP(d, s) d = (s) & (d)
314 #include "cirrus_vga_rop.h"
316 #define ROP_NAME src_and_notdst
317 #define ROP_OP(d, s) d = (s) & (~(d))
318 #include "cirrus_vga_rop.h"
320 #define ROP_NAME notdst
321 #define ROP_OP(d, s) d = ~(d)
322 #include "cirrus_vga_rop.h"
325 #define ROP_OP(d, s) d = s
326 #include "cirrus_vga_rop.h"
329 #define ROP_OP(d, s) d = ~0
330 #include "cirrus_vga_rop.h"
332 #define ROP_NAME notsrc_and_dst
333 #define ROP_OP(d, s) d = (~(s)) & (d)
334 #include "cirrus_vga_rop.h"
336 #define ROP_NAME src_xor_dst
337 #define ROP_OP(d, s) d = (s) ^ (d)
338 #include "cirrus_vga_rop.h"
340 #define ROP_NAME src_or_dst
341 #define ROP_OP(d, s) d = (s) | (d)
342 #include "cirrus_vga_rop.h"
344 #define ROP_NAME notsrc_or_notdst
345 #define ROP_OP(d, s) d = (~(s)) | (~(d))
346 #include "cirrus_vga_rop.h"
348 #define ROP_NAME src_notxor_dst
349 #define ROP_OP(d, s) d = ~((s) ^ (d))
350 #include "cirrus_vga_rop.h"
352 #define ROP_NAME src_or_notdst
353 #define ROP_OP(d, s) d = (s) | (~(d))
354 #include "cirrus_vga_rop.h"
356 #define ROP_NAME notsrc
357 #define ROP_OP(d, s) d = (~(s))
358 #include "cirrus_vga_rop.h"
360 #define ROP_NAME notsrc_or_dst
361 #define ROP_OP(d, s) d = (~(s)) | (d)
362 #include "cirrus_vga_rop.h"
364 #define ROP_NAME notsrc_and_notdst
365 #define ROP_OP(d, s) d = (~(s)) & (~(d))
366 #include "cirrus_vga_rop.h"
368 static const cirrus_bitblt_rop_t cirrus_fwd_rop
[16] = {
369 cirrus_bitblt_rop_fwd_0
,
370 cirrus_bitblt_rop_fwd_src_and_dst
,
371 cirrus_bitblt_rop_nop
,
372 cirrus_bitblt_rop_fwd_src_and_notdst
,
373 cirrus_bitblt_rop_fwd_notdst
,
374 cirrus_bitblt_rop_fwd_src
,
375 cirrus_bitblt_rop_fwd_1
,
376 cirrus_bitblt_rop_fwd_notsrc_and_dst
,
377 cirrus_bitblt_rop_fwd_src_xor_dst
,
378 cirrus_bitblt_rop_fwd_src_or_dst
,
379 cirrus_bitblt_rop_fwd_notsrc_or_notdst
,
380 cirrus_bitblt_rop_fwd_src_notxor_dst
,
381 cirrus_bitblt_rop_fwd_src_or_notdst
,
382 cirrus_bitblt_rop_fwd_notsrc
,
383 cirrus_bitblt_rop_fwd_notsrc_or_dst
,
384 cirrus_bitblt_rop_fwd_notsrc_and_notdst
,
387 static const cirrus_bitblt_rop_t cirrus_bkwd_rop
[16] = {
388 cirrus_bitblt_rop_bkwd_0
,
389 cirrus_bitblt_rop_bkwd_src_and_dst
,
390 cirrus_bitblt_rop_nop
,
391 cirrus_bitblt_rop_bkwd_src_and_notdst
,
392 cirrus_bitblt_rop_bkwd_notdst
,
393 cirrus_bitblt_rop_bkwd_src
,
394 cirrus_bitblt_rop_bkwd_1
,
395 cirrus_bitblt_rop_bkwd_notsrc_and_dst
,
396 cirrus_bitblt_rop_bkwd_src_xor_dst
,
397 cirrus_bitblt_rop_bkwd_src_or_dst
,
398 cirrus_bitblt_rop_bkwd_notsrc_or_notdst
,
399 cirrus_bitblt_rop_bkwd_src_notxor_dst
,
400 cirrus_bitblt_rop_bkwd_src_or_notdst
,
401 cirrus_bitblt_rop_bkwd_notsrc
,
402 cirrus_bitblt_rop_bkwd_notsrc_or_dst
,
403 cirrus_bitblt_rop_bkwd_notsrc_and_notdst
,
406 #define ROP2(name) {\
413 #define ROP_NOP2(func) {\
420 static const cirrus_bitblt_rop_t cirrus_patternfill
[16][4] = {
421 ROP2(cirrus_patternfill_0
),
422 ROP2(cirrus_patternfill_src_and_dst
),
423 ROP_NOP2(cirrus_bitblt_rop_nop
),
424 ROP2(cirrus_patternfill_src_and_notdst
),
425 ROP2(cirrus_patternfill_notdst
),
426 ROP2(cirrus_patternfill_src
),
427 ROP2(cirrus_patternfill_1
),
428 ROP2(cirrus_patternfill_notsrc_and_dst
),
429 ROP2(cirrus_patternfill_src_xor_dst
),
430 ROP2(cirrus_patternfill_src_or_dst
),
431 ROP2(cirrus_patternfill_notsrc_or_notdst
),
432 ROP2(cirrus_patternfill_src_notxor_dst
),
433 ROP2(cirrus_patternfill_src_or_notdst
),
434 ROP2(cirrus_patternfill_notsrc
),
435 ROP2(cirrus_patternfill_notsrc_or_dst
),
436 ROP2(cirrus_patternfill_notsrc_and_notdst
),
439 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp
[16][4] = {
440 ROP2(cirrus_colorexpand_transp_0
),
441 ROP2(cirrus_colorexpand_transp_src_and_dst
),
442 ROP_NOP2(cirrus_bitblt_rop_nop
),
443 ROP2(cirrus_colorexpand_transp_src_and_notdst
),
444 ROP2(cirrus_colorexpand_transp_notdst
),
445 ROP2(cirrus_colorexpand_transp_src
),
446 ROP2(cirrus_colorexpand_transp_1
),
447 ROP2(cirrus_colorexpand_transp_notsrc_and_dst
),
448 ROP2(cirrus_colorexpand_transp_src_xor_dst
),
449 ROP2(cirrus_colorexpand_transp_src_or_dst
),
450 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst
),
451 ROP2(cirrus_colorexpand_transp_src_notxor_dst
),
452 ROP2(cirrus_colorexpand_transp_src_or_notdst
),
453 ROP2(cirrus_colorexpand_transp_notsrc
),
454 ROP2(cirrus_colorexpand_transp_notsrc_or_dst
),
455 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst
),
458 static const cirrus_bitblt_rop_t cirrus_colorexpand
[16][4] = {
459 ROP2(cirrus_colorexpand_0
),
460 ROP2(cirrus_colorexpand_src_and_dst
),
461 ROP_NOP2(cirrus_bitblt_rop_nop
),
462 ROP2(cirrus_colorexpand_src_and_notdst
),
463 ROP2(cirrus_colorexpand_notdst
),
464 ROP2(cirrus_colorexpand_src
),
465 ROP2(cirrus_colorexpand_1
),
466 ROP2(cirrus_colorexpand_notsrc_and_dst
),
467 ROP2(cirrus_colorexpand_src_xor_dst
),
468 ROP2(cirrus_colorexpand_src_or_dst
),
469 ROP2(cirrus_colorexpand_notsrc_or_notdst
),
470 ROP2(cirrus_colorexpand_src_notxor_dst
),
471 ROP2(cirrus_colorexpand_src_or_notdst
),
472 ROP2(cirrus_colorexpand_notsrc
),
473 ROP2(cirrus_colorexpand_notsrc_or_dst
),
474 ROP2(cirrus_colorexpand_notsrc_and_notdst
),
477 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp
[16][4] = {
478 ROP2(cirrus_colorexpand_pattern_transp_0
),
479 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst
),
480 ROP_NOP2(cirrus_bitblt_rop_nop
),
481 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst
),
482 ROP2(cirrus_colorexpand_pattern_transp_notdst
),
483 ROP2(cirrus_colorexpand_pattern_transp_src
),
484 ROP2(cirrus_colorexpand_pattern_transp_1
),
485 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst
),
486 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst
),
487 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst
),
488 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst
),
489 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst
),
490 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst
),
491 ROP2(cirrus_colorexpand_pattern_transp_notsrc
),
492 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst
),
493 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst
),
496 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern
[16][4] = {
497 ROP2(cirrus_colorexpand_pattern_0
),
498 ROP2(cirrus_colorexpand_pattern_src_and_dst
),
499 ROP_NOP2(cirrus_bitblt_rop_nop
),
500 ROP2(cirrus_colorexpand_pattern_src_and_notdst
),
501 ROP2(cirrus_colorexpand_pattern_notdst
),
502 ROP2(cirrus_colorexpand_pattern_src
),
503 ROP2(cirrus_colorexpand_pattern_1
),
504 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst
),
505 ROP2(cirrus_colorexpand_pattern_src_xor_dst
),
506 ROP2(cirrus_colorexpand_pattern_src_or_dst
),
507 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst
),
508 ROP2(cirrus_colorexpand_pattern_src_notxor_dst
),
509 ROP2(cirrus_colorexpand_pattern_src_or_notdst
),
510 ROP2(cirrus_colorexpand_pattern_notsrc
),
511 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst
),
512 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst
),
515 static const cirrus_fill_t cirrus_fill
[16][4] = {
517 ROP2(cirrus_fill_src_and_dst
),
518 ROP_NOP2(cirrus_bitblt_fill_nop
),
519 ROP2(cirrus_fill_src_and_notdst
),
520 ROP2(cirrus_fill_notdst
),
521 ROP2(cirrus_fill_src
),
523 ROP2(cirrus_fill_notsrc_and_dst
),
524 ROP2(cirrus_fill_src_xor_dst
),
525 ROP2(cirrus_fill_src_or_dst
),
526 ROP2(cirrus_fill_notsrc_or_notdst
),
527 ROP2(cirrus_fill_src_notxor_dst
),
528 ROP2(cirrus_fill_src_or_notdst
),
529 ROP2(cirrus_fill_notsrc
),
530 ROP2(cirrus_fill_notsrc_or_dst
),
531 ROP2(cirrus_fill_notsrc_and_notdst
),
534 static inline void cirrus_bitblt_fgcol(CirrusVGAState
*s
)
537 switch (s
->cirrus_blt_pixelwidth
) {
539 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
;
542 color
= s
->cirrus_shadow_gr1
| (s
->gr
[0x11] << 8);
543 s
->cirrus_blt_fgcol
= le16_to_cpu(color
);
546 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
|
547 (s
->gr
[0x11] << 8) | (s
->gr
[0x13] << 16);
551 color
= s
->cirrus_shadow_gr1
| (s
->gr
[0x11] << 8) |
552 (s
->gr
[0x13] << 16) | (s
->gr
[0x15] << 24);
553 s
->cirrus_blt_fgcol
= le32_to_cpu(color
);
558 static inline void cirrus_bitblt_bgcol(CirrusVGAState
*s
)
561 switch (s
->cirrus_blt_pixelwidth
) {
563 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
;
566 color
= s
->cirrus_shadow_gr0
| (s
->gr
[0x10] << 8);
567 s
->cirrus_blt_bgcol
= le16_to_cpu(color
);
570 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
|
571 (s
->gr
[0x10] << 8) | (s
->gr
[0x12] << 16);
575 color
= s
->cirrus_shadow_gr0
| (s
->gr
[0x10] << 8) |
576 (s
->gr
[0x12] << 16) | (s
->gr
[0x14] << 24);
577 s
->cirrus_blt_bgcol
= le32_to_cpu(color
);
582 static void cirrus_invalidate_region(CirrusVGAState
* s
, int off_begin
,
583 int off_pitch
, int bytesperline
,
590 for (y
= 0; y
< lines
; y
++) {
592 off_cur_end
= off_cur
+ bytesperline
;
593 off_cur
&= TARGET_PAGE_MASK
;
594 while (off_cur
< off_cur_end
) {
595 cpu_physical_memory_set_dirty(s
->vram_offset
+ off_cur
);
596 off_cur
+= TARGET_PAGE_SIZE
;
598 off_begin
+= off_pitch
;
602 static int cirrus_bitblt_common_patterncopy(CirrusVGAState
* s
,
607 dst
= s
->vram_ptr
+ s
->cirrus_blt_dstaddr
;
608 (*s
->cirrus_rop
) (s
, dst
, src
,
609 s
->cirrus_blt_dstpitch
, 0,
610 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
611 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
612 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
613 s
->cirrus_blt_height
);
619 static int cirrus_bitblt_solidfill(CirrusVGAState
*s
, int blt_rop
)
621 cirrus_fill_t rop_func
;
623 rop_func
= cirrus_fill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
624 rop_func(s
, s
->vram_ptr
+ s
->cirrus_blt_dstaddr
,
625 s
->cirrus_blt_dstpitch
,
626 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
627 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
628 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
629 s
->cirrus_blt_height
);
630 cirrus_bitblt_reset(s
);
634 /***************************************
636 * bitblt (video-to-video)
638 ***************************************/
640 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState
* s
)
642 return cirrus_bitblt_common_patterncopy(s
,
644 (s
->cirrus_blt_srcaddr
& ~7));
647 static void cirrus_do_copy(CirrusVGAState
*s
, int dst
, int src
, int w
, int h
)
655 depth
= s
->get_bpp((VGAState
*)s
) / 8;
656 s
->get_resolution((VGAState
*)s
, &width
, &height
);
659 sx
= (src
% (width
* depth
)) / depth
;
660 sy
= (src
/ (width
* depth
));
661 dx
= (dst
% (width
*depth
)) / depth
;
662 dy
= (dst
/ (width
* depth
));
664 /* normalize width */
667 /* if we're doing a backward copy, we have to adjust
668 our x/y to be the upper left corner (instead of the lower
670 if (s
->cirrus_blt_dstpitch
< 0) {
671 sx
-= (s
->cirrus_blt_width
/ depth
) - 1;
672 dx
-= (s
->cirrus_blt_width
/ depth
) - 1;
673 sy
-= s
->cirrus_blt_height
- 1;
674 dy
-= s
->cirrus_blt_height
- 1;
677 /* are we in the visible portion of memory? */
678 if (sx
>= 0 && sy
>= 0 && dx
>= 0 && dy
>= 0 &&
679 (sx
+ w
) <= width
&& (sy
+ h
) <= height
&&
680 (dx
+ w
) <= width
&& (dy
+ h
) <= height
) {
684 /* make to sure only copy if it's a plain copy ROP */
685 if (*s
->cirrus_rop
!= cirrus_bitblt_rop_fwd_src
&&
686 *s
->cirrus_rop
!= cirrus_bitblt_rop_bkwd_src
)
689 /* we have to flush all pending changes so that the copy
690 is generated at the appropriate moment in time */
694 (*s
->cirrus_rop
) (s
, s
->vram_ptr
+ s
->cirrus_blt_dstaddr
,
695 s
->vram_ptr
+ s
->cirrus_blt_srcaddr
,
696 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_srcpitch
,
697 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
700 s
->ds
->dpy_copy(s
->ds
,
702 s
->cirrus_blt_width
/ depth
,
703 s
->cirrus_blt_height
);
705 /* we don't have to notify the display that this portion has
706 changed since dpy_copy implies this */
709 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
710 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
711 s
->cirrus_blt_height
);
714 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState
* s
)
716 if (s
->ds
->dpy_copy
) {
717 cirrus_do_copy(s
, s
->cirrus_blt_dstaddr
- s
->start_addr
,
718 s
->cirrus_blt_srcaddr
- s
->start_addr
,
719 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
721 (*s
->cirrus_rop
) (s
, s
->vram_ptr
+ s
->cirrus_blt_dstaddr
,
722 s
->vram_ptr
+ s
->cirrus_blt_srcaddr
,
723 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_srcpitch
,
724 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
726 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
727 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
728 s
->cirrus_blt_height
);
734 /***************************************
736 * bitblt (cpu-to-video)
738 ***************************************/
740 static void cirrus_bitblt_cputovideo_next(CirrusVGAState
* s
)
745 if (s
->cirrus_srccounter
> 0) {
746 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
747 cirrus_bitblt_common_patterncopy(s
, s
->cirrus_bltbuf
);
749 s
->cirrus_srccounter
= 0;
750 cirrus_bitblt_reset(s
);
752 /* at least one scan line */
754 (*s
->cirrus_rop
)(s
, s
->vram_ptr
+ s
->cirrus_blt_dstaddr
,
755 s
->cirrus_bltbuf
, 0, 0, s
->cirrus_blt_width
, 1);
756 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
, 0,
757 s
->cirrus_blt_width
, 1);
758 s
->cirrus_blt_dstaddr
+= s
->cirrus_blt_dstpitch
;
759 s
->cirrus_srccounter
-= s
->cirrus_blt_srcpitch
;
760 if (s
->cirrus_srccounter
<= 0)
762 /* more bytes than needed can be transfered because of
763 word alignment, so we keep them for the next line */
764 /* XXX: keep alignment to speed up transfer */
765 end_ptr
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
766 copy_count
= s
->cirrus_srcptr_end
- end_ptr
;
767 memmove(s
->cirrus_bltbuf
, end_ptr
, copy_count
);
768 s
->cirrus_srcptr
= s
->cirrus_bltbuf
+ copy_count
;
769 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
770 } while (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
);
775 /***************************************
779 ***************************************/
781 static void cirrus_bitblt_reset(CirrusVGAState
* s
)
784 ~(CIRRUS_BLT_START
| CIRRUS_BLT_BUSY
| CIRRUS_BLT_FIFOUSED
);
785 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
786 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
787 s
->cirrus_srccounter
= 0;
788 cirrus_update_memory_access(s
);
791 static int cirrus_bitblt_cputovideo(CirrusVGAState
* s
)
795 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_MEMSYSSRC
;
796 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
797 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
799 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
800 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
801 s
->cirrus_blt_srcpitch
= 8;
803 /* XXX: check for 24 bpp */
804 s
->cirrus_blt_srcpitch
= 8 * 8 * s
->cirrus_blt_pixelwidth
;
806 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
;
808 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
809 w
= s
->cirrus_blt_width
/ s
->cirrus_blt_pixelwidth
;
810 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_DWORDGRANULARITY
)
811 s
->cirrus_blt_srcpitch
= ((w
+ 31) >> 5);
813 s
->cirrus_blt_srcpitch
= ((w
+ 7) >> 3);
815 /* always align input size to 32 bits */
816 s
->cirrus_blt_srcpitch
= (s
->cirrus_blt_width
+ 3) & ~3;
818 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
* s
->cirrus_blt_height
;
820 s
->cirrus_srcptr
= s
->cirrus_bltbuf
;
821 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
822 cirrus_update_memory_access(s
);
826 static int cirrus_bitblt_videotocpu(CirrusVGAState
* s
)
830 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
835 static int cirrus_bitblt_videotovideo(CirrusVGAState
* s
)
839 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
840 ret
= cirrus_bitblt_videotovideo_patterncopy(s
);
842 ret
= cirrus_bitblt_videotovideo_copy(s
);
845 cirrus_bitblt_reset(s
);
849 static void cirrus_bitblt_start(CirrusVGAState
* s
)
853 s
->gr
[0x31] |= CIRRUS_BLT_BUSY
;
855 s
->cirrus_blt_width
= (s
->gr
[0x20] | (s
->gr
[0x21] << 8)) + 1;
856 s
->cirrus_blt_height
= (s
->gr
[0x22] | (s
->gr
[0x23] << 8)) + 1;
857 s
->cirrus_blt_dstpitch
= (s
->gr
[0x24] | (s
->gr
[0x25] << 8));
858 s
->cirrus_blt_srcpitch
= (s
->gr
[0x26] | (s
->gr
[0x27] << 8));
859 s
->cirrus_blt_dstaddr
=
860 (s
->gr
[0x28] | (s
->gr
[0x29] << 8) | (s
->gr
[0x2a] << 16));
861 s
->cirrus_blt_srcaddr
=
862 (s
->gr
[0x2c] | (s
->gr
[0x2d] << 8) | (s
->gr
[0x2e] << 16));
863 s
->cirrus_blt_mode
= s
->gr
[0x30];
864 s
->cirrus_blt_modeext
= s
->gr
[0x33];
865 blt_rop
= s
->gr
[0x32];
868 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
871 s
->cirrus_blt_modeext
,
873 s
->cirrus_blt_height
,
874 s
->cirrus_blt_dstpitch
,
875 s
->cirrus_blt_srcpitch
,
876 s
->cirrus_blt_dstaddr
,
877 s
->cirrus_blt_srcaddr
,
881 switch (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PIXELWIDTHMASK
) {
882 case CIRRUS_BLTMODE_PIXELWIDTH8
:
883 s
->cirrus_blt_pixelwidth
= 1;
885 case CIRRUS_BLTMODE_PIXELWIDTH16
:
886 s
->cirrus_blt_pixelwidth
= 2;
888 case CIRRUS_BLTMODE_PIXELWIDTH24
:
889 s
->cirrus_blt_pixelwidth
= 3;
891 case CIRRUS_BLTMODE_PIXELWIDTH32
:
892 s
->cirrus_blt_pixelwidth
= 4;
896 printf("cirrus: bitblt - pixel width is unknown\n");
900 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_PIXELWIDTHMASK
;
903 cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSSRC
|
904 CIRRUS_BLTMODE_MEMSYSDEST
))
905 == (CIRRUS_BLTMODE_MEMSYSSRC
| CIRRUS_BLTMODE_MEMSYSDEST
)) {
907 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
912 if ((s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_SOLIDFILL
) &&
913 (s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSDEST
|
914 CIRRUS_BLTMODE_TRANSPARENTCOMP
|
915 CIRRUS_BLTMODE_PATTERNCOPY
|
916 CIRRUS_BLTMODE_COLOREXPAND
)) ==
917 (CIRRUS_BLTMODE_PATTERNCOPY
| CIRRUS_BLTMODE_COLOREXPAND
)) {
918 cirrus_bitblt_fgcol(s
);
919 cirrus_bitblt_solidfill(s
, blt_rop
);
921 if ((s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_COLOREXPAND
|
922 CIRRUS_BLTMODE_PATTERNCOPY
)) ==
923 CIRRUS_BLTMODE_COLOREXPAND
) {
925 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
926 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
927 cirrus_bitblt_bgcol(s
);
929 cirrus_bitblt_fgcol(s
);
930 s
->cirrus_rop
= cirrus_colorexpand_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
932 cirrus_bitblt_fgcol(s
);
933 cirrus_bitblt_bgcol(s
);
934 s
->cirrus_rop
= cirrus_colorexpand
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
936 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
937 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
938 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
939 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
940 cirrus_bitblt_bgcol(s
);
942 cirrus_bitblt_fgcol(s
);
943 s
->cirrus_rop
= cirrus_colorexpand_pattern_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
945 cirrus_bitblt_fgcol(s
);
946 cirrus_bitblt_bgcol(s
);
947 s
->cirrus_rop
= cirrus_colorexpand_pattern
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
950 s
->cirrus_rop
= cirrus_patternfill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
953 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_BACKWARDS
) {
954 s
->cirrus_blt_dstpitch
= -s
->cirrus_blt_dstpitch
;
955 s
->cirrus_blt_srcpitch
= -s
->cirrus_blt_srcpitch
;
956 s
->cirrus_rop
= cirrus_bkwd_rop
[rop_to_index
[blt_rop
]];
958 s
->cirrus_rop
= cirrus_fwd_rop
[rop_to_index
[blt_rop
]];
962 // setup bitblt engine.
963 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSSRC
) {
964 if (!cirrus_bitblt_cputovideo(s
))
966 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSDEST
) {
967 if (!cirrus_bitblt_videotocpu(s
))
970 if (!cirrus_bitblt_videotovideo(s
))
976 cirrus_bitblt_reset(s
);
979 static void cirrus_write_bitblt(CirrusVGAState
* s
, unsigned reg_value
)
983 old_value
= s
->gr
[0x31];
984 s
->gr
[0x31] = reg_value
;
986 if (((old_value
& CIRRUS_BLT_RESET
) != 0) &&
987 ((reg_value
& CIRRUS_BLT_RESET
) == 0)) {
988 cirrus_bitblt_reset(s
);
989 } else if (((old_value
& CIRRUS_BLT_START
) == 0) &&
990 ((reg_value
& CIRRUS_BLT_START
) != 0)) {
991 cirrus_bitblt_start(s
);
996 /***************************************
1000 ***************************************/
1002 static void cirrus_get_offsets(VGAState
*s1
,
1003 uint32_t *pline_offset
,
1004 uint32_t *pstart_addr
)
1006 CirrusVGAState
* s
= (CirrusVGAState
*)s1
;
1007 uint32_t start_addr
;
1008 uint32_t line_offset
;
1010 line_offset
= s
->cr
[0x13]
1011 | ((s
->cr
[0x1b] & 0x10) << 4);
1013 *pline_offset
= line_offset
;
1015 start_addr
= (s
->cr
[0x0c] << 8)
1017 | ((s
->cr
[0x1b] & 0x01) << 16)
1018 | ((s
->cr
[0x1b] & 0x0c) << 15)
1019 | ((s
->cr
[0x1d] & 0x80) << 12);
1020 *pstart_addr
= start_addr
;
1023 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState
* s
)
1027 switch (s
->cirrus_hidden_dac_data
& 0xf) {
1030 break; /* Sierra HiColor */
1033 break; /* XGA HiColor */
1036 printf("cirrus: invalid DAC value %x in 16bpp\n",
1037 (s
->cirrus_hidden_dac_data
& 0xf));
1045 static int cirrus_get_bpp(VGAState
*s1
)
1047 CirrusVGAState
* s
= (CirrusVGAState
*)s1
;
1050 if ((s
->sr
[0x07] & 0x01) != 0) {
1052 switch (s
->sr
[0x07] & CIRRUS_SR7_BPP_MASK
) {
1053 case CIRRUS_SR7_BPP_8
:
1056 case CIRRUS_SR7_BPP_16_DOUBLEVCLK
:
1057 ret
= cirrus_get_bpp16_depth(s
);
1059 case CIRRUS_SR7_BPP_24
:
1062 case CIRRUS_SR7_BPP_16
:
1063 ret
= cirrus_get_bpp16_depth(s
);
1065 case CIRRUS_SR7_BPP_32
:
1070 printf("cirrus: unknown bpp - sr7=%x\n", s
->sr
[0x7]);
1083 static void cirrus_get_resolution(VGAState
*s
, int *pwidth
, int *pheight
)
1087 width
= (s
->cr
[0x01] + 1) * 8;
1088 height
= s
->cr
[0x12] |
1089 ((s
->cr
[0x07] & 0x02) << 7) |
1090 ((s
->cr
[0x07] & 0x40) << 3);
1091 height
= (height
+ 1);
1092 /* interlace support */
1093 if (s
->cr
[0x1a] & 0x01)
1094 height
= height
* 2;
1099 /***************************************
1103 ***************************************/
1105 static void cirrus_update_bank_ptr(CirrusVGAState
* s
, unsigned bank_index
)
1110 if ((s
->gr
[0x0b] & 0x01) != 0) /* dual bank */
1111 offset
= s
->gr
[0x09 + bank_index
];
1112 else /* single bank */
1113 offset
= s
->gr
[0x09];
1115 if ((s
->gr
[0x0b] & 0x20) != 0)
1120 if (s
->real_vram_size
<= offset
)
1123 limit
= s
->real_vram_size
- offset
;
1125 if (((s
->gr
[0x0b] & 0x01) == 0) && (bank_index
!= 0)) {
1126 if (limit
> 0x8000) {
1135 s
->cirrus_bank_base
[bank_index
] = offset
;
1136 s
->cirrus_bank_limit
[bank_index
] = limit
;
1138 s
->cirrus_bank_base
[bank_index
] = 0;
1139 s
->cirrus_bank_limit
[bank_index
] = 0;
1143 /***************************************
1145 * I/O access between 0x3c4-0x3c5
1147 ***************************************/
1150 cirrus_hook_read_sr(CirrusVGAState
* s
, unsigned reg_index
, int *reg_value
)
1152 switch (reg_index
) {
1153 case 0x00: // Standard VGA
1154 case 0x01: // Standard VGA
1155 case 0x02: // Standard VGA
1156 case 0x03: // Standard VGA
1157 case 0x04: // Standard VGA
1158 return CIRRUS_HOOK_NOT_HANDLED
;
1159 case 0x06: // Unlock Cirrus extensions
1160 *reg_value
= s
->sr
[reg_index
];
1165 case 0x70: // Graphics Cursor X
1169 case 0xf0: // Graphics Cursor X
1170 *reg_value
= s
->sr
[0x10];
1175 case 0x71: // Graphics Cursor Y
1179 case 0xf1: // Graphics Cursor Y
1180 *reg_value
= s
->sr
[0x11];
1183 case 0x07: // Extended Sequencer Mode
1184 case 0x08: // EEPROM Control
1185 case 0x09: // Scratch Register 0
1186 case 0x0a: // Scratch Register 1
1187 case 0x0b: // VCLK 0
1188 case 0x0c: // VCLK 1
1189 case 0x0d: // VCLK 2
1190 case 0x0e: // VCLK 3
1191 case 0x0f: // DRAM Control
1192 case 0x12: // Graphics Cursor Attribute
1193 case 0x13: // Graphics Cursor Pattern Address
1194 case 0x14: // Scratch Register 2
1195 case 0x15: // Scratch Register 3
1196 case 0x16: // Performance Tuning Register
1197 case 0x17: // Configuration Readback and Extended Control
1198 case 0x18: // Signature Generator Control
1199 case 0x19: // Signal Generator Result
1200 case 0x1a: // Signal Generator Result
1201 case 0x1b: // VCLK 0 Denominator & Post
1202 case 0x1c: // VCLK 1 Denominator & Post
1203 case 0x1d: // VCLK 2 Denominator & Post
1204 case 0x1e: // VCLK 3 Denominator & Post
1205 case 0x1f: // BIOS Write Enable and MCLK select
1207 printf("cirrus: handled inport sr_index %02x\n", reg_index
);
1209 *reg_value
= s
->sr
[reg_index
];
1213 printf("cirrus: inport sr_index %02x\n", reg_index
);
1219 return CIRRUS_HOOK_HANDLED
;
1223 cirrus_hook_write_sr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1225 switch (reg_index
) {
1226 case 0x00: // Standard VGA
1227 case 0x01: // Standard VGA
1228 case 0x02: // Standard VGA
1229 case 0x03: // Standard VGA
1230 case 0x04: // Standard VGA
1231 return CIRRUS_HOOK_NOT_HANDLED
;
1232 case 0x06: // Unlock Cirrus extensions
1234 if (reg_value
== 0x12) {
1235 s
->sr
[reg_index
] = 0x12;
1237 s
->sr
[reg_index
] = 0x0f;
1243 case 0x70: // Graphics Cursor X
1247 case 0xf0: // Graphics Cursor X
1248 s
->sr
[0x10] = reg_value
;
1249 s
->hw_cursor_x
= (reg_value
<< 3) | (reg_index
>> 5);
1254 case 0x71: // Graphics Cursor Y
1258 case 0xf1: // Graphics Cursor Y
1259 s
->sr
[0x11] = reg_value
;
1260 s
->hw_cursor_y
= (reg_value
<< 3) | (reg_index
>> 5);
1262 case 0x07: // Extended Sequencer Mode
1263 case 0x08: // EEPROM Control
1264 case 0x09: // Scratch Register 0
1265 case 0x0a: // Scratch Register 1
1266 case 0x0b: // VCLK 0
1267 case 0x0c: // VCLK 1
1268 case 0x0d: // VCLK 2
1269 case 0x0e: // VCLK 3
1270 case 0x0f: // DRAM Control
1271 case 0x12: // Graphics Cursor Attribute
1272 case 0x13: // Graphics Cursor Pattern Address
1273 case 0x14: // Scratch Register 2
1274 case 0x15: // Scratch Register 3
1275 case 0x16: // Performance Tuning Register
1276 case 0x18: // Signature Generator Control
1277 case 0x19: // Signature Generator Result
1278 case 0x1a: // Signature Generator Result
1279 case 0x1b: // VCLK 0 Denominator & Post
1280 case 0x1c: // VCLK 1 Denominator & Post
1281 case 0x1d: // VCLK 2 Denominator & Post
1282 case 0x1e: // VCLK 3 Denominator & Post
1283 case 0x1f: // BIOS Write Enable and MCLK select
1284 s
->sr
[reg_index
] = reg_value
;
1286 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1287 reg_index
, reg_value
);
1290 case 0x17: // Configuration Readback and Extended Control
1291 s
->sr
[reg_index
] = (s
->sr
[reg_index
] & 0x38) | (reg_value
& 0xc7);
1292 cirrus_update_memory_access(s
);
1296 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index
,
1302 return CIRRUS_HOOK_HANDLED
;
1305 /***************************************
1307 * I/O access at 0x3c6
1309 ***************************************/
1311 static void cirrus_read_hidden_dac(CirrusVGAState
* s
, int *reg_value
)
1314 if (++s
->cirrus_hidden_dac_lockindex
== 5) {
1315 *reg_value
= s
->cirrus_hidden_dac_data
;
1316 s
->cirrus_hidden_dac_lockindex
= 0;
1320 static void cirrus_write_hidden_dac(CirrusVGAState
* s
, int reg_value
)
1322 if (s
->cirrus_hidden_dac_lockindex
== 4) {
1323 s
->cirrus_hidden_dac_data
= reg_value
;
1324 #if defined(DEBUG_CIRRUS)
1325 printf("cirrus: outport hidden DAC, value %02x\n", reg_value
);
1328 s
->cirrus_hidden_dac_lockindex
= 0;
1331 /***************************************
1333 * I/O access at 0x3c9
1335 ***************************************/
1337 static int cirrus_hook_read_palette(CirrusVGAState
* s
, int *reg_value
)
1339 if (!(s
->sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
))
1340 return CIRRUS_HOOK_NOT_HANDLED
;
1342 s
->cirrus_hidden_palette
[(s
->dac_read_index
& 0x0f) * 3 +
1344 if (++s
->dac_sub_index
== 3) {
1345 s
->dac_sub_index
= 0;
1346 s
->dac_read_index
++;
1348 return CIRRUS_HOOK_HANDLED
;
1351 static int cirrus_hook_write_palette(CirrusVGAState
* s
, int reg_value
)
1353 if (!(s
->sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
))
1354 return CIRRUS_HOOK_NOT_HANDLED
;
1355 s
->dac_cache
[s
->dac_sub_index
] = reg_value
;
1356 if (++s
->dac_sub_index
== 3) {
1357 memcpy(&s
->cirrus_hidden_palette
[(s
->dac_write_index
& 0x0f) * 3],
1359 /* XXX update cursor */
1360 s
->dac_sub_index
= 0;
1361 s
->dac_write_index
++;
1363 return CIRRUS_HOOK_HANDLED
;
1366 /***************************************
1368 * I/O access between 0x3ce-0x3cf
1370 ***************************************/
1373 cirrus_hook_read_gr(CirrusVGAState
* s
, unsigned reg_index
, int *reg_value
)
1375 switch (reg_index
) {
1376 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1377 *reg_value
= s
->cirrus_shadow_gr0
;
1378 return CIRRUS_HOOK_HANDLED
;
1379 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1380 *reg_value
= s
->cirrus_shadow_gr1
;
1381 return CIRRUS_HOOK_HANDLED
;
1382 case 0x02: // Standard VGA
1383 case 0x03: // Standard VGA
1384 case 0x04: // Standard VGA
1385 case 0x06: // Standard VGA
1386 case 0x07: // Standard VGA
1387 case 0x08: // Standard VGA
1388 return CIRRUS_HOOK_NOT_HANDLED
;
1389 case 0x05: // Standard VGA, Cirrus extended mode
1394 if (reg_index
< 0x3a) {
1395 *reg_value
= s
->gr
[reg_index
];
1398 printf("cirrus: inport gr_index %02x\n", reg_index
);
1403 return CIRRUS_HOOK_HANDLED
;
1407 cirrus_hook_write_gr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1409 #if defined(DEBUG_BITBLT) && 0
1410 printf("gr%02x: %02x\n", reg_index
, reg_value
);
1412 switch (reg_index
) {
1413 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1414 s
->cirrus_shadow_gr0
= reg_value
;
1415 return CIRRUS_HOOK_NOT_HANDLED
;
1416 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1417 s
->cirrus_shadow_gr1
= reg_value
;
1418 return CIRRUS_HOOK_NOT_HANDLED
;
1419 case 0x02: // Standard VGA
1420 case 0x03: // Standard VGA
1421 case 0x04: // Standard VGA
1422 case 0x06: // Standard VGA
1423 case 0x07: // Standard VGA
1424 case 0x08: // Standard VGA
1425 return CIRRUS_HOOK_NOT_HANDLED
;
1426 case 0x05: // Standard VGA, Cirrus extended mode
1427 s
->gr
[reg_index
] = reg_value
& 0x7f;
1428 cirrus_update_memory_access(s
);
1430 case 0x09: // bank offset #0
1431 case 0x0A: // bank offset #1
1432 s
->gr
[reg_index
] = reg_value
;
1433 cirrus_update_bank_ptr(s
, 0);
1434 cirrus_update_bank_ptr(s
, 1);
1437 s
->gr
[reg_index
] = reg_value
;
1438 cirrus_update_bank_ptr(s
, 0);
1439 cirrus_update_bank_ptr(s
, 1);
1440 cirrus_update_memory_access(s
);
1442 case 0x10: // BGCOLOR 0x0000ff00
1443 case 0x11: // FGCOLOR 0x0000ff00
1444 case 0x12: // BGCOLOR 0x00ff0000
1445 case 0x13: // FGCOLOR 0x00ff0000
1446 case 0x14: // BGCOLOR 0xff000000
1447 case 0x15: // FGCOLOR 0xff000000
1448 case 0x20: // BLT WIDTH 0x0000ff
1449 case 0x22: // BLT HEIGHT 0x0000ff
1450 case 0x24: // BLT DEST PITCH 0x0000ff
1451 case 0x26: // BLT SRC PITCH 0x0000ff
1452 case 0x28: // BLT DEST ADDR 0x0000ff
1453 case 0x29: // BLT DEST ADDR 0x00ff00
1454 case 0x2c: // BLT SRC ADDR 0x0000ff
1455 case 0x2d: // BLT SRC ADDR 0x00ff00
1456 case 0x2f: // BLT WRITEMASK
1457 case 0x30: // BLT MODE
1458 case 0x32: // RASTER OP
1459 case 0x33: // BLT MODEEXT
1460 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1461 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1462 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1463 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1464 s
->gr
[reg_index
] = reg_value
;
1466 case 0x21: // BLT WIDTH 0x001f00
1467 case 0x23: // BLT HEIGHT 0x001f00
1468 case 0x25: // BLT DEST PITCH 0x001f00
1469 case 0x27: // BLT SRC PITCH 0x001f00
1470 s
->gr
[reg_index
] = reg_value
& 0x1f;
1472 case 0x2a: // BLT DEST ADDR 0x3f0000
1473 s
->gr
[reg_index
] = reg_value
& 0x3f;
1474 /* if auto start mode, starts bit blt now */
1475 if (s
->gr
[0x31] & CIRRUS_BLT_AUTOSTART
) {
1476 cirrus_bitblt_start(s
);
1479 case 0x2e: // BLT SRC ADDR 0x3f0000
1480 s
->gr
[reg_index
] = reg_value
& 0x3f;
1482 case 0x31: // BLT STATUS/START
1483 cirrus_write_bitblt(s
, reg_value
);
1487 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index
,
1493 return CIRRUS_HOOK_HANDLED
;
1496 /***************************************
1498 * I/O access between 0x3d4-0x3d5
1500 ***************************************/
1503 cirrus_hook_read_cr(CirrusVGAState
* s
, unsigned reg_index
, int *reg_value
)
1505 switch (reg_index
) {
1506 case 0x00: // Standard VGA
1507 case 0x01: // Standard VGA
1508 case 0x02: // Standard VGA
1509 case 0x03: // Standard VGA
1510 case 0x04: // Standard VGA
1511 case 0x05: // Standard VGA
1512 case 0x06: // Standard VGA
1513 case 0x07: // Standard VGA
1514 case 0x08: // Standard VGA
1515 case 0x09: // Standard VGA
1516 case 0x0a: // Standard VGA
1517 case 0x0b: // Standard VGA
1518 case 0x0c: // Standard VGA
1519 case 0x0d: // Standard VGA
1520 case 0x0e: // Standard VGA
1521 case 0x0f: // Standard VGA
1522 case 0x10: // Standard VGA
1523 case 0x11: // Standard VGA
1524 case 0x12: // Standard VGA
1525 case 0x13: // Standard VGA
1526 case 0x14: // Standard VGA
1527 case 0x15: // Standard VGA
1528 case 0x16: // Standard VGA
1529 case 0x17: // Standard VGA
1530 case 0x18: // Standard VGA
1531 return CIRRUS_HOOK_NOT_HANDLED
;
1532 case 0x19: // Interlace End
1533 case 0x1a: // Miscellaneous Control
1534 case 0x1b: // Extended Display Control
1535 case 0x1c: // Sync Adjust and Genlock
1536 case 0x1d: // Overlay Extended Control
1537 case 0x22: // Graphics Data Latches Readback (R)
1538 case 0x24: // Attribute Controller Toggle Readback (R)
1539 case 0x25: // Part Status
1540 case 0x27: // Part ID (R)
1541 *reg_value
= s
->cr
[reg_index
];
1543 case 0x26: // Attribute Controller Index Readback (R)
1544 *reg_value
= s
->ar_index
& 0x3f;
1548 printf("cirrus: inport cr_index %02x\n", reg_index
);
1554 return CIRRUS_HOOK_HANDLED
;
1558 cirrus_hook_write_cr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1560 switch (reg_index
) {
1561 case 0x00: // Standard VGA
1562 case 0x01: // Standard VGA
1563 case 0x02: // Standard VGA
1564 case 0x03: // Standard VGA
1565 case 0x04: // Standard VGA
1566 case 0x05: // Standard VGA
1567 case 0x06: // Standard VGA
1568 case 0x07: // Standard VGA
1569 case 0x08: // Standard VGA
1570 case 0x09: // Standard VGA
1571 case 0x0a: // Standard VGA
1572 case 0x0b: // Standard VGA
1573 case 0x0c: // Standard VGA
1574 case 0x0d: // Standard VGA
1575 case 0x0e: // Standard VGA
1576 case 0x0f: // Standard VGA
1577 case 0x10: // Standard VGA
1578 case 0x11: // Standard VGA
1579 case 0x12: // Standard VGA
1580 case 0x13: // Standard VGA
1581 case 0x14: // Standard VGA
1582 case 0x15: // Standard VGA
1583 case 0x16: // Standard VGA
1584 case 0x17: // Standard VGA
1585 case 0x18: // Standard VGA
1586 return CIRRUS_HOOK_NOT_HANDLED
;
1587 case 0x19: // Interlace End
1588 case 0x1a: // Miscellaneous Control
1589 case 0x1b: // Extended Display Control
1590 case 0x1c: // Sync Adjust and Genlock
1591 case 0x1d: // Overlay Extended Control
1592 s
->cr
[reg_index
] = reg_value
;
1594 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1595 reg_index
, reg_value
);
1598 case 0x22: // Graphics Data Latches Readback (R)
1599 case 0x24: // Attribute Controller Toggle Readback (R)
1600 case 0x26: // Attribute Controller Index Readback (R)
1601 case 0x27: // Part ID (R)
1603 case 0x25: // Part Status
1606 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index
,
1612 return CIRRUS_HOOK_HANDLED
;
1615 /***************************************
1617 * memory-mapped I/O (bitblt)
1619 ***************************************/
1621 static uint8_t cirrus_mmio_blt_read(CirrusVGAState
* s
, unsigned address
)
1626 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1627 cirrus_hook_read_gr(s
, 0x00, &value
);
1629 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1630 cirrus_hook_read_gr(s
, 0x10, &value
);
1632 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1633 cirrus_hook_read_gr(s
, 0x12, &value
);
1635 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1636 cirrus_hook_read_gr(s
, 0x14, &value
);
1638 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1639 cirrus_hook_read_gr(s
, 0x01, &value
);
1641 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1642 cirrus_hook_read_gr(s
, 0x11, &value
);
1644 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1645 cirrus_hook_read_gr(s
, 0x13, &value
);
1647 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1648 cirrus_hook_read_gr(s
, 0x15, &value
);
1650 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1651 cirrus_hook_read_gr(s
, 0x20, &value
);
1653 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1654 cirrus_hook_read_gr(s
, 0x21, &value
);
1656 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1657 cirrus_hook_read_gr(s
, 0x22, &value
);
1659 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1660 cirrus_hook_read_gr(s
, 0x23, &value
);
1662 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1663 cirrus_hook_read_gr(s
, 0x24, &value
);
1665 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1666 cirrus_hook_read_gr(s
, 0x25, &value
);
1668 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1669 cirrus_hook_read_gr(s
, 0x26, &value
);
1671 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1672 cirrus_hook_read_gr(s
, 0x27, &value
);
1674 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1675 cirrus_hook_read_gr(s
, 0x28, &value
);
1677 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1678 cirrus_hook_read_gr(s
, 0x29, &value
);
1680 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1681 cirrus_hook_read_gr(s
, 0x2a, &value
);
1683 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1684 cirrus_hook_read_gr(s
, 0x2c, &value
);
1686 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1687 cirrus_hook_read_gr(s
, 0x2d, &value
);
1689 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1690 cirrus_hook_read_gr(s
, 0x2e, &value
);
1692 case CIRRUS_MMIO_BLTWRITEMASK
:
1693 cirrus_hook_read_gr(s
, 0x2f, &value
);
1695 case CIRRUS_MMIO_BLTMODE
:
1696 cirrus_hook_read_gr(s
, 0x30, &value
);
1698 case CIRRUS_MMIO_BLTROP
:
1699 cirrus_hook_read_gr(s
, 0x32, &value
);
1701 case CIRRUS_MMIO_BLTMODEEXT
:
1702 cirrus_hook_read_gr(s
, 0x33, &value
);
1704 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1705 cirrus_hook_read_gr(s
, 0x34, &value
);
1707 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1708 cirrus_hook_read_gr(s
, 0x35, &value
);
1710 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1711 cirrus_hook_read_gr(s
, 0x38, &value
);
1713 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1714 cirrus_hook_read_gr(s
, 0x39, &value
);
1716 case CIRRUS_MMIO_BLTSTATUS
:
1717 cirrus_hook_read_gr(s
, 0x31, &value
);
1721 printf("cirrus: mmio read - address 0x%04x\n", address
);
1726 return (uint8_t) value
;
1729 static void cirrus_mmio_blt_write(CirrusVGAState
* s
, unsigned address
,
1733 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1734 cirrus_hook_write_gr(s
, 0x00, value
);
1736 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1737 cirrus_hook_write_gr(s
, 0x10, value
);
1739 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1740 cirrus_hook_write_gr(s
, 0x12, value
);
1742 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1743 cirrus_hook_write_gr(s
, 0x14, value
);
1745 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1746 cirrus_hook_write_gr(s
, 0x01, value
);
1748 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1749 cirrus_hook_write_gr(s
, 0x11, value
);
1751 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1752 cirrus_hook_write_gr(s
, 0x13, value
);
1754 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1755 cirrus_hook_write_gr(s
, 0x15, value
);
1757 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1758 cirrus_hook_write_gr(s
, 0x20, value
);
1760 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1761 cirrus_hook_write_gr(s
, 0x21, value
);
1763 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1764 cirrus_hook_write_gr(s
, 0x22, value
);
1766 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1767 cirrus_hook_write_gr(s
, 0x23, value
);
1769 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1770 cirrus_hook_write_gr(s
, 0x24, value
);
1772 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1773 cirrus_hook_write_gr(s
, 0x25, value
);
1775 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1776 cirrus_hook_write_gr(s
, 0x26, value
);
1778 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1779 cirrus_hook_write_gr(s
, 0x27, value
);
1781 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1782 cirrus_hook_write_gr(s
, 0x28, value
);
1784 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1785 cirrus_hook_write_gr(s
, 0x29, value
);
1787 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1788 cirrus_hook_write_gr(s
, 0x2a, value
);
1790 case (CIRRUS_MMIO_BLTDESTADDR
+ 3):
1793 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1794 cirrus_hook_write_gr(s
, 0x2c, value
);
1796 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1797 cirrus_hook_write_gr(s
, 0x2d, value
);
1799 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1800 cirrus_hook_write_gr(s
, 0x2e, value
);
1802 case CIRRUS_MMIO_BLTWRITEMASK
:
1803 cirrus_hook_write_gr(s
, 0x2f, value
);
1805 case CIRRUS_MMIO_BLTMODE
:
1806 cirrus_hook_write_gr(s
, 0x30, value
);
1808 case CIRRUS_MMIO_BLTROP
:
1809 cirrus_hook_write_gr(s
, 0x32, value
);
1811 case CIRRUS_MMIO_BLTMODEEXT
:
1812 cirrus_hook_write_gr(s
, 0x33, value
);
1814 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1815 cirrus_hook_write_gr(s
, 0x34, value
);
1817 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1818 cirrus_hook_write_gr(s
, 0x35, value
);
1820 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1821 cirrus_hook_write_gr(s
, 0x38, value
);
1823 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1824 cirrus_hook_write_gr(s
, 0x39, value
);
1826 case CIRRUS_MMIO_BLTSTATUS
:
1827 cirrus_hook_write_gr(s
, 0x31, value
);
1831 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1838 /***************************************
1842 * assume TARGET_PAGE_SIZE >= 16
1844 ***************************************/
1846 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState
* s
,
1852 unsigned val
= mem_value
;
1855 dst
= s
->vram_ptr
+ offset
;
1856 for (x
= 0; x
< 8; x
++) {
1858 *dst
= s
->cirrus_shadow_gr1
;
1859 } else if (mode
== 5) {
1860 *dst
= s
->cirrus_shadow_gr0
;
1865 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
);
1866 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
+ 7);
1869 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState
* s
,
1875 unsigned val
= mem_value
;
1878 dst
= s
->vram_ptr
+ offset
;
1879 for (x
= 0; x
< 8; x
++) {
1881 *dst
= s
->cirrus_shadow_gr1
;
1882 *(dst
+ 1) = s
->gr
[0x11];
1883 } else if (mode
== 5) {
1884 *dst
= s
->cirrus_shadow_gr0
;
1885 *(dst
+ 1) = s
->gr
[0x10];
1890 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
);
1891 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
+ 15);
1894 /***************************************
1896 * memory access between 0xa0000-0xbffff
1898 ***************************************/
1900 static uint32_t cirrus_vga_mem_readb(void *opaque
, target_phys_addr_t addr
)
1902 CirrusVGAState
*s
= opaque
;
1903 unsigned bank_index
;
1904 unsigned bank_offset
;
1907 if ((s
->sr
[0x07] & 0x01) == 0) {
1908 return vga_mem_readb(s
, addr
);
1913 if (addr
< 0x10000) {
1914 /* XXX handle bitblt */
1916 bank_index
= addr
>> 15;
1917 bank_offset
= addr
& 0x7fff;
1918 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
1919 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
1920 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
1922 } else if (s
->gr
[0x0B] & 0x02) {
1925 bank_offset
&= s
->cirrus_addr_mask
;
1926 val
= *(s
->vram_ptr
+ bank_offset
);
1929 } else if (addr
>= 0x18000 && addr
< 0x18100) {
1930 /* memory-mapped I/O */
1932 if ((s
->sr
[0x17] & 0x44) == 0x04) {
1933 val
= cirrus_mmio_blt_read(s
, addr
& 0xff);
1938 printf("cirrus: mem_readb %06x\n", addr
);
1944 static uint32_t cirrus_vga_mem_readw(void *opaque
, target_phys_addr_t addr
)
1947 #ifdef TARGET_WORDS_BIGENDIAN
1948 v
= cirrus_vga_mem_readb(opaque
, addr
) << 8;
1949 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1);
1951 v
= cirrus_vga_mem_readb(opaque
, addr
);
1952 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1) << 8;
1957 static uint32_t cirrus_vga_mem_readl(void *opaque
, target_phys_addr_t addr
)
1960 #ifdef TARGET_WORDS_BIGENDIAN
1961 v
= cirrus_vga_mem_readb(opaque
, addr
) << 24;
1962 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1) << 16;
1963 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 2) << 8;
1964 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 3);
1966 v
= cirrus_vga_mem_readb(opaque
, addr
);
1967 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1) << 8;
1968 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 2) << 16;
1969 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 3) << 24;
1974 static void cirrus_vga_mem_writeb(void *opaque
, target_phys_addr_t addr
,
1977 CirrusVGAState
*s
= opaque
;
1978 unsigned bank_index
;
1979 unsigned bank_offset
;
1982 if ((s
->sr
[0x07] & 0x01) == 0) {
1983 vga_mem_writeb(s
, addr
, mem_value
);
1989 if (addr
< 0x10000) {
1990 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
1992 *s
->cirrus_srcptr
++ = (uint8_t) mem_value
;
1993 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
1994 cirrus_bitblt_cputovideo_next(s
);
1998 bank_index
= addr
>> 15;
1999 bank_offset
= addr
& 0x7fff;
2000 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
2001 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
2002 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2004 } else if (s
->gr
[0x0B] & 0x02) {
2007 bank_offset
&= s
->cirrus_addr_mask
;
2008 mode
= s
->gr
[0x05] & 0x7;
2009 if (mode
< 4 || mode
> 5 || ((s
->gr
[0x0B] & 0x4) == 0)) {
2010 *(s
->vram_ptr
+ bank_offset
) = mem_value
;
2011 cpu_physical_memory_set_dirty(s
->vram_offset
+
2014 if ((s
->gr
[0x0B] & 0x14) != 0x14) {
2015 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
,
2019 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
,
2026 } else if (addr
>= 0x18000 && addr
< 0x18100) {
2027 /* memory-mapped I/O */
2028 if ((s
->sr
[0x17] & 0x44) == 0x04) {
2029 cirrus_mmio_blt_write(s
, addr
& 0xff, mem_value
);
2033 printf("cirrus: mem_writeb %06x value %02x\n", addr
, mem_value
);
2038 static void cirrus_vga_mem_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
2040 #ifdef TARGET_WORDS_BIGENDIAN
2041 cirrus_vga_mem_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2042 cirrus_vga_mem_writeb(opaque
, addr
+ 1, val
& 0xff);
2044 cirrus_vga_mem_writeb(opaque
, addr
, val
& 0xff);
2045 cirrus_vga_mem_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2049 static void cirrus_vga_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
2051 #ifdef TARGET_WORDS_BIGENDIAN
2052 cirrus_vga_mem_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2053 cirrus_vga_mem_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2054 cirrus_vga_mem_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2055 cirrus_vga_mem_writeb(opaque
, addr
+ 3, val
& 0xff);
2057 cirrus_vga_mem_writeb(opaque
, addr
, val
& 0xff);
2058 cirrus_vga_mem_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2059 cirrus_vga_mem_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2060 cirrus_vga_mem_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2064 static CPUReadMemoryFunc
*cirrus_vga_mem_read
[3] = {
2065 cirrus_vga_mem_readb
,
2066 cirrus_vga_mem_readw
,
2067 cirrus_vga_mem_readl
,
2070 static CPUWriteMemoryFunc
*cirrus_vga_mem_write
[3] = {
2071 cirrus_vga_mem_writeb
,
2072 cirrus_vga_mem_writew
,
2073 cirrus_vga_mem_writel
,
2076 /***************************************
2080 ***************************************/
2082 static inline void invalidate_cursor1(CirrusVGAState
*s
)
2084 if (s
->last_hw_cursor_size
) {
2085 vga_invalidate_scanlines((VGAState
*)s
,
2086 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_start
,
2087 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_end
);
2091 static inline void cirrus_cursor_compute_yrange(CirrusVGAState
*s
)
2095 int y
, y_min
, y_max
;
2097 src
= s
->vram_ptr
+ s
->real_vram_size
- 16 * 1024;
2098 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2099 src
+= (s
->sr
[0x13] & 0x3c) * 256;
2102 for(y
= 0; y
< 64; y
++) {
2103 content
= ((uint32_t *)src
)[0] |
2104 ((uint32_t *)src
)[1] |
2105 ((uint32_t *)src
)[2] |
2106 ((uint32_t *)src
)[3];
2116 src
+= (s
->sr
[0x13] & 0x3f) * 256;
2119 for(y
= 0; y
< 32; y
++) {
2120 content
= ((uint32_t *)src
)[0] |
2121 ((uint32_t *)(src
+ 128))[0];
2131 if (y_min
> y_max
) {
2132 s
->last_hw_cursor_y_start
= 0;
2133 s
->last_hw_cursor_y_end
= 0;
2135 s
->last_hw_cursor_y_start
= y_min
;
2136 s
->last_hw_cursor_y_end
= y_max
+ 1;
2140 /* NOTE: we do not currently handle the cursor bitmap change, so we
2141 update the cursor only if it moves. */
2142 static void cirrus_cursor_invalidate(VGAState
*s1
)
2144 CirrusVGAState
*s
= (CirrusVGAState
*)s1
;
2147 if (!s
->sr
[0x12] & CIRRUS_CURSOR_SHOW
) {
2150 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
)
2155 /* invalidate last cursor and new cursor if any change */
2156 if (s
->last_hw_cursor_size
!= size
||
2157 s
->last_hw_cursor_x
!= s
->hw_cursor_x
||
2158 s
->last_hw_cursor_y
!= s
->hw_cursor_y
) {
2160 invalidate_cursor1(s
);
2162 s
->last_hw_cursor_size
= size
;
2163 s
->last_hw_cursor_x
= s
->hw_cursor_x
;
2164 s
->last_hw_cursor_y
= s
->hw_cursor_y
;
2165 /* compute the real cursor min and max y */
2166 cirrus_cursor_compute_yrange(s
);
2167 invalidate_cursor1(s
);
2171 static void cirrus_cursor_draw_line(VGAState
*s1
, uint8_t *d1
, int scr_y
)
2173 CirrusVGAState
*s
= (CirrusVGAState
*)s1
;
2174 int w
, h
, bpp
, x1
, x2
, poffset
;
2175 unsigned int color0
, color1
;
2176 const uint8_t *palette
, *src
;
2179 if (!(s
->sr
[0x12] & CIRRUS_CURSOR_SHOW
))
2181 /* fast test to see if the cursor intersects with the scan line */
2182 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2187 if (scr_y
< s
->hw_cursor_y
||
2188 scr_y
>= (s
->hw_cursor_y
+ h
))
2191 src
= s
->vram_ptr
+ s
->real_vram_size
- 16 * 1024;
2192 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2193 src
+= (s
->sr
[0x13] & 0x3c) * 256;
2194 src
+= (scr_y
- s
->hw_cursor_y
) * 16;
2196 content
= ((uint32_t *)src
)[0] |
2197 ((uint32_t *)src
)[1] |
2198 ((uint32_t *)src
)[2] |
2199 ((uint32_t *)src
)[3];
2201 src
+= (s
->sr
[0x13] & 0x3f) * 256;
2202 src
+= (scr_y
- s
->hw_cursor_y
) * 4;
2204 content
= ((uint32_t *)src
)[0] |
2205 ((uint32_t *)(src
+ 128))[0];
2207 /* if nothing to draw, no need to continue */
2212 x1
= s
->hw_cursor_x
;
2213 if (x1
>= s
->last_scr_width
)
2215 x2
= s
->hw_cursor_x
+ w
;
2216 if (x2
> s
->last_scr_width
)
2217 x2
= s
->last_scr_width
;
2219 palette
= s
->cirrus_hidden_palette
;
2220 color0
= s
->rgb_to_pixel(c6_to_8(palette
[0x0 * 3]),
2221 c6_to_8(palette
[0x0 * 3 + 1]),
2222 c6_to_8(palette
[0x0 * 3 + 2]));
2223 color1
= s
->rgb_to_pixel(c6_to_8(palette
[0xf * 3]),
2224 c6_to_8(palette
[0xf * 3 + 1]),
2225 c6_to_8(palette
[0xf * 3 + 2]));
2226 bpp
= ((s
->ds
->depth
+ 7) >> 3);
2228 switch(s
->ds
->depth
) {
2232 vga_draw_cursor_line_8(d1
, src
, poffset
, w
, color0
, color1
, 0xff);
2235 vga_draw_cursor_line_16(d1
, src
, poffset
, w
, color0
, color1
, 0x7fff);
2238 vga_draw_cursor_line_16(d1
, src
, poffset
, w
, color0
, color1
, 0xffff);
2241 vga_draw_cursor_line_32(d1
, src
, poffset
, w
, color0
, color1
, 0xffffff);
2246 /***************************************
2250 ***************************************/
2252 static uint32_t cirrus_linear_readb(void *opaque
, target_phys_addr_t addr
)
2254 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2257 addr
&= s
->cirrus_addr_mask
;
2259 if (((s
->sr
[0x17] & 0x44) == 0x44) &&
2260 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2261 /* memory-mapped I/O */
2262 ret
= cirrus_mmio_blt_read(s
, addr
& 0xff);
2264 /* XXX handle bitblt */
2268 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2270 } else if (s
->gr
[0x0B] & 0x02) {
2273 addr
&= s
->cirrus_addr_mask
;
2274 ret
= *(s
->vram_ptr
+ addr
);
2280 static uint32_t cirrus_linear_readw(void *opaque
, target_phys_addr_t addr
)
2283 #ifdef TARGET_WORDS_BIGENDIAN
2284 v
= cirrus_linear_readb(opaque
, addr
) << 8;
2285 v
|= cirrus_linear_readb(opaque
, addr
+ 1);
2287 v
= cirrus_linear_readb(opaque
, addr
);
2288 v
|= cirrus_linear_readb(opaque
, addr
+ 1) << 8;
2293 static uint32_t cirrus_linear_readl(void *opaque
, target_phys_addr_t addr
)
2296 #ifdef TARGET_WORDS_BIGENDIAN
2297 v
= cirrus_linear_readb(opaque
, addr
) << 24;
2298 v
|= cirrus_linear_readb(opaque
, addr
+ 1) << 16;
2299 v
|= cirrus_linear_readb(opaque
, addr
+ 2) << 8;
2300 v
|= cirrus_linear_readb(opaque
, addr
+ 3);
2302 v
= cirrus_linear_readb(opaque
, addr
);
2303 v
|= cirrus_linear_readb(opaque
, addr
+ 1) << 8;
2304 v
|= cirrus_linear_readb(opaque
, addr
+ 2) << 16;
2305 v
|= cirrus_linear_readb(opaque
, addr
+ 3) << 24;
2310 static void cirrus_linear_writeb(void *opaque
, target_phys_addr_t addr
,
2313 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2316 addr
&= s
->cirrus_addr_mask
;
2318 if (((s
->sr
[0x17] & 0x44) == 0x44) &&
2319 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2320 /* memory-mapped I/O */
2321 cirrus_mmio_blt_write(s
, addr
& 0xff, val
);
2322 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2324 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2325 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2326 cirrus_bitblt_cputovideo_next(s
);
2330 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2332 } else if (s
->gr
[0x0B] & 0x02) {
2335 addr
&= s
->cirrus_addr_mask
;
2337 mode
= s
->gr
[0x05] & 0x7;
2338 if (mode
< 4 || mode
> 5 || ((s
->gr
[0x0B] & 0x4) == 0)) {
2339 *(s
->vram_ptr
+ addr
) = (uint8_t) val
;
2340 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2342 if ((s
->gr
[0x0B] & 0x14) != 0x14) {
2343 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
, addr
, val
);
2345 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
, addr
, val
);
2351 static void cirrus_linear_writew(void *opaque
, target_phys_addr_t addr
,
2354 #ifdef TARGET_WORDS_BIGENDIAN
2355 cirrus_linear_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2356 cirrus_linear_writeb(opaque
, addr
+ 1, val
& 0xff);
2358 cirrus_linear_writeb(opaque
, addr
, val
& 0xff);
2359 cirrus_linear_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2363 static void cirrus_linear_writel(void *opaque
, target_phys_addr_t addr
,
2366 #ifdef TARGET_WORDS_BIGENDIAN
2367 cirrus_linear_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2368 cirrus_linear_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2369 cirrus_linear_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2370 cirrus_linear_writeb(opaque
, addr
+ 3, val
& 0xff);
2372 cirrus_linear_writeb(opaque
, addr
, val
& 0xff);
2373 cirrus_linear_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2374 cirrus_linear_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2375 cirrus_linear_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2380 static CPUReadMemoryFunc
*cirrus_linear_read
[3] = {
2381 cirrus_linear_readb
,
2382 cirrus_linear_readw
,
2383 cirrus_linear_readl
,
2386 static CPUWriteMemoryFunc
*cirrus_linear_write
[3] = {
2387 cirrus_linear_writeb
,
2388 cirrus_linear_writew
,
2389 cirrus_linear_writel
,
2392 static void cirrus_linear_mem_writeb(void *opaque
, target_phys_addr_t addr
,
2395 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2397 addr
&= s
->cirrus_addr_mask
;
2398 *(s
->vram_ptr
+ addr
) = val
;
2399 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2402 static void cirrus_linear_mem_writew(void *opaque
, target_phys_addr_t addr
,
2405 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2407 addr
&= s
->cirrus_addr_mask
;
2408 cpu_to_le16w((uint16_t *)(s
->vram_ptr
+ addr
), val
);
2409 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2412 static void cirrus_linear_mem_writel(void *opaque
, target_phys_addr_t addr
,
2415 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2417 addr
&= s
->cirrus_addr_mask
;
2418 cpu_to_le32w((uint32_t *)(s
->vram_ptr
+ addr
), val
);
2419 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2422 /***************************************
2424 * system to screen memory access
2426 ***************************************/
2429 static uint32_t cirrus_linear_bitblt_readb(void *opaque
, target_phys_addr_t addr
)
2433 /* XXX handle bitblt */
2438 static uint32_t cirrus_linear_bitblt_readw(void *opaque
, target_phys_addr_t addr
)
2441 #ifdef TARGET_WORDS_BIGENDIAN
2442 v
= cirrus_linear_bitblt_readb(opaque
, addr
) << 8;
2443 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1);
2445 v
= cirrus_linear_bitblt_readb(opaque
, addr
);
2446 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1) << 8;
2451 static uint32_t cirrus_linear_bitblt_readl(void *opaque
, target_phys_addr_t addr
)
2454 #ifdef TARGET_WORDS_BIGENDIAN
2455 v
= cirrus_linear_bitblt_readb(opaque
, addr
) << 24;
2456 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1) << 16;
2457 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 2) << 8;
2458 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 3);
2460 v
= cirrus_linear_bitblt_readb(opaque
, addr
);
2461 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1) << 8;
2462 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 2) << 16;
2463 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 3) << 24;
2468 static void cirrus_linear_bitblt_writeb(void *opaque
, target_phys_addr_t addr
,
2471 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2473 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2475 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2476 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2477 cirrus_bitblt_cputovideo_next(s
);
2482 static void cirrus_linear_bitblt_writew(void *opaque
, target_phys_addr_t addr
,
2485 #ifdef TARGET_WORDS_BIGENDIAN
2486 cirrus_linear_bitblt_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2487 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, val
& 0xff);
2489 cirrus_linear_bitblt_writeb(opaque
, addr
, val
& 0xff);
2490 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2494 static void cirrus_linear_bitblt_writel(void *opaque
, target_phys_addr_t addr
,
2497 #ifdef TARGET_WORDS_BIGENDIAN
2498 cirrus_linear_bitblt_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2499 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2500 cirrus_linear_bitblt_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2501 cirrus_linear_bitblt_writeb(opaque
, addr
+ 3, val
& 0xff);
2503 cirrus_linear_bitblt_writeb(opaque
, addr
, val
& 0xff);
2504 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2505 cirrus_linear_bitblt_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2506 cirrus_linear_bitblt_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2511 static CPUReadMemoryFunc
*cirrus_linear_bitblt_read
[3] = {
2512 cirrus_linear_bitblt_readb
,
2513 cirrus_linear_bitblt_readw
,
2514 cirrus_linear_bitblt_readl
,
2517 static CPUWriteMemoryFunc
*cirrus_linear_bitblt_write
[3] = {
2518 cirrus_linear_bitblt_writeb
,
2519 cirrus_linear_bitblt_writew
,
2520 cirrus_linear_bitblt_writel
,
2523 /* Compute the memory access functions */
2524 static void cirrus_update_memory_access(CirrusVGAState
*s
)
2528 if ((s
->sr
[0x17] & 0x44) == 0x44) {
2530 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2533 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2535 } else if (s
->gr
[0x0B] & 0x02) {
2539 mode
= s
->gr
[0x05] & 0x7;
2540 if (mode
< 4 || mode
> 5 || ((s
->gr
[0x0B] & 0x4) == 0)) {
2541 s
->cirrus_linear_write
[0] = cirrus_linear_mem_writeb
;
2542 s
->cirrus_linear_write
[1] = cirrus_linear_mem_writew
;
2543 s
->cirrus_linear_write
[2] = cirrus_linear_mem_writel
;
2546 s
->cirrus_linear_write
[0] = cirrus_linear_writeb
;
2547 s
->cirrus_linear_write
[1] = cirrus_linear_writew
;
2548 s
->cirrus_linear_write
[2] = cirrus_linear_writel
;
2556 static uint32_t vga_ioport_read(void *opaque
, uint32_t addr
)
2558 CirrusVGAState
*s
= opaque
;
2561 /* check port range access depending on color/monochrome mode */
2562 if ((addr
>= 0x3b0 && addr
<= 0x3bf && (s
->msr
& MSR_COLOR_EMULATION
))
2563 || (addr
>= 0x3d0 && addr
<= 0x3df
2564 && !(s
->msr
& MSR_COLOR_EMULATION
))) {
2569 if (s
->ar_flip_flop
== 0) {
2576 index
= s
->ar_index
& 0x1f;
2589 if (cirrus_hook_read_sr(s
, s
->sr_index
, &val
))
2591 val
= s
->sr
[s
->sr_index
];
2592 #ifdef DEBUG_VGA_REG
2593 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
2597 cirrus_read_hidden_dac(s
, &val
);
2603 val
= s
->dac_write_index
;
2604 s
->cirrus_hidden_dac_lockindex
= 0;
2607 if (cirrus_hook_read_palette(s
, &val
))
2609 val
= s
->palette
[s
->dac_read_index
* 3 + s
->dac_sub_index
];
2610 if (++s
->dac_sub_index
== 3) {
2611 s
->dac_sub_index
= 0;
2612 s
->dac_read_index
++;
2625 if (cirrus_hook_read_gr(s
, s
->gr_index
, &val
))
2627 val
= s
->gr
[s
->gr_index
];
2628 #ifdef DEBUG_VGA_REG
2629 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
2638 if (cirrus_hook_read_cr(s
, s
->cr_index
, &val
))
2640 val
= s
->cr
[s
->cr_index
];
2641 #ifdef DEBUG_VGA_REG
2642 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
2647 /* just toggle to fool polling */
2648 s
->st01
^= ST01_V_RETRACE
| ST01_DISP_ENABLE
;
2650 s
->ar_flip_flop
= 0;
2657 #if defined(DEBUG_VGA)
2658 printf("VGA: read addr=0x%04x data=0x%02x\n", addr
, val
);
2663 static void vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
2665 CirrusVGAState
*s
= opaque
;
2668 /* check port range access depending on color/monochrome mode */
2669 if ((addr
>= 0x3b0 && addr
<= 0x3bf && (s
->msr
& MSR_COLOR_EMULATION
))
2670 || (addr
>= 0x3d0 && addr
<= 0x3df
2671 && !(s
->msr
& MSR_COLOR_EMULATION
)))
2675 printf("VGA: write addr=0x%04x data=0x%02x\n", addr
, val
);
2680 if (s
->ar_flip_flop
== 0) {
2684 index
= s
->ar_index
& 0x1f;
2687 s
->ar
[index
] = val
& 0x3f;
2690 s
->ar
[index
] = val
& ~0x10;
2696 s
->ar
[index
] = val
& ~0xc0;
2699 s
->ar
[index
] = val
& ~0xf0;
2702 s
->ar
[index
] = val
& ~0xf0;
2708 s
->ar_flip_flop
^= 1;
2711 s
->msr
= val
& ~0x10;
2717 if (cirrus_hook_write_sr(s
, s
->sr_index
, val
))
2719 #ifdef DEBUG_VGA_REG
2720 printf("vga: write SR%x = 0x%02x\n", s
->sr_index
, val
);
2722 s
->sr
[s
->sr_index
] = val
& sr_mask
[s
->sr_index
];
2725 cirrus_write_hidden_dac(s
, val
);
2728 s
->dac_read_index
= val
;
2729 s
->dac_sub_index
= 0;
2733 s
->dac_write_index
= val
;
2734 s
->dac_sub_index
= 0;
2738 if (cirrus_hook_write_palette(s
, val
))
2740 s
->dac_cache
[s
->dac_sub_index
] = val
;
2741 if (++s
->dac_sub_index
== 3) {
2742 memcpy(&s
->palette
[s
->dac_write_index
* 3], s
->dac_cache
, 3);
2743 s
->dac_sub_index
= 0;
2744 s
->dac_write_index
++;
2751 if (cirrus_hook_write_gr(s
, s
->gr_index
, val
))
2753 #ifdef DEBUG_VGA_REG
2754 printf("vga: write GR%x = 0x%02x\n", s
->gr_index
, val
);
2756 s
->gr
[s
->gr_index
] = val
& gr_mask
[s
->gr_index
];
2764 if (cirrus_hook_write_cr(s
, s
->cr_index
, val
))
2766 #ifdef DEBUG_VGA_REG
2767 printf("vga: write CR%x = 0x%02x\n", s
->cr_index
, val
);
2769 /* handle CR0-7 protection */
2770 if ((s
->cr
[0x11] & 0x80) && s
->cr_index
<= 7) {
2771 /* can always write bit 4 of CR7 */
2772 if (s
->cr_index
== 7)
2773 s
->cr
[7] = (s
->cr
[7] & ~0x10) | (val
& 0x10);
2776 switch (s
->cr_index
) {
2777 case 0x01: /* horizontal display end */
2782 case 0x12: /* veritcal display end */
2783 s
->cr
[s
->cr_index
] = val
;
2787 s
->cr
[s
->cr_index
] = val
;
2793 s
->fcr
= val
& 0x10;
2798 /***************************************
2800 * memory-mapped I/O access
2802 ***************************************/
2804 static uint32_t cirrus_mmio_readb(void *opaque
, target_phys_addr_t addr
)
2806 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2808 addr
&= CIRRUS_PNPMMIO_SIZE
- 1;
2810 if (addr
>= 0x100) {
2811 return cirrus_mmio_blt_read(s
, addr
- 0x100);
2813 return vga_ioport_read(s
, addr
+ 0x3c0);
2817 static uint32_t cirrus_mmio_readw(void *opaque
, target_phys_addr_t addr
)
2820 #ifdef TARGET_WORDS_BIGENDIAN
2821 v
= cirrus_mmio_readb(opaque
, addr
) << 8;
2822 v
|= cirrus_mmio_readb(opaque
, addr
+ 1);
2824 v
= cirrus_mmio_readb(opaque
, addr
);
2825 v
|= cirrus_mmio_readb(opaque
, addr
+ 1) << 8;
2830 static uint32_t cirrus_mmio_readl(void *opaque
, target_phys_addr_t addr
)
2833 #ifdef TARGET_WORDS_BIGENDIAN
2834 v
= cirrus_mmio_readb(opaque
, addr
) << 24;
2835 v
|= cirrus_mmio_readb(opaque
, addr
+ 1) << 16;
2836 v
|= cirrus_mmio_readb(opaque
, addr
+ 2) << 8;
2837 v
|= cirrus_mmio_readb(opaque
, addr
+ 3);
2839 v
= cirrus_mmio_readb(opaque
, addr
);
2840 v
|= cirrus_mmio_readb(opaque
, addr
+ 1) << 8;
2841 v
|= cirrus_mmio_readb(opaque
, addr
+ 2) << 16;
2842 v
|= cirrus_mmio_readb(opaque
, addr
+ 3) << 24;
2847 static void cirrus_mmio_writeb(void *opaque
, target_phys_addr_t addr
,
2850 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2852 addr
&= CIRRUS_PNPMMIO_SIZE
- 1;
2854 if (addr
>= 0x100) {
2855 cirrus_mmio_blt_write(s
, addr
- 0x100, val
);
2857 vga_ioport_write(s
, addr
+ 0x3c0, val
);
2861 static void cirrus_mmio_writew(void *opaque
, target_phys_addr_t addr
,
2864 #ifdef TARGET_WORDS_BIGENDIAN
2865 cirrus_mmio_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2866 cirrus_mmio_writeb(opaque
, addr
+ 1, val
& 0xff);
2868 cirrus_mmio_writeb(opaque
, addr
, val
& 0xff);
2869 cirrus_mmio_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2873 static void cirrus_mmio_writel(void *opaque
, target_phys_addr_t addr
,
2876 #ifdef TARGET_WORDS_BIGENDIAN
2877 cirrus_mmio_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2878 cirrus_mmio_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2879 cirrus_mmio_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2880 cirrus_mmio_writeb(opaque
, addr
+ 3, val
& 0xff);
2882 cirrus_mmio_writeb(opaque
, addr
, val
& 0xff);
2883 cirrus_mmio_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2884 cirrus_mmio_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2885 cirrus_mmio_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2890 static CPUReadMemoryFunc
*cirrus_mmio_read
[3] = {
2896 static CPUWriteMemoryFunc
*cirrus_mmio_write
[3] = {
2902 /* load/save state */
2904 static void cirrus_vga_save(QEMUFile
*f
, void *opaque
)
2906 CirrusVGAState
*s
= opaque
;
2908 qemu_put_be32s(f
, &s
->latch
);
2909 qemu_put_8s(f
, &s
->sr_index
);
2910 qemu_put_buffer(f
, s
->sr
, 256);
2911 qemu_put_8s(f
, &s
->gr_index
);
2912 qemu_put_8s(f
, &s
->cirrus_shadow_gr0
);
2913 qemu_put_8s(f
, &s
->cirrus_shadow_gr1
);
2914 qemu_put_buffer(f
, s
->gr
+ 2, 254);
2915 qemu_put_8s(f
, &s
->ar_index
);
2916 qemu_put_buffer(f
, s
->ar
, 21);
2917 qemu_put_be32s(f
, &s
->ar_flip_flop
);
2918 qemu_put_8s(f
, &s
->cr_index
);
2919 qemu_put_buffer(f
, s
->cr
, 256);
2920 qemu_put_8s(f
, &s
->msr
);
2921 qemu_put_8s(f
, &s
->fcr
);
2922 qemu_put_8s(f
, &s
->st00
);
2923 qemu_put_8s(f
, &s
->st01
);
2925 qemu_put_8s(f
, &s
->dac_state
);
2926 qemu_put_8s(f
, &s
->dac_sub_index
);
2927 qemu_put_8s(f
, &s
->dac_read_index
);
2928 qemu_put_8s(f
, &s
->dac_write_index
);
2929 qemu_put_buffer(f
, s
->dac_cache
, 3);
2930 qemu_put_buffer(f
, s
->palette
, 768);
2932 qemu_put_be32s(f
, &s
->bank_offset
);
2934 qemu_put_8s(f
, &s
->cirrus_hidden_dac_lockindex
);
2935 qemu_put_8s(f
, &s
->cirrus_hidden_dac_data
);
2937 qemu_put_be32s(f
, &s
->hw_cursor_x
);
2938 qemu_put_be32s(f
, &s
->hw_cursor_y
);
2939 /* XXX: we do not save the bitblt state - we assume we do not save
2940 the state when the blitter is active */
2943 static int cirrus_vga_load(QEMUFile
*f
, void *opaque
, int version_id
)
2945 CirrusVGAState
*s
= opaque
;
2947 if (version_id
!= 1)
2950 qemu_get_be32s(f
, &s
->latch
);
2951 qemu_get_8s(f
, &s
->sr_index
);
2952 qemu_get_buffer(f
, s
->sr
, 256);
2953 qemu_get_8s(f
, &s
->gr_index
);
2954 qemu_get_8s(f
, &s
->cirrus_shadow_gr0
);
2955 qemu_get_8s(f
, &s
->cirrus_shadow_gr1
);
2956 s
->gr
[0x00] = s
->cirrus_shadow_gr0
& 0x0f;
2957 s
->gr
[0x01] = s
->cirrus_shadow_gr1
& 0x0f;
2958 qemu_get_buffer(f
, s
->gr
+ 2, 254);
2959 qemu_get_8s(f
, &s
->ar_index
);
2960 qemu_get_buffer(f
, s
->ar
, 21);
2961 qemu_get_be32s(f
, &s
->ar_flip_flop
);
2962 qemu_get_8s(f
, &s
->cr_index
);
2963 qemu_get_buffer(f
, s
->cr
, 256);
2964 qemu_get_8s(f
, &s
->msr
);
2965 qemu_get_8s(f
, &s
->fcr
);
2966 qemu_get_8s(f
, &s
->st00
);
2967 qemu_get_8s(f
, &s
->st01
);
2969 qemu_get_8s(f
, &s
->dac_state
);
2970 qemu_get_8s(f
, &s
->dac_sub_index
);
2971 qemu_get_8s(f
, &s
->dac_read_index
);
2972 qemu_get_8s(f
, &s
->dac_write_index
);
2973 qemu_get_buffer(f
, s
->dac_cache
, 3);
2974 qemu_get_buffer(f
, s
->palette
, 768);
2976 qemu_get_be32s(f
, &s
->bank_offset
);
2978 qemu_get_8s(f
, &s
->cirrus_hidden_dac_lockindex
);
2979 qemu_get_8s(f
, &s
->cirrus_hidden_dac_data
);
2981 qemu_get_be32s(f
, &s
->hw_cursor_x
);
2982 qemu_get_be32s(f
, &s
->hw_cursor_y
);
2985 s
->graphic_mode
= -1;
2986 cirrus_update_bank_ptr(s
, 0);
2987 cirrus_update_bank_ptr(s
, 1);
2991 /***************************************
2995 ***************************************/
2997 static void cirrus_init_common(CirrusVGAState
* s
, int device_id
, int is_pci
)
2999 int vga_io_memory
, i
;
3004 for(i
= 0;i
< 256; i
++)
3005 rop_to_index
[i
] = CIRRUS_ROP_NOP_INDEX
; /* nop rop */
3006 rop_to_index
[CIRRUS_ROP_0
] = 0;
3007 rop_to_index
[CIRRUS_ROP_SRC_AND_DST
] = 1;
3008 rop_to_index
[CIRRUS_ROP_NOP
] = 2;
3009 rop_to_index
[CIRRUS_ROP_SRC_AND_NOTDST
] = 3;
3010 rop_to_index
[CIRRUS_ROP_NOTDST
] = 4;
3011 rop_to_index
[CIRRUS_ROP_SRC
] = 5;
3012 rop_to_index
[CIRRUS_ROP_1
] = 6;
3013 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_DST
] = 7;
3014 rop_to_index
[CIRRUS_ROP_SRC_XOR_DST
] = 8;
3015 rop_to_index
[CIRRUS_ROP_SRC_OR_DST
] = 9;
3016 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_NOTDST
] = 10;
3017 rop_to_index
[CIRRUS_ROP_SRC_NOTXOR_DST
] = 11;
3018 rop_to_index
[CIRRUS_ROP_SRC_OR_NOTDST
] = 12;
3019 rop_to_index
[CIRRUS_ROP_NOTSRC
] = 13;
3020 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_DST
] = 14;
3021 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_NOTDST
] = 15;
3024 register_ioport_write(0x3c0, 16, 1, vga_ioport_write
, s
);
3026 register_ioport_write(0x3b4, 2, 1, vga_ioport_write
, s
);
3027 register_ioport_write(0x3d4, 2, 1, vga_ioport_write
, s
);
3028 register_ioport_write(0x3ba, 1, 1, vga_ioport_write
, s
);
3029 register_ioport_write(0x3da, 1, 1, vga_ioport_write
, s
);
3031 register_ioport_read(0x3c0, 16, 1, vga_ioport_read
, s
);
3033 register_ioport_read(0x3b4, 2, 1, vga_ioport_read
, s
);
3034 register_ioport_read(0x3d4, 2, 1, vga_ioport_read
, s
);
3035 register_ioport_read(0x3ba, 1, 1, vga_ioport_read
, s
);
3036 register_ioport_read(0x3da, 1, 1, vga_ioport_read
, s
);
3038 vga_io_memory
= cpu_register_io_memory(0, cirrus_vga_mem_read
,
3039 cirrus_vga_mem_write
, s
);
3040 cpu_register_physical_memory(isa_mem_base
+ 0x000a0000, 0x20000,
3044 if (device_id
== CIRRUS_ID_CLGD5446
) {
3045 /* 4MB 64 bit memory config, always PCI */
3046 s
->sr
[0x1F] = 0x2d; // MemClock
3047 s
->gr
[0x18] = 0x0f; // fastest memory configuration
3051 s
->sr
[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3052 s
->real_vram_size
= 4096 * 1024;
3056 s
->sr
[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3057 s
->real_vram_size
= 2048 * 1024;
3060 s
->sr
[0x1F] = 0x22; // MemClock
3061 s
->sr
[0x0F] = CIRRUS_MEMSIZE_2M
;
3063 s
->sr
[0x17] = CIRRUS_BUSTYPE_PCI
;
3065 s
->sr
[0x17] = CIRRUS_BUSTYPE_ISA
;
3066 s
->real_vram_size
= 2048 * 1024;
3067 s
->sr
[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3069 s
->cr
[0x27] = device_id
;
3071 /* Win2K seems to assume that the pattern buffer is at 0xff
3073 memset(s
->vram_ptr
, 0xff, s
->real_vram_size
);
3075 s
->cirrus_hidden_dac_lockindex
= 5;
3076 s
->cirrus_hidden_dac_data
= 0;
3078 /* I/O handler for LFB */
3079 s
->cirrus_linear_io_addr
=
3080 cpu_register_io_memory(0, cirrus_linear_read
, cirrus_linear_write
,
3082 s
->cirrus_linear_write
= cpu_get_io_memory_write(s
->cirrus_linear_io_addr
);
3084 /* I/O handler for LFB */
3085 s
->cirrus_linear_bitblt_io_addr
=
3086 cpu_register_io_memory(0, cirrus_linear_bitblt_read
, cirrus_linear_bitblt_write
,
3089 /* I/O handler for memory-mapped I/O */
3090 s
->cirrus_mmio_io_addr
=
3091 cpu_register_io_memory(0, cirrus_mmio_read
, cirrus_mmio_write
, s
);
3093 /* XXX: s->vram_size must be a power of two */
3094 s
->cirrus_addr_mask
= s
->real_vram_size
- 1;
3095 s
->linear_mmio_mask
= s
->real_vram_size
- 256;
3097 s
->get_bpp
= cirrus_get_bpp
;
3098 s
->get_offsets
= cirrus_get_offsets
;
3099 s
->get_resolution
= cirrus_get_resolution
;
3100 s
->cursor_invalidate
= cirrus_cursor_invalidate
;
3101 s
->cursor_draw_line
= cirrus_cursor_draw_line
;
3103 register_savevm("cirrus_vga", 0, 1, cirrus_vga_save
, cirrus_vga_load
, s
);
3106 /***************************************
3110 ***************************************/
3112 void isa_cirrus_vga_init(DisplayState
*ds
, uint8_t *vga_ram_base
,
3113 unsigned long vga_ram_offset
, int vga_ram_size
)
3117 s
= qemu_mallocz(sizeof(CirrusVGAState
));
3119 vga_common_init((VGAState
*)s
,
3120 ds
, vga_ram_base
, vga_ram_offset
, vga_ram_size
);
3121 cirrus_init_common(s
, CIRRUS_ID_CLGD5430
, 0);
3122 /* XXX ISA-LFB support */
3125 /***************************************
3129 ***************************************/
3131 static void cirrus_pci_lfb_map(PCIDevice
*d
, int region_num
,
3132 uint32_t addr
, uint32_t size
, int type
)
3134 CirrusVGAState
*s
= &((PCICirrusVGAState
*)d
)->cirrus_vga
;
3136 /* XXX: add byte swapping apertures */
3137 cpu_register_physical_memory(addr
, s
->vram_size
,
3138 s
->cirrus_linear_io_addr
);
3139 cpu_register_physical_memory(addr
+ 0x1000000, 0x400000,
3140 s
->cirrus_linear_bitblt_io_addr
);
3143 static void cirrus_pci_mmio_map(PCIDevice
*d
, int region_num
,
3144 uint32_t addr
, uint32_t size
, int type
)
3146 CirrusVGAState
*s
= &((PCICirrusVGAState
*)d
)->cirrus_vga
;
3148 cpu_register_physical_memory(addr
, CIRRUS_PNPMMIO_SIZE
,
3149 s
->cirrus_mmio_io_addr
);
3152 void pci_cirrus_vga_init(PCIBus
*bus
, DisplayState
*ds
, uint8_t *vga_ram_base
,
3153 unsigned long vga_ram_offset
, int vga_ram_size
)
3155 PCICirrusVGAState
*d
;
3160 device_id
= CIRRUS_ID_CLGD5446
;
3162 /* setup PCI configuration registers */
3163 d
= (PCICirrusVGAState
*)pci_register_device(bus
, "Cirrus VGA",
3164 sizeof(PCICirrusVGAState
),
3166 pci_conf
= d
->dev
.config
;
3167 pci_conf
[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS
& 0xff);
3168 pci_conf
[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS
>> 8);
3169 pci_conf
[0x02] = (uint8_t) (device_id
& 0xff);
3170 pci_conf
[0x03] = (uint8_t) (device_id
>> 8);
3171 pci_conf
[0x04] = PCI_COMMAND_IOACCESS
| PCI_COMMAND_MEMACCESS
;
3172 pci_conf
[0x0a] = PCI_CLASS_SUB_VGA
;
3173 pci_conf
[0x0b] = PCI_CLASS_BASE_DISPLAY
;
3174 pci_conf
[0x0e] = PCI_CLASS_HEADERTYPE_00h
;
3178 vga_common_init((VGAState
*)s
,
3179 ds
, vga_ram_base
, vga_ram_offset
, vga_ram_size
);
3180 cirrus_init_common(s
, device_id
, 1);
3182 /* setup memory space */
3184 /* memory #1 memory-mapped I/O */
3185 /* XXX: s->vram_size must be a power of two */
3186 pci_register_io_region((PCIDevice
*)d
, 0, 0x2000000,
3187 PCI_ADDRESS_SPACE_MEM_PREFETCH
, cirrus_pci_lfb_map
);
3188 if (device_id
== CIRRUS_ID_CLGD5446
) {
3189 pci_register_io_region((PCIDevice
*)d
, 1, CIRRUS_PNPMMIO_SIZE
,
3190 PCI_ADDRESS_SPACE_MEM
, cirrus_pci_mmio_map
);