hw/cpu/a15mpcore.c

   1 /*
   2  * Cortex-A15MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2012 Linaro Limited.
   5  * Written by Peter Maydell.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "hw/sysbus.h"
  22 #include "sysemu/kvm.h"
  23 #include "hw/intc/arm_gic.h"
  24
  25 /* A15MP private memory region.  */
  26
  27 #define TYPE_A15MPCORE_PRIV "a15mpcore_priv"
  28 #define A15MPCORE_PRIV(obj) \
  29     OBJECT_CHECK(A15MPPrivState, (obj), TYPE_A15MPCORE_PRIV)
  30
  31 typedef struct A15MPPrivState {
  32     /*< private >*/
  33     SysBusDevice parent_obj;
  34     /*< public >*/
  35
  36     uint32_t num_cpu;
  37     uint32_t num_irq;
  38     MemoryRegion container;
  39
  40     GICState gic;
  41 } A15MPPrivState;
  42
  43 static void a15mp_priv_set_irq(void *opaque, int irq, int level)
  44 {
  45     A15MPPrivState *s = (A15MPPrivState *)opaque;
  46
  47     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  48 }
  49
  50 static void a15mp_priv_initfn(Object *obj)
  51 {
  52     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  53     A15MPPrivState *s = A15MPCORE_PRIV(obj);
  54     DeviceState *gicdev;
  55     const char *gictype = "arm_gic";
  56
  57     if (kvm_irqchip_in_kernel()) {
  58         gictype = "kvm-arm-gic";
  59     }
  60
  61     memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
  62     sysbus_init_mmio(sbd, &s->container);
  63
  64     object_initialize(&s->gic, sizeof(s->gic), gictype);
  65     gicdev = DEVICE(&s->gic);
  66     qdev_set_parent_bus(gicdev, sysbus_get_default());
  67     qdev_prop_set_uint32(gicdev, "revision", 2);
  68 }
  69
  70 static int a15mp_priv_init(SysBusDevice *dev)
  71 {
  72     A15MPPrivState *s = A15MPCORE_PRIV(dev);
  73     DeviceState *gicdev;
  74     SysBusDevice *busdev;
  75     int i;
  76
  77     gicdev = DEVICE(&s->gic);
  78     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  79     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  80     qdev_init_nofail(gicdev);
  81     busdev = SYS_BUS_DEVICE(&s->gic);
  82
  83     /* Pass through outbound IRQ lines from the GIC */
  84     sysbus_pass_irq(dev, busdev);
  85
  86     /* Pass through inbound GPIO lines to the GIC */
  87     qdev_init_gpio_in(DEVICE(dev), a15mp_priv_set_irq, s->num_irq - 32);
  88
  89     /* Wire the outputs from each CPU's generic timer to the
  90      * appropriate GIC PPI inputs
  91      */
  92     for (i = 0; i < s->num_cpu; i++) {
  93         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
  94         int ppibase = s->num_irq - 32 + i * 32;
  95         /* physical timer; we wire it up to the non-secure timer's ID,
  96          * since a real A15 always has TrustZone but QEMU doesn't.
  97          */
  98         qdev_connect_gpio_out(cpudev, 0,
  99                               qdev_get_gpio_in(gicdev, ppibase + 30));
 100         /* virtual timer */
 101         qdev_connect_gpio_out(cpudev, 1,
 102                               qdev_get_gpio_in(gicdev, ppibase + 27));
 103     }
 104
 105     /* Memory map (addresses are offsets from PERIPHBASE):
 106      *  0x0000-0x0fff -- reserved
 107      *  0x1000-0x1fff -- GIC Distributor
 108      *  0x2000-0x2fff -- GIC CPU interface
 109      *  0x4000-0x4fff -- GIC virtual interface control (not modelled)
 110      *  0x5000-0x5fff -- GIC virtual interface control (not modelled)
 111      *  0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
 112      */
 113     memory_region_add_subregion(&s->container, 0x1000,
 114                                 sysbus_mmio_get_region(busdev, 0));
 115     memory_region_add_subregion(&s->container, 0x2000,
 116                                 sysbus_mmio_get_region(busdev, 1));
 117
 118     return 0;
 119 }
 120
 121 static Property a15mp_priv_properties[] = {
 122     DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
 123     /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
 124      * IRQ lines (with another 32 internal). We default to 128+32, which
 125      * is the number provided by the Cortex-A15MP test chip in the
 126      * Versatile Express A15 development board.
 127      * Other boards may differ and should set this property appropriately.
 128      */
 129     DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
 130     DEFINE_PROP_END_OF_LIST(),
 131 };
 132
 133 static void a15mp_priv_class_init(ObjectClass *klass, void *data)
 134 {
 135     DeviceClass *dc = DEVICE_CLASS(klass);
 136     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 137     k->init = a15mp_priv_init;
 138     dc->props = a15mp_priv_properties;
 139     /* We currently have no savable state */
 140 }
 141
 142 static const TypeInfo a15mp_priv_info = {
 143     .name  = TYPE_A15MPCORE_PRIV,
 144     .parent = TYPE_SYS_BUS_DEVICE,
 145     .instance_size  = sizeof(A15MPPrivState),
 146     .instance_init = a15mp_priv_initfn,
 147     .class_init = a15mp_priv_class_init,
 148 };
 149
 150 static void a15mp_register_types(void)
 151 {
 152     type_register_static(&a15mp_priv_info);
 153 }
 154
 155 type_init(a15mp_register_types)