hw/cpu/a15mpcore.c

   1 /*
   2  * Cortex-A15MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2012 Linaro Limited.
   5  * Written by Peter Maydell.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "hw/cpu/a15mpcore.h"
  22 #include "sysemu/kvm.h"
  23 #include "kvm_arm.h"
  24
  25 static void a15mp_priv_set_irq(void *opaque, int irq, int level)
  26 {
  27     A15MPPrivState *s = (A15MPPrivState *)opaque;
  28
  29     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  30 }
  31
  32 static void a15mp_priv_initfn(Object *obj)
  33 {
  34     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  35     A15MPPrivState *s = A15MPCORE_PRIV(obj);
  36     DeviceState *gicdev;
  37
  38     memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
  39     sysbus_init_mmio(sbd, &s->container);
  40
  41     object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
  42     gicdev = DEVICE(&s->gic);
  43     qdev_set_parent_bus(gicdev, sysbus_get_default());
  44     qdev_prop_set_uint32(gicdev, "revision", 2);
  45 }
  46
  47 static void a15mp_priv_realize(DeviceState *dev, Error **errp)
  48 {
  49     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  50     A15MPPrivState *s = A15MPCORE_PRIV(dev);
  51     DeviceState *gicdev;
  52     SysBusDevice *busdev;
  53     int i;
  54     Error *err = NULL;
  55
  56     gicdev = DEVICE(&s->gic);
  57     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  58     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  59     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
  60     if (err != NULL) {
  61         error_propagate(errp, err);
  62         return;
  63     }
  64     busdev = SYS_BUS_DEVICE(&s->gic);
  65
  66     /* Pass through outbound IRQ lines from the GIC */
  67     sysbus_pass_irq(sbd, busdev);
  68
  69     /* Pass through inbound GPIO lines to the GIC */
  70     qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
  71
  72     /* Wire the outputs from each CPU's generic timer to the
  73      * appropriate GIC PPI inputs
  74      */
  75     for (i = 0; i < s->num_cpu; i++) {
  76         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
  77         int ppibase = s->num_irq - 32 + i * 32;
  78         int irq;
  79         /* Mapping from the output timer irq lines from the CPU to the
  80          * GIC PPI inputs used on the A15:
  81          */
  82         const int timer_irq[] = {
  83             [GTIMER_PHYS] = 30,
  84             [GTIMER_VIRT] = 27,
  85             [GTIMER_HYP]  = 26,
  86             [GTIMER_SEC]  = 29,
  87         };
  88         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
  89             qdev_connect_gpio_out(cpudev, irq,
  90                                   qdev_get_gpio_in(gicdev,
  91                                                    ppibase + timer_irq[irq]));
  92         }
  93     }
  94
  95     /* Memory map (addresses are offsets from PERIPHBASE):
  96      *  0x0000-0x0fff -- reserved
  97      *  0x1000-0x1fff -- GIC Distributor
  98      *  0x2000-0x2fff -- GIC CPU interface
  99      *  0x4000-0x4fff -- GIC virtual interface control (not modelled)
 100      *  0x5000-0x5fff -- GIC virtual interface control (not modelled)
 101      *  0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
 102      */
 103     memory_region_add_subregion(&s->container, 0x1000,
 104                                 sysbus_mmio_get_region(busdev, 0));
 105     memory_region_add_subregion(&s->container, 0x2000,
 106                                 sysbus_mmio_get_region(busdev, 1));
 107 }
 108
 109 static Property a15mp_priv_properties[] = {
 110     DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
 111     /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
 112      * IRQ lines (with another 32 internal). We default to 128+32, which
 113      * is the number provided by the Cortex-A15MP test chip in the
 114      * Versatile Express A15 development board.
 115      * Other boards may differ and should set this property appropriately.
 116      */
 117     DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
 118     DEFINE_PROP_END_OF_LIST(),
 119 };
 120
 121 static void a15mp_priv_class_init(ObjectClass *klass, void *data)
 122 {
 123     DeviceClass *dc = DEVICE_CLASS(klass);
 124
 125     dc->realize = a15mp_priv_realize;
 126     dc->props = a15mp_priv_properties;
 127     /* We currently have no savable state */
 128 }
 129
 130 static const TypeInfo a15mp_priv_info = {
 131     .name  = TYPE_A15MPCORE_PRIV,
 132     .parent = TYPE_SYS_BUS_DEVICE,
 133     .instance_size  = sizeof(A15MPPrivState),
 134     .instance_init = a15mp_priv_initfn,
 135     .class_init = a15mp_priv_class_init,
 136 };
 137
 138 static void a15mp_register_types(void)
 139 {
 140     type_register_static(&a15mp_priv_info);
 141 }
 142
 143 type_init(a15mp_register_types)