hw/cpu/arm11mpcore.c

   1 /*
   2  * ARM11MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "qemu/timer.h"
  12
  13 /* MPCore private memory region.  */
  14
  15 #define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv"
  16 #define ARM11MPCORE_PRIV(obj) \
  17     OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV)
  18
  19 typedef struct ARM11MPCorePriveState {
  20     SysBusDevice parent_obj;
  21
  22     uint32_t scu_control;
  23     int iomemtype;
  24     uint32_t old_timer_status[8];
  25     uint32_t num_cpu;
  26     MemoryRegion iomem;
  27     MemoryRegion container;
  28     DeviceState *mptimer;
  29     DeviceState *wdtimer;
  30     DeviceState *gic;
  31     uint32_t num_irq;
  32 } ARM11MPCorePriveState;
  33
  34 /* Per-CPU private memory mapped IO.  */
  35
  36 static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
  37                                 unsigned size)
  38 {
  39     ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
  40     int id;
  41     /* SCU */
  42     switch (offset) {
  43     case 0x00: /* Control.  */
  44         return s->scu_control;
  45     case 0x04: /* Configuration.  */
  46         id = ((1 << s->num_cpu) - 1) << 4;
  47         return id | (s->num_cpu - 1);
  48     case 0x08: /* CPU status.  */
  49         return 0;
  50     case 0x0c: /* Invalidate all.  */
  51         return 0;
  52     default:
  53         qemu_log_mask(LOG_GUEST_ERROR,
  54                       "mpcore_priv_read: Bad offset %x\n", (int)offset);
  55         return 0;
  56     }
  57 }
  58
  59 static void mpcore_scu_write(void *opaque, hwaddr offset,
  60                              uint64_t value, unsigned size)
  61 {
  62     ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
  63     /* SCU */
  64     switch (offset) {
  65     case 0: /* Control register.  */
  66         s->scu_control = value & 1;
  67         break;
  68     case 0x0c: /* Invalidate all.  */
  69         /* This is a no-op as cache is not emulated.  */
  70         break;
  71     default:
  72         qemu_log_mask(LOG_GUEST_ERROR,
  73                       "mpcore_priv_read: Bad offset %x\n", (int)offset);
  74     }
  75 }
  76
  77 static const MemoryRegionOps mpcore_scu_ops = {
  78     .read = mpcore_scu_read,
  79     .write = mpcore_scu_write,
  80     .endianness = DEVICE_NATIVE_ENDIAN,
  81 };
  82
  83 static void mpcore_priv_set_irq(void *opaque, int irq, int level)
  84 {
  85     ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
  86     qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
  87 }
  88
  89 static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
  90 {
  91     int i;
  92     SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic);
  93     SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer);
  94     SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer);
  95     memory_region_init(&s->container, OBJECT(s),
  96                        "mpcode-priv-container", 0x2000);
  97     memory_region_init_io(&s->iomem, OBJECT(s),
  98                           &mpcore_scu_ops, s, "mpcore-scu", 0x100);
  99     memory_region_add_subregion(&s->container, 0, &s->iomem);
 100     /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
 101      * at 0x200, 0x300...
 102      */
 103     for (i = 0; i < (s->num_cpu + 1); i++) {
 104         hwaddr offset = 0x100 + (i * 0x100);
 105         memory_region_add_subregion(&s->container, offset,
 106                                     sysbus_mmio_get_region(gicbusdev, i + 1));
 107     }
 108     /* Add the regions for timer and watchdog for "current CPU" and
 109      * for each specific CPU.
 110      */
 111     for (i = 0; i < (s->num_cpu + 1); i++) {
 112         /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
 113         hwaddr offset = 0x600 + i * 0x100;
 114         memory_region_add_subregion(&s->container, offset,
 115                                     sysbus_mmio_get_region(timerbusdev, i));
 116         memory_region_add_subregion(&s->container, offset + 0x20,
 117                                     sysbus_mmio_get_region(wdtbusdev, i));
 118     }
 119     memory_region_add_subregion(&s->container, 0x1000,
 120                                 sysbus_mmio_get_region(gicbusdev, 0));
 121     /* Wire up the interrupt from each watchdog and timer.
 122      * For each core the timer is PPI 29 and the watchdog PPI 30.
 123      */
 124     for (i = 0; i < s->num_cpu; i++) {
 125         int ppibase = (s->num_irq - 32) + i * 32;
 126         sysbus_connect_irq(timerbusdev, i,
 127                            qdev_get_gpio_in(s->gic, ppibase + 29));
 128         sysbus_connect_irq(wdtbusdev, i,
 129                            qdev_get_gpio_in(s->gic, ppibase + 30));
 130     }
 131 }
 132
 133 static int mpcore_priv_init(SysBusDevice *sbd)
 134 {
 135     DeviceState *dev = DEVICE(sbd);
 136     ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
 137
 138     s->gic = qdev_create(NULL, "arm_gic");
 139     qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
 140     qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
 141     /* Request the legacy 11MPCore GIC behaviour: */
 142     qdev_prop_set_uint32(s->gic, "revision", 0);
 143     qdev_init_nofail(s->gic);
 144
 145     /* Pass through outbound IRQ lines from the GIC */
 146     sysbus_pass_irq(sbd, SYS_BUS_DEVICE(s->gic));
 147
 148     /* Pass through inbound GPIO lines to the GIC */
 149     qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
 150
 151     s->mptimer = qdev_create(NULL, "arm_mptimer");
 152     qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
 153     qdev_init_nofail(s->mptimer);
 154
 155     s->wdtimer = qdev_create(NULL, "arm_mptimer");
 156     qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu);
 157     qdev_init_nofail(s->wdtimer);
 158
 159     mpcore_priv_map_setup(s);
 160     sysbus_init_mmio(sbd, &s->container);
 161     return 0;
 162 }
 163
 164 #define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
 165 #define REALVIEW_MPCORE_RIRQ(obj) \
 166     OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
 167
 168 /* Dummy PIC to route IRQ lines.  The baseboard has 4 independent IRQ
 169    controllers.  The output of these, plus some of the raw input lines
 170    are fed into a single SMP-aware interrupt controller on the CPU.  */
 171 typedef struct {
 172     SysBusDevice parent_obj;
 173
 174     SysBusDevice *priv;
 175     qemu_irq cpuic[32];
 176     qemu_irq rvic[4][64];
 177     uint32_t num_cpu;
 178 } mpcore_rirq_state;
 179
 180 /* Map baseboard IRQs onto CPU IRQ lines.  */
 181 static const int mpcore_irq_map[32] = {
 182     -1, -1, -1, -1,  1,  2, -1, -1,
 183     -1, -1,  6, -1,  4,  5, -1, -1,
 184     -1, 14, 15,  0,  7,  8, -1, -1,
 185     -1, -1, -1, -1,  9,  3, -1, -1,
 186 };
 187
 188 static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
 189 {
 190     mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
 191     int i;
 192
 193     for (i = 0; i < 4; i++) {
 194         qemu_set_irq(s->rvic[i][irq], level);
 195     }
 196     if (irq < 32) {
 197         irq = mpcore_irq_map[irq];
 198         if (irq >= 0) {
 199             qemu_set_irq(s->cpuic[irq], level);
 200         }
 201     }
 202 }
 203
 204 static int realview_mpcore_init(SysBusDevice *sbd)
 205 {
 206     DeviceState *dev = DEVICE(sbd);
 207     mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
 208     DeviceState *gic;
 209     DeviceState *priv;
 210     int n;
 211     int i;
 212
 213     priv = qdev_create(NULL, TYPE_ARM11MPCORE_PRIV);
 214     qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
 215     qdev_init_nofail(priv);
 216     s->priv = SYS_BUS_DEVICE(priv);
 217     sysbus_pass_irq(sbd, s->priv);
 218     for (i = 0; i < 32; i++) {
 219         s->cpuic[i] = qdev_get_gpio_in(priv, i);
 220     }
 221     /* ??? IRQ routing is hardcoded to "normal" mode.  */
 222     for (n = 0; n < 4; n++) {
 223         gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
 224                                    s->cpuic[10 + n]);
 225         for (i = 0; i < 64; i++) {
 226             s->rvic[n][i] = qdev_get_gpio_in(gic, i);
 227         }
 228     }
 229     qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
 230     sysbus_init_mmio(sbd, sysbus_mmio_get_region(s->priv, 0));
 231     return 0;
 232 }
 233
 234 static Property mpcore_rirq_properties[] = {
 235     DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
 236     DEFINE_PROP_END_OF_LIST(),
 237 };
 238
 239 static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
 240 {
 241     DeviceClass *dc = DEVICE_CLASS(klass);
 242     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 243
 244     k->init = realview_mpcore_init;
 245     dc->props = mpcore_rirq_properties;
 246 }
 247
 248 static const TypeInfo mpcore_rirq_info = {
 249     .name          = TYPE_REALVIEW_MPCORE_RIRQ,
 250     .parent        = TYPE_SYS_BUS_DEVICE,
 251     .instance_size = sizeof(mpcore_rirq_state),
 252     .class_init    = mpcore_rirq_class_init,
 253 };
 254
 255 static Property mpcore_priv_properties[] = {
 256     DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
 257     /* The ARM11 MPCORE TRM says the on-chip controller may have
 258      * anything from 0 to 224 external interrupt IRQ lines (with another
 259      * 32 internal). We default to 32+32, which is the number provided by
 260      * the ARM11 MPCore test chip in the Realview Versatile Express
 261      * coretile. Other boards may differ and should set this property
 262      * appropriately. Some Linux kernels may not boot if the hardware
 263      * has more IRQ lines than the kernel expects.
 264      */
 265     DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
 266     DEFINE_PROP_END_OF_LIST(),
 267 };
 268
 269 static void mpcore_priv_class_init(ObjectClass *klass, void *data)
 270 {
 271     DeviceClass *dc = DEVICE_CLASS(klass);
 272     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 273
 274     k->init = mpcore_priv_init;
 275     dc->props = mpcore_priv_properties;
 276 }
 277
 278 static const TypeInfo mpcore_priv_info = {
 279     .name          = TYPE_ARM11MPCORE_PRIV,
 280     .parent        = TYPE_SYS_BUS_DEVICE,
 281     .instance_size = sizeof(ARM11MPCorePriveState),
 282     .class_init    = mpcore_priv_class_init,
 283 };
 284
 285 static void arm11mpcore_register_types(void)
 286 {
 287     type_register_static(&mpcore_rirq_info);
 288     type_register_static(&mpcore_priv_info);
 289 }
 290
 291 type_init(arm11mpcore_register_types)