hw/cs4231.c

   1 /*
   2  * QEMU Crystal CS4231 audio chip emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sun4m.h"
  26 #include "sysbus.h"
  27
  28 /* debug CS4231 */
  29 //#define DEBUG_CS
  30
  31 /*
  32  * In addition to Crystal CS4231 there is a DMA controller on Sparc.
  33  */
  34 #define CS_SIZE 0x40
  35 #define CS_REGS 16
  36 #define CS_DREGS 32
  37 #define CS_MAXDREG (CS_DREGS - 1)
  38
  39 typedef struct CSState {
  40     SysBusDevice busdev;
  41     qemu_irq irq;
  42     uint32_t regs[CS_REGS];
  43     uint8_t dregs[CS_DREGS];
  44 } CSState;
  45
  46 #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
  47 #define CS_VER 0xa0
  48 #define CS_CDC_VER 0x8a
  49
  50 #ifdef DEBUG_CS
  51 #define DPRINTF(fmt, ...)                                       \
  52     do { printf("CS: " fmt , ## __VA_ARGS__); } while (0)
  53 #else
  54 #define DPRINTF(fmt, ...)
  55 #endif
  56
  57 static void cs_reset(void *opaque)
  58 {
  59     CSState *s = opaque;
  60
  61     memset(s->regs, 0, CS_REGS * 4);
  62     memset(s->dregs, 0, CS_DREGS);
  63     s->dregs[12] = CS_CDC_VER;
  64     s->dregs[25] = CS_VER;
  65 }
  66
  67 static uint32_t cs_mem_readl(void *opaque, a_target_phys_addr addr)
  68 {
  69     CSState *s = opaque;
  70     uint32_t saddr, ret;
  71
  72     saddr = addr >> 2;
  73     switch (saddr) {
  74     case 1:
  75         switch (CS_RAP(s)) {
  76         case 3: // Write only
  77             ret = 0;
  78             break;
  79         default:
  80             ret = s->dregs[CS_RAP(s)];
  81             break;
  82         }
  83         DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
  84         break;
  85     default:
  86         ret = s->regs[saddr];
  87         DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
  88         break;
  89     }
  90     return ret;
  91 }
  92
  93 static void cs_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
  94 {
  95     CSState *s = opaque;
  96     uint32_t saddr;
  97
  98     saddr = addr >> 2;
  99     DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
 100     switch (saddr) {
 101     case 1:
 102         DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s),
 103                 s->dregs[CS_RAP(s)], val);
 104         switch(CS_RAP(s)) {
 105         case 11:
 106         case 25: // Read only
 107             break;
 108         case 12:
 109             val &= 0x40;
 110             val |= CS_CDC_VER; // Codec version
 111             s->dregs[CS_RAP(s)] = val;
 112             break;
 113         default:
 114             s->dregs[CS_RAP(s)] = val;
 115             break;
 116         }
 117         break;
 118     case 2: // Read only
 119         break;
 120     case 4:
 121         if (val & 1)
 122             cs_reset(s);
 123         val &= 0x7f;
 124         s->regs[saddr] = val;
 125         break;
 126     default:
 127         s->regs[saddr] = val;
 128         break;
 129     }
 130 }
 131
 132 static CPUReadMemoryFunc * const cs_mem_read[3] = {
 133     cs_mem_readl,
 134     cs_mem_readl,
 135     cs_mem_readl,
 136 };
 137
 138 static CPUWriteMemoryFunc * const cs_mem_write[3] = {
 139     cs_mem_writel,
 140     cs_mem_writel,
 141     cs_mem_writel,
 142 };
 143
 144 static void cs_save(QEMUFile *f, void *opaque)
 145 {
 146     CSState *s = opaque;
 147     unsigned int i;
 148
 149     for (i = 0; i < CS_REGS; i++)
 150         qemu_put_be32s(f, &s->regs[i]);
 151
 152     qemu_put_buffer(f, s->dregs, CS_DREGS);
 153 }
 154
 155 static int cs_load(QEMUFile *f, void *opaque, int version_id)
 156 {
 157     CSState *s = opaque;
 158     unsigned int i;
 159
 160     if (version_id > 1)
 161         return -EINVAL;
 162
 163     for (i = 0; i < CS_REGS; i++)
 164         qemu_get_be32s(f, &s->regs[i]);
 165
 166     qemu_get_buffer(f, s->dregs, CS_DREGS);
 167     return 0;
 168 }
 169
 170 static int cs4231_init1(SysBusDevice *dev)
 171 {
 172     int io;
 173     CSState *s = FROM_SYSBUS(CSState, dev);
 174
 175     io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s);
 176     sysbus_init_mmio(dev, CS_SIZE, io);
 177     sysbus_init_irq(dev, &s->irq);
 178
 179     register_savevm("cs4231", -1, 1, cs_save, cs_load, s);
 180     qemu_register_reset(cs_reset, s);
 181     cs_reset(s);
 182     return 0;
 183 }
 184
 185 static SysBusDeviceInfo cs4231_info = {
 186     .init = cs4231_init1,
 187     .qdev.name  = "SUNW,CS4231",
 188     .qdev.size  = sizeof(CSState),
 189     .qdev.props = (Property[]) {
 190         {.name = NULL}
 191     }
 192 };
 193
 194 static void cs4231_register_devices(void)
 195 {
 196     sysbus_register_withprop(&cs4231_info);
 197 }
 198
 199 device_init(cs4231_register_devices)