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2 * QEMU PowerMac CUDA device support
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu-timer.h"
30 /* XXX: implement all timer modes */
35 /* debug CUDA packets */
36 //#define DEBUG_CUDA_PACKET
39 #define CUDA_DPRINTF(fmt, ...) \
40 do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0)
42 #define CUDA_DPRINTF(fmt, ...)
45 /* Bits in B data register: all active low */
46 #define TREQ 0x08 /* Transfer request (input) */
47 #define TACK 0x10 /* Transfer acknowledge (output) */
48 #define TIP 0x20 /* Transfer in progress (output) */
51 #define SR_CTRL 0x1c /* Shift register control bits */
52 #define SR_EXT 0x0c /* Shift on external clock */
53 #define SR_OUT 0x10 /* Shift out if 1 */
55 /* Bits in IFR and IER */
56 #define IER_SET 0x80 /* set bits in IER */
57 #define IER_CLR 0 /* clear bits in IER */
58 #define SR_INT 0x04 /* Shift register full/empty */
59 #define T1_INT 0x40 /* Timer 1 interrupt */
60 #define T2_INT 0x20 /* Timer 2 interrupt */
63 #define T1MODE 0xc0 /* Timer 1 mode */
64 #define T1MODE_CONT 0x40 /* continuous interrupts */
66 /* commands (1st byte) */
69 #define ERROR_PACKET 2
70 #define TIMER_PACKET 3
71 #define POWER_PACKET 4
72 #define MACIIC_PACKET 5
76 /* CUDA commands (2nd byte) */
77 #define CUDA_WARM_START 0x0
78 #define CUDA_AUTOPOLL 0x1
79 #define CUDA_GET_6805_ADDR 0x2
80 #define CUDA_GET_TIME 0x3
81 #define CUDA_GET_PRAM 0x7
82 #define CUDA_SET_6805_ADDR 0x8
83 #define CUDA_SET_TIME 0x9
84 #define CUDA_POWERDOWN 0xa
85 #define CUDA_POWERUP_TIME 0xb
86 #define CUDA_SET_PRAM 0xc
87 #define CUDA_MS_RESET 0xd
88 #define CUDA_SEND_DFAC 0xe
89 #define CUDA_BATTERY_SWAP_SENSE 0x10
90 #define CUDA_RESET_SYSTEM 0x11
91 #define CUDA_SET_IPL 0x12
92 #define CUDA_FILE_SERVER_FLAG 0x13
93 #define CUDA_SET_AUTO_RATE 0x14
94 #define CUDA_GET_AUTO_RATE 0x16
95 #define CUDA_SET_DEVICE_LIST 0x19
96 #define CUDA_GET_DEVICE_LIST 0x1a
97 #define CUDA_SET_ONE_SECOND_MODE 0x1b
98 #define CUDA_SET_POWER_MESSAGES 0x21
99 #define CUDA_GET_SET_IIC 0x22
100 #define CUDA_WAKEUP 0x23
101 #define CUDA_TIMER_TICKLE 0x24
102 #define CUDA_COMBINED_FORMAT_IIC 0x25
104 #define CUDA_TIMER_FREQ (4700000 / 6)
105 #define CUDA_ADB_POLL_FREQ 50
107 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
108 #define RTC_OFFSET 2082844800
110 typedef struct CUDATimer
{
113 uint16_t counter_value
; /* counter value at load time */
115 int64_t next_irq_time
;
119 typedef struct CUDAState
{
121 uint8_t b
; /* B-side data */
122 uint8_t a
; /* A-side data */
123 uint8_t dirb
; /* B-side direction (1=output) */
124 uint8_t dira
; /* A-side direction (1=output) */
125 uint8_t sr
; /* Shift register */
126 uint8_t acr
; /* Auxiliary control register */
127 uint8_t pcr
; /* Peripheral control register */
128 uint8_t ifr
; /* Interrupt flag register */
129 uint8_t ier
; /* Interrupt enable register */
130 uint8_t anh
; /* A-side data, no handshake */
134 uint32_t tick_offset
;
136 uint8_t last_b
; /* last value of B register */
137 uint8_t last_acr
; /* last value of B register */
145 uint8_t data_in
[128];
146 uint8_t data_out
[16];
147 QEMUTimer
*adb_poll_timer
;
150 static CUDAState cuda_state
;
153 static void cuda_update(CUDAState
*s
);
154 static void cuda_receive_packet_from_host(CUDAState
*s
,
155 const uint8_t *data
, int len
);
156 static void cuda_timer_update(CUDAState
*s
, CUDATimer
*ti
,
157 int64_t current_time
);
159 static void cuda_update_irq(CUDAState
*s
)
161 if (s
->ifr
& s
->ier
& (SR_INT
| T1_INT
)) {
162 qemu_irq_raise(s
->irq
);
164 qemu_irq_lower(s
->irq
);
168 static unsigned int get_counter(CUDATimer
*s
)
171 unsigned int counter
;
173 d
= muldiv64(qemu_get_clock(vm_clock
) - s
->load_time
,
174 CUDA_TIMER_FREQ
, get_ticks_per_sec());
176 /* the timer goes down from latch to -1 (period of latch + 2) */
177 if (d
<= (s
->counter_value
+ 1)) {
178 counter
= (s
->counter_value
- d
) & 0xffff;
180 counter
= (d
- (s
->counter_value
+ 1)) % (s
->latch
+ 2);
181 counter
= (s
->latch
- counter
) & 0xffff;
184 counter
= (s
->counter_value
- d
) & 0xffff;
189 static void set_counter(CUDAState
*s
, CUDATimer
*ti
, unsigned int val
)
191 CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti
->timer
== NULL
), val
);
192 ti
->load_time
= qemu_get_clock(vm_clock
);
193 ti
->counter_value
= val
;
194 cuda_timer_update(s
, ti
, ti
->load_time
);
197 static int64_t get_next_irq_time(CUDATimer
*s
, int64_t current_time
)
199 int64_t d
, next_time
;
200 unsigned int counter
;
202 /* current counter value */
203 d
= muldiv64(current_time
- s
->load_time
,
204 CUDA_TIMER_FREQ
, get_ticks_per_sec());
205 /* the timer goes down from latch to -1 (period of latch + 2) */
206 if (d
<= (s
->counter_value
+ 1)) {
207 counter
= (s
->counter_value
- d
) & 0xffff;
209 counter
= (d
- (s
->counter_value
+ 1)) % (s
->latch
+ 2);
210 counter
= (s
->latch
- counter
) & 0xffff;
213 /* Note: we consider the irq is raised on 0 */
214 if (counter
== 0xffff) {
215 next_time
= d
+ s
->latch
+ 1;
216 } else if (counter
== 0) {
217 next_time
= d
+ s
->latch
+ 2;
219 next_time
= d
+ counter
;
221 CUDA_DPRINTF("latch=%d counter=%" PRId64
" delta_next=%" PRId64
"\n",
222 s
->latch
, d
, next_time
- d
);
223 next_time
= muldiv64(next_time
, get_ticks_per_sec(), CUDA_TIMER_FREQ
) +
225 if (next_time
<= current_time
)
226 next_time
= current_time
+ 1;
230 static void cuda_timer_update(CUDAState
*s
, CUDATimer
*ti
,
231 int64_t current_time
)
235 if ((s
->acr
& T1MODE
) != T1MODE_CONT
) {
236 qemu_del_timer(ti
->timer
);
238 ti
->next_irq_time
= get_next_irq_time(ti
, current_time
);
239 qemu_mod_timer(ti
->timer
, ti
->next_irq_time
);
243 static void cuda_timer1(void *opaque
)
245 CUDAState
*s
= opaque
;
246 CUDATimer
*ti
= &s
->timers
[0];
248 cuda_timer_update(s
, ti
, ti
->next_irq_time
);
253 static uint32_t cuda_readb(void *opaque
, target_phys_addr_t addr
)
255 CUDAState
*s
= opaque
;
258 addr
= (addr
>> 9) & 0xf;
273 val
= get_counter(&s
->timers
[0]) & 0xff;
278 val
= get_counter(&s
->timers
[0]) >> 8;
282 val
= s
->timers
[0].latch
& 0xff;
285 /* XXX: check this */
286 val
= (s
->timers
[0].latch
>> 8) & 0xff;
289 val
= get_counter(&s
->timers
[1]) & 0xff;
293 val
= get_counter(&s
->timers
[1]) >> 8;
319 if (addr
!= 13 || val
!= 0) {
320 CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr
, val
);
326 static void cuda_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
328 CUDAState
*s
= opaque
;
330 addr
= (addr
>> 9) & 0xf;
331 CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr
, val
);
348 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff00) | val
;
349 cuda_timer_update(s
, &s
->timers
[0], qemu_get_clock(vm_clock
));
352 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff) | (val
<< 8);
354 set_counter(s
, &s
->timers
[0], s
->timers
[0].latch
);
357 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff00) | val
;
358 cuda_timer_update(s
, &s
->timers
[0], qemu_get_clock(vm_clock
));
361 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff) | (val
<< 8);
363 cuda_timer_update(s
, &s
->timers
[0], qemu_get_clock(vm_clock
));
366 s
->timers
[1].latch
= val
;
367 set_counter(s
, &s
->timers
[1], val
);
370 set_counter(s
, &s
->timers
[1], (val
<< 8) | s
->timers
[1].latch
);
377 cuda_timer_update(s
, &s
->timers
[0], qemu_get_clock(vm_clock
));
391 s
->ier
|= val
& 0x7f;
405 /* NOTE: TIP and TREQ are negated */
406 static void cuda_update(CUDAState
*s
)
408 int packet_received
, len
;
412 /* transfer requested from host */
414 if (s
->acr
& SR_OUT
) {
416 if ((s
->b
& (TACK
| TIP
)) != (s
->last_b
& (TACK
| TIP
))) {
417 if (s
->data_out_index
< sizeof(s
->data_out
)) {
418 CUDA_DPRINTF("send: %02x\n", s
->sr
);
419 s
->data_out
[s
->data_out_index
++] = s
->sr
;
425 if (s
->data_in_index
< s
->data_in_size
) {
427 if ((s
->b
& (TACK
| TIP
)) != (s
->last_b
& (TACK
| TIP
))) {
428 s
->sr
= s
->data_in
[s
->data_in_index
++];
429 CUDA_DPRINTF("recv: %02x\n", s
->sr
);
430 /* indicate end of transfer */
431 if (s
->data_in_index
>= s
->data_in_size
) {
432 s
->b
= (s
->b
| TREQ
);
440 /* no transfer requested: handle sync case */
441 if ((s
->last_b
& TIP
) && (s
->b
& TACK
) != (s
->last_b
& TACK
)) {
442 /* update TREQ state each time TACK change state */
444 s
->b
= (s
->b
| TREQ
);
446 s
->b
= (s
->b
& ~TREQ
);
450 if (!(s
->last_b
& TIP
)) {
451 /* handle end of host to cuda transfer */
452 packet_received
= (s
->data_out_index
> 0);
453 /* always an IRQ at the end of transfer */
457 /* signal if there is data to read */
458 if (s
->data_in_index
< s
->data_in_size
) {
459 s
->b
= (s
->b
& ~TREQ
);
464 s
->last_acr
= s
->acr
;
467 /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
469 if (packet_received
) {
470 len
= s
->data_out_index
;
471 s
->data_out_index
= 0;
472 cuda_receive_packet_from_host(s
, s
->data_out
, len
);
476 static void cuda_send_packet_to_host(CUDAState
*s
,
477 const uint8_t *data
, int len
)
479 #ifdef DEBUG_CUDA_PACKET
482 printf("cuda_send_packet_to_host:\n");
483 for(i
= 0; i
< len
; i
++)
484 printf(" %02x", data
[i
]);
488 memcpy(s
->data_in
, data
, len
);
489 s
->data_in_size
= len
;
490 s
->data_in_index
= 0;
496 static void cuda_adb_poll(void *opaque
)
498 CUDAState
*s
= opaque
;
499 uint8_t obuf
[ADB_MAX_OUT_LEN
+ 2];
502 olen
= adb_poll(&adb_bus
, obuf
+ 2);
504 obuf
[0] = ADB_PACKET
;
505 obuf
[1] = 0x40; /* polled data */
506 cuda_send_packet_to_host(s
, obuf
, olen
+ 2);
508 qemu_mod_timer(s
->adb_poll_timer
,
509 qemu_get_clock(vm_clock
) +
510 (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ
));
513 static void cuda_receive_packet(CUDAState
*s
,
514 const uint8_t *data
, int len
)
522 autopoll
= (data
[1] != 0);
523 if (autopoll
!= s
->autopoll
) {
524 s
->autopoll
= autopoll
;
526 qemu_mod_timer(s
->adb_poll_timer
,
527 qemu_get_clock(vm_clock
) +
528 (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ
));
530 qemu_del_timer(s
->adb_poll_timer
);
533 obuf
[0] = CUDA_PACKET
;
535 cuda_send_packet_to_host(s
, obuf
, 2);
538 ti
= (((uint32_t)data
[1]) << 24) + (((uint32_t)data
[2]) << 16) + (((uint32_t)data
[3]) << 8) + data
[4];
539 s
->tick_offset
= ti
- (qemu_get_clock(vm_clock
) / get_ticks_per_sec());
540 obuf
[0] = CUDA_PACKET
;
543 cuda_send_packet_to_host(s
, obuf
, 3);
546 ti
= s
->tick_offset
+ (qemu_get_clock(vm_clock
) / get_ticks_per_sec());
547 obuf
[0] = CUDA_PACKET
;
554 cuda_send_packet_to_host(s
, obuf
, 7);
556 case CUDA_FILE_SERVER_FLAG
:
557 case CUDA_SET_DEVICE_LIST
:
558 case CUDA_SET_AUTO_RATE
:
559 case CUDA_SET_POWER_MESSAGES
:
560 obuf
[0] = CUDA_PACKET
;
562 cuda_send_packet_to_host(s
, obuf
, 2);
565 obuf
[0] = CUDA_PACKET
;
567 cuda_send_packet_to_host(s
, obuf
, 2);
568 qemu_system_shutdown_request();
570 case CUDA_RESET_SYSTEM
:
571 obuf
[0] = CUDA_PACKET
;
573 cuda_send_packet_to_host(s
, obuf
, 2);
574 qemu_system_reset_request();
581 static void cuda_receive_packet_from_host(CUDAState
*s
,
582 const uint8_t *data
, int len
)
584 #ifdef DEBUG_CUDA_PACKET
587 printf("cuda_receive_packet_from_host:\n");
588 for(i
= 0; i
< len
; i
++)
589 printf(" %02x", data
[i
]);
596 uint8_t obuf
[ADB_MAX_OUT_LEN
+ 2];
598 olen
= adb_request(&adb_bus
, obuf
+ 2, data
+ 1, len
- 1);
600 obuf
[0] = ADB_PACKET
;
604 obuf
[0] = ADB_PACKET
;
608 cuda_send_packet_to_host(s
, obuf
, olen
+ 2);
612 cuda_receive_packet(s
, data
+ 1, len
- 1);
617 static void cuda_writew (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
621 static void cuda_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
625 static uint32_t cuda_readw (void *opaque
, target_phys_addr_t addr
)
630 static uint32_t cuda_readl (void *opaque
, target_phys_addr_t addr
)
635 static CPUWriteMemoryFunc
* const cuda_write
[] = {
641 static CPUReadMemoryFunc
* const cuda_read
[] = {
647 static void cuda_save_timer(QEMUFile
*f
, CUDATimer
*s
)
649 qemu_put_be16s(f
, &s
->latch
);
650 qemu_put_be16s(f
, &s
->counter_value
);
651 qemu_put_sbe64s(f
, &s
->load_time
);
652 qemu_put_sbe64s(f
, &s
->next_irq_time
);
654 qemu_put_timer(f
, s
->timer
);
657 static void cuda_save(QEMUFile
*f
, void *opaque
)
659 CUDAState
*s
= (CUDAState
*)opaque
;
661 qemu_put_ubyte(f
, s
->b
);
662 qemu_put_ubyte(f
, s
->a
);
663 qemu_put_ubyte(f
, s
->dirb
);
664 qemu_put_ubyte(f
, s
->dira
);
665 qemu_put_ubyte(f
, s
->sr
);
666 qemu_put_ubyte(f
, s
->acr
);
667 qemu_put_ubyte(f
, s
->pcr
);
668 qemu_put_ubyte(f
, s
->ifr
);
669 qemu_put_ubyte(f
, s
->ier
);
670 qemu_put_ubyte(f
, s
->anh
);
671 qemu_put_sbe32s(f
, &s
->data_in_size
);
672 qemu_put_sbe32s(f
, &s
->data_in_index
);
673 qemu_put_sbe32s(f
, &s
->data_out_index
);
674 qemu_put_ubyte(f
, s
->autopoll
);
675 qemu_put_buffer(f
, s
->data_in
, sizeof(s
->data_in
));
676 qemu_put_buffer(f
, s
->data_out
, sizeof(s
->data_out
));
677 qemu_put_be32s(f
, &s
->tick_offset
);
678 cuda_save_timer(f
, &s
->timers
[0]);
679 cuda_save_timer(f
, &s
->timers
[1]);
682 static void cuda_load_timer(QEMUFile
*f
, CUDATimer
*s
)
684 qemu_get_be16s(f
, &s
->latch
);
685 qemu_get_be16s(f
, &s
->counter_value
);
686 qemu_get_sbe64s(f
, &s
->load_time
);
687 qemu_get_sbe64s(f
, &s
->next_irq_time
);
689 qemu_get_timer(f
, s
->timer
);
692 static int cuda_load(QEMUFile
*f
, void *opaque
, int version_id
)
694 CUDAState
*s
= (CUDAState
*)opaque
;
699 s
->b
= qemu_get_ubyte(f
);
700 s
->a
= qemu_get_ubyte(f
);
701 s
->dirb
= qemu_get_ubyte(f
);
702 s
->dira
= qemu_get_ubyte(f
);
703 s
->sr
= qemu_get_ubyte(f
);
704 s
->acr
= qemu_get_ubyte(f
);
705 s
->pcr
= qemu_get_ubyte(f
);
706 s
->ifr
= qemu_get_ubyte(f
);
707 s
->ier
= qemu_get_ubyte(f
);
708 s
->anh
= qemu_get_ubyte(f
);
709 qemu_get_sbe32s(f
, &s
->data_in_size
);
710 qemu_get_sbe32s(f
, &s
->data_in_index
);
711 qemu_get_sbe32s(f
, &s
->data_out_index
);
712 s
->autopoll
= qemu_get_ubyte(f
);
713 qemu_get_buffer(f
, s
->data_in
, sizeof(s
->data_in
));
714 qemu_get_buffer(f
, s
->data_out
, sizeof(s
->data_out
));
715 qemu_get_be32s(f
, &s
->tick_offset
);
716 cuda_load_timer(f
, &s
->timers
[0]);
717 cuda_load_timer(f
, &s
->timers
[1]);
722 static void cuda_reset(void *opaque
)
724 CUDAState
*s
= opaque
;
735 // s->ier = T1_INT | SR_INT;
738 s
->data_in_index
= 0;
739 s
->data_out_index
= 0;
742 s
->timers
[0].latch
= 0xffff;
743 set_counter(s
, &s
->timers
[0], 0xffff);
745 s
->timers
[1].latch
= 0;
746 set_counter(s
, &s
->timers
[1], 0xffff);
749 void cuda_init (int *cuda_mem_index
, qemu_irq irq
)
752 CUDAState
*s
= &cuda_state
;
756 s
->timers
[0].index
= 0;
757 s
->timers
[0].timer
= qemu_new_timer(vm_clock
, cuda_timer1
, s
);
759 s
->timers
[1].index
= 1;
761 qemu_get_timedate(&tm
, 0);
762 s
->tick_offset
= (uint32_t)mktimegm(&tm
) + RTC_OFFSET
;
764 s
->adb_poll_timer
= qemu_new_timer(vm_clock
, cuda_adb_poll
, s
);
765 *cuda_mem_index
= cpu_register_io_memory(cuda_read
, cuda_write
, s
,
766 DEVICE_NATIVE_ENDIAN
);
767 register_savevm(NULL
, "cuda", -1, 1, cuda_save
, cuda_load
, s
);
768 qemu_register_reset(cuda_reset
, s
);