hw/cuda.c

   1 /*
   2  * QEMU CUDA support
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* Bits in B data register: all active low */
  27 #define TREQ            0x08            /* Transfer request (input) */
  28 #define TACK            0x10            /* Transfer acknowledge (output) */
  29 #define TIP             0x20            /* Transfer in progress (output) */
  30
  31 /* Bits in ACR */
  32 #define SR_CTRL         0x1c            /* Shift register control bits */
  33 #define SR_EXT          0x0c            /* Shift on external clock */
  34 #define SR_OUT          0x10            /* Shift out if 1 */
  35
  36 /* Bits in IFR and IER */
  37 #define IER_SET         0x80            /* set bits in IER */
  38 #define IER_CLR         0               /* clear bits in IER */
  39 #define SR_INT          0x04            /* Shift register full/empty */
  40 #define T1_INT          0x40            /* Timer 1 interrupt */
  41
  42 /* Bits in ACR */
  43 #define T1MODE          0xc0            /* Timer 1 mode */
  44 #define T1MODE_CONT     0x40            /*  continuous interrupts */
  45
  46 /* commands (1st byte) */
  47 #define ADB_PACKET      0
  48 #define CUDA_PACKET     1
  49 #define ERROR_PACKET    2
  50 #define TIMER_PACKET    3
  51 #define POWER_PACKET    4
  52 #define MACIIC_PACKET   5
  53 #define PMU_PACKET      6
  54
  55
  56 /* CUDA commands (2nd byte) */
  57 #define CUDA_WARM_START                 0x0
  58 #define CUDA_AUTOPOLL                   0x1
  59 #define CUDA_GET_6805_ADDR              0x2
  60 #define CUDA_GET_TIME                   0x3
  61 #define CUDA_GET_PRAM                   0x7
  62 #define CUDA_SET_6805_ADDR              0x8
  63 #define CUDA_SET_TIME                   0x9
  64 #define CUDA_POWERDOWN                  0xa
  65 #define CUDA_POWERUP_TIME               0xb
  66 #define CUDA_SET_PRAM                   0xc
  67 #define CUDA_MS_RESET                   0xd
  68 #define CUDA_SEND_DFAC                  0xe
  69 #define CUDA_BATTERY_SWAP_SENSE         0x10
  70 #define CUDA_RESET_SYSTEM               0x11
  71 #define CUDA_SET_IPL                    0x12
  72 #define CUDA_FILE_SERVER_FLAG           0x13
  73 #define CUDA_SET_AUTO_RATE              0x14
  74 #define CUDA_GET_AUTO_RATE              0x16
  75 #define CUDA_SET_DEVICE_LIST            0x19
  76 #define CUDA_GET_DEVICE_LIST            0x1a
  77 #define CUDA_SET_ONE_SECOND_MODE        0x1b
  78 #define CUDA_SET_POWER_MESSAGES         0x21
  79 #define CUDA_GET_SET_IIC                0x22
  80 #define CUDA_WAKEUP                     0x23
  81 #define CUDA_TIMER_TICKLE               0x24
  82 #define CUDA_COMBINED_FORMAT_IIC        0x25
  83
  84 #define CUDA_TIMER_FREQ (4700000 / 6)
  85
  86 typedef struct CUDATimer {
  87     unsigned int latch;
  88     uint16_t counter_value; /* counter value at load time */
  89     int64_t load_time;
  90     int64_t next_irq_time;
  91     QEMUTimer *timer;
  92 } CUDATimer;
  93
  94 typedef struct CUDAState {
  95     /* cuda registers */
  96     uint8_t b;      /* B-side data */
  97     uint8_t a;      /* A-side data */
  98     uint8_t dirb;   /* B-side direction (1=output) */
  99     uint8_t dira;   /* A-side direction (1=output) */
 100     uint8_t sr;     /* Shift register */
 101     uint8_t acr;    /* Auxiliary control register */
 102     uint8_t pcr;    /* Peripheral control register */
 103     uint8_t ifr;    /* Interrupt flag register */
 104     uint8_t ier;    /* Interrupt enable register */
 105     uint8_t anh;    /* A-side data, no handshake */
 106
 107     CUDATimer timers[2];
 108
 109     uint8_t last_b; /* last value of B register */
 110     uint8_t last_acr; /* last value of B register */
 111
 112     int data_in_size;
 113     int data_in_index;
 114     int data_out_index;
 115
 116     int irq;
 117     uint8_t autopoll;
 118     uint8_t data_in[128];
 119     uint8_t data_out[16];
 120 } CUDAState;
 121
 122 static CUDAState cuda_state;
 123 ADBBusState adb_bus;
 124
 125 static void cuda_update(CUDAState *s);
 126 static void cuda_receive_packet_from_host(CUDAState *s,
 127                                           const uint8_t *data, int len);
 128
 129 static void cuda_update_irq(CUDAState *s)
 130 {
 131     if (s->ifr & s->ier & SR_INT) {
 132         pic_set_irq(s->irq, 1);
 133     } else {
 134         pic_set_irq(s->irq, 0);
 135     }
 136 }
 137
 138 static unsigned int get_counter(CUDATimer *s)
 139 {
 140     int64_t d;
 141     unsigned int counter;
 142
 143     d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
 144                  CUDA_TIMER_FREQ, ticks_per_sec);
 145     if (d <= s->counter_value) {
 146         counter = d;
 147     } else {
 148         counter = s->latch - 1 - ((d - s->counter_value) % s->latch);
 149     }
 150     return counter;
 151 }
 152
 153 static void set_counter(CUDATimer *s, unsigned int val)
 154 {
 155     s->load_time = qemu_get_clock(vm_clock);
 156     s->counter_value = val;
 157 }
 158
 159 static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
 160 {
 161     int64_t d, next_time, base;
 162     /* current counter value */
 163     d = muldiv64(current_time - s->load_time,
 164                  CUDA_TIMER_FREQ, ticks_per_sec);
 165     if (d <= s->counter_value) {
 166         next_time = s->counter_value + 1;
 167     } else {
 168         base = ((d - s->counter_value) % s->latch);
 169         base = (base * s->latch) + s->counter_value;
 170         next_time = base + s->latch;
 171     }
 172     next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
 173         s->load_time;
 174     if (next_time <= current_time)
 175         next_time = current_time + 1;
 176     return next_time;
 177 }
 178
 179 static void cuda_timer1(void *opaque)
 180 {
 181     CUDAState *s = opaque;
 182     CUDATimer *ti = &s->timers[0];
 183
 184     ti->next_irq_time = get_next_irq_time(ti, ti->next_irq_time);
 185     qemu_mod_timer(ti->timer, ti->next_irq_time);
 186     s->ifr |= T1_INT;
 187     cuda_update_irq(s);
 188 }
 189
 190 static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
 191 {
 192     CUDAState *s = opaque;
 193     uint32_t val;
 194
 195     addr = (addr >> 9) & 0xf;
 196     switch(addr) {
 197     case 0:
 198         val = s->b;
 199         break;
 200     case 1:
 201         val = s->a;
 202         break;
 203     case 2:
 204         val = s->dirb;
 205         break;
 206     case 3:
 207         val = s->dira;
 208         break;
 209     case 4:
 210         val = get_counter(&s->timers[0]) & 0xff;
 211         s->ifr &= ~T1_INT;
 212         cuda_update_irq(s);
 213         break;
 214     case 5:
 215         val = get_counter(&s->timers[0]) >> 8;
 216         s->ifr &= ~T1_INT;
 217         cuda_update_irq(s);
 218         break;
 219     case 6:
 220         val = s->timers[0].latch & 0xff;
 221         break;
 222     case 7:
 223         val = (s->timers[0].latch >> 8) & 0xff;
 224         break;
 225     case 8:
 226         val = get_counter(&s->timers[1]) & 0xff;
 227         break;
 228     case 9:
 229         val = get_counter(&s->timers[1]) >> 8;
 230         break;
 231     case 10:
 232         if (s->data_in_index < s->data_in_size) {
 233             val = s->data_in[s->data_in_index];
 234         } else {
 235             val = 0;
 236         }
 237         break;
 238     case 11:
 239         val = s->acr;
 240         break;
 241     case 12:
 242         val = s->pcr;
 243         break;
 244     case 13:
 245         val = s->ifr;
 246         break;
 247     case 14:
 248         val = s->ier;
 249         break;
 250     default:
 251     case 15:
 252         val = s->anh;
 253         break;
 254     }
 255 #ifdef DEBUG_CUDA
 256     printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
 257 #endif
 258     return val;
 259 }
 260
 261 static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 262 {
 263     CUDAState *s = opaque;
 264
 265     addr = (addr >> 9) & 0xf;
 266 #ifdef DEBUG_CUDA
 267     printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
 268 #endif
 269
 270     switch(addr) {
 271     case 0:
 272         s->b = val;
 273         cuda_update(s);
 274         break;
 275     case 1:
 276         s->a = val;
 277         break;
 278     case 2:
 279         s->dirb = val;
 280         break;
 281     case 3:
 282         s->dira = val;
 283         break;
 284     case 4:
 285         val = val | (get_counter(&s->timers[0]) & 0xff00);
 286         set_counter(&s->timers[0], val);
 287         break;
 288     case 5:
 289         val = (val << 8) |  (get_counter(&s->timers[0]) & 0xff);
 290         set_counter(&s->timers[0], val);
 291         break;
 292     case 6:
 293         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 294         break;
 295     case 7:
 296         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 297         break;
 298     case 8:
 299         val = val | (get_counter(&s->timers[1]) & 0xff00);
 300         set_counter(&s->timers[1], val);
 301         break;
 302     case 9:
 303         val = (val << 8) |  (get_counter(&s->timers[1]) & 0xff);
 304         set_counter(&s->timers[1], val);
 305         break;
 306     case 10:
 307         s->sr = val;
 308         break;
 309     case 11:
 310         s->acr = val;
 311         if ((s->acr & T1MODE) == T1MODE_CONT) {
 312             if ((s->last_acr & T1MODE) != T1MODE_CONT) {
 313                 CUDATimer *ti = &s->timers[0];
 314                 /* activate timer interrupt */
 315                 ti->next_irq_time = get_next_irq_time(ti, qemu_get_clock(vm_clock));
 316                 qemu_mod_timer(ti->timer, ti->next_irq_time);
 317             }
 318         } else {
 319             if ((s->last_acr & T1MODE) == T1MODE_CONT) {
 320                 CUDATimer *ti = &s->timers[0];
 321                 qemu_del_timer(ti->timer);
 322             }
 323         }
 324         cuda_update(s);
 325         break;
 326     case 12:
 327         s->pcr = val;
 328         break;
 329     case 13:
 330         /* reset bits */
 331         s->ifr &= ~val;
 332         cuda_update_irq(s);
 333         break;
 334     case 14:
 335         if (val & IER_SET) {
 336             /* set bits */
 337             s->ier |= val & 0x7f;
 338         } else {
 339             /* reset bits */
 340             s->ier &= ~val;
 341         }
 342         cuda_update_irq(s);
 343         break;
 344     default:
 345     case 15:
 346         s->anh = val;
 347         break;
 348     }
 349 }
 350
 351 /* NOTE: TIP and TREQ are negated */
 352 static void cuda_update(CUDAState *s)
 353 {
 354     if (s->data_in_index < s->data_in_size) {
 355         /* data input */
 356         if (!(s->b & TIP) &&
 357             (s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
 358             s->sr = s->data_in[s->data_in_index++];
 359             s->ifr |= SR_INT;
 360             cuda_update_irq(s);
 361         }
 362     }
 363     if (s->data_in_index < s->data_in_size) {
 364         /* there is some data to read */
 365         s->b = (s->b & ~TREQ);
 366     } else {
 367         s->b = (s->b | TREQ);
 368     }
 369
 370     if (s->acr & SR_OUT) {
 371         /* data output */
 372         if (!(s->b & TIP) &&
 373             (s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
 374             if (s->data_out_index < sizeof(s->data_out)) {
 375                 s->data_out[s->data_out_index++] = s->sr;
 376             }
 377             s->ifr |= SR_INT;
 378             cuda_update_irq(s);
 379         }
 380     }
 381
 382     /* check end of data output */
 383     if (!(s->acr & SR_OUT) && (s->last_acr & SR_OUT)) {
 384         if (s->data_out_index > 0)
 385             cuda_receive_packet_from_host(s, s->data_out, s->data_out_index);
 386         s->data_out_index = 0;
 387     }
 388     s->last_acr = s->acr;
 389     s->last_b = s->b;
 390 }
 391
 392 static void cuda_send_packet_to_host(CUDAState *s,
 393                                      const uint8_t *data, int len)
 394 {
 395     memcpy(s->data_in, data, len);
 396     s->data_in_size = len;
 397     s->data_in_index = 0;
 398     cuda_update(s);
 399     s->ifr |= SR_INT;
 400     cuda_update_irq(s);
 401 }
 402
 403 void adb_send_packet(ADBBusState *bus, const uint8_t *buf, int len)
 404 {
 405     CUDAState *s = &cuda_state;
 406     uint8_t data[16];
 407
 408     memcpy(data + 1, buf, len);
 409     data[0] = ADB_PACKET;
 410     cuda_send_packet_to_host(s, data, len + 1);
 411 }
 412
 413 static void cuda_receive_packet(CUDAState *s,
 414                                 const uint8_t *data, int len)
 415 {
 416     uint8_t obuf[16];
 417     int ti;
 418
 419     switch(data[0]) {
 420     case CUDA_AUTOPOLL:
 421         s->autopoll = data[1];
 422         obuf[0] = CUDA_PACKET;
 423         obuf[1] = data[1];
 424         cuda_send_packet_to_host(s, obuf, 2);
 425         break;
 426     case CUDA_GET_TIME:
 427         /* XXX: add time support ? */
 428         ti = 0;
 429         obuf[0] = CUDA_PACKET;
 430         obuf[1] = 0;
 431         obuf[2] = 0;
 432         obuf[3] = ti >> 24;
 433         obuf[4] = ti >> 16;
 434         obuf[5] = ti >> 8;
 435         obuf[6] = ti;
 436         cuda_send_packet_to_host(s, obuf, 7);
 437         break;
 438     case CUDA_SET_TIME:
 439     case CUDA_FILE_SERVER_FLAG:
 440     case CUDA_SET_DEVICE_LIST:
 441     case CUDA_SET_AUTO_RATE:
 442     case CUDA_SET_POWER_MESSAGES:
 443         obuf[0] = CUDA_PACKET;
 444         obuf[1] = 0;
 445         cuda_send_packet_to_host(s, obuf, 2);
 446         break;
 447     default:
 448         break;
 449     }
 450 }
 451
 452 static void cuda_receive_packet_from_host(CUDAState *s,
 453                                           const uint8_t *data, int len)
 454 {
 455     switch(data[0]) {
 456     case ADB_PACKET:
 457         adb_receive_packet(&adb_bus, data + 1, len - 1);
 458         break;
 459     case CUDA_PACKET:
 460         cuda_receive_packet(s, data + 1, len - 1);
 461         break;
 462     }
 463 }
 464
 465 static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 466 {
 467 }
 468
 469 static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 470 {
 471 }
 472
 473 static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
 474 {
 475     return 0;
 476 }
 477
 478 static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
 479 {
 480     return 0;
 481 }
 482
 483 static CPUWriteMemoryFunc *cuda_write[] = {
 484     &cuda_writeb,
 485     &cuda_writew,
 486     &cuda_writel,
 487 };
 488
 489 static CPUReadMemoryFunc *cuda_read[] = {
 490     &cuda_readb,
 491     &cuda_readw,
 492     &cuda_readl,
 493 };
 494
 495 int cuda_init(void)
 496 {
 497     CUDAState *s = &cuda_state;
 498     int cuda_mem_index;
 499
 500     s->timers[0].latch = 0x10000;
 501     set_counter(&s->timers[0], 0xffff);
 502     s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
 503     s->timers[1].latch = 0x10000;
 504     set_counter(&s->timers[1], 0xffff);
 505     cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
 506     return cuda_mem_index;
 507 }