2 * QEMU ATI SVGA emulation
4 * Copyright (c) 2019 BALATON Zoltan
6 * This work is licensed under the GNU GPL license version 2 or later.
11 * This is very incomplete and only enough for Linux console and some
12 * unaccelerated X output at the moment.
13 * Currently it's little more than a frame buffer with minimal functions,
14 * other more advanced features of the hardware are yet to be implemented.
15 * We only aim for Rage 128 Pro (and some RV100) and 2D only at first,
16 * No 3D at all yet (maybe after 2D works, but feel free to improve it)
19 #include "qemu/osdep.h"
24 #include "qemu/module.h"
25 #include "qemu/error-report.h"
26 #include "qapi/error.h"
27 #include "ui/console.h"
28 #include "hw/display/i2c-ddc.h"
31 #define ATI_DEBUG_HW_CURSOR 0
36 } ati_model_aliases
[] = {
37 { "rage128p", PCI_DEVICE_ID_ATI_RAGE128_PF
},
38 { "rv100", PCI_DEVICE_ID_ATI_RADEON_QY
},
41 enum { VGA_MODE
, EXT_MODE
};
43 static void ati_vga_switch_mode(ATIVGAState
*s
)
46 s
->mode
, !!(s
->regs
.crtc_gen_cntl
& CRTC2_EXT_DISP_EN
));
47 if (s
->regs
.crtc_gen_cntl
& CRTC2_EXT_DISP_EN
) {
48 /* Extended mode enabled */
50 if (s
->regs
.crtc_gen_cntl
& CRTC2_EN
) {
51 /* CRT controller enabled, use CRTC values */
52 uint32_t offs
= s
->regs
.crtc_offset
& 0x07ffffff;
53 int stride
= (s
->regs
.crtc_pitch
& 0x7ff) * 8;
57 if (s
->regs
.crtc_h_total_disp
== 0) {
58 s
->regs
.crtc_h_total_disp
= ((640 / 8) - 1) << 16;
60 if (s
->regs
.crtc_v_total_disp
== 0) {
61 s
->regs
.crtc_v_total_disp
= (480 - 1) << 16;
63 h
= ((s
->regs
.crtc_h_total_disp
>> 16) + 1) * 8;
64 v
= (s
->regs
.crtc_v_total_disp
>> 16) + 1;
65 switch (s
->regs
.crtc_gen_cntl
& CRTC_PIX_WIDTH_MASK
) {
66 case CRTC_PIX_WIDTH_4BPP
:
69 case CRTC_PIX_WIDTH_8BPP
:
72 case CRTC_PIX_WIDTH_15BPP
:
75 case CRTC_PIX_WIDTH_16BPP
:
78 case CRTC_PIX_WIDTH_24BPP
:
81 case CRTC_PIX_WIDTH_32BPP
:
85 qemu_log_mask(LOG_UNIMP
, "Unsupported bpp value\n");
88 DPRINTF("Switching to %dx%d %d %d @ %x\n", h
, v
, stride
, bpp
, offs
);
89 vbe_ioport_write_index(&s
->vga
, 0, VBE_DISPI_INDEX_ENABLE
);
90 vbe_ioport_write_data(&s
->vga
, 0, VBE_DISPI_DISABLED
);
91 s
->vga
.big_endian_fb
= false;
92 /* reset VBE regs then set up mode */
93 s
->vga
.vbe_regs
[VBE_DISPI_INDEX_XRES
] = h
;
94 s
->vga
.vbe_regs
[VBE_DISPI_INDEX_YRES
] = v
;
95 s
->vga
.vbe_regs
[VBE_DISPI_INDEX_BPP
] = bpp
;
96 /* enable mode via ioport so it updates vga regs */
97 vbe_ioport_write_index(&s
->vga
, 0, VBE_DISPI_INDEX_ENABLE
);
98 vbe_ioport_write_data(&s
->vga
, 0, VBE_DISPI_ENABLED
|
99 VBE_DISPI_LFB_ENABLED
| VBE_DISPI_NOCLEARMEM
|
100 (s
->regs
.dac_cntl
& DAC_8BIT_EN
? VBE_DISPI_8BIT_DAC
: 0));
101 /* now set offset and stride after enable as that resets these */
103 vbe_ioport_write_index(&s
->vga
, 0, VBE_DISPI_INDEX_VIRT_WIDTH
);
104 vbe_ioport_write_data(&s
->vga
, 0, stride
);
105 if (offs
% stride
== 0) {
106 vbe_ioport_write_index(&s
->vga
, 0, VBE_DISPI_INDEX_Y_OFFSET
);
107 vbe_ioport_write_data(&s
->vga
, 0, offs
/ stride
);
109 /* FIXME what to do with this? */
110 error_report("VGA offset is not multiple of pitch, "
111 "expect bad picture");
116 /* VGA mode enabled */
118 vbe_ioport_write_index(&s
->vga
, 0, VBE_DISPI_INDEX_ENABLE
);
119 vbe_ioport_write_data(&s
->vga
, 0, VBE_DISPI_DISABLED
);
123 /* Used by host side hardware cursor */
124 static void ati_cursor_define(ATIVGAState
*s
)
130 if ((s
->regs
.cur_offset
& BIT(31)) || s
->cursor_guest_mode
) {
131 return; /* Do not update cursor if locked or rendered by guest */
133 /* FIXME handle cur_hv_offs correctly */
134 src
= s
->vga
.vram_ptr
+ (s
->regs
.crtc_offset
& 0x07ffffff) +
135 s
->regs
.cur_offset
- (s
->regs
.cur_hv_offs
>> 16) -
136 (s
->regs
.cur_hv_offs
& 0xffff) * 16;
137 for (i
= 0; i
< 64; i
++) {
138 for (j
= 0; j
< 8; j
++, idx
++) {
139 data
[idx
] = src
[i
* 16 + j
];
140 data
[512 + idx
] = src
[i
* 16 + j
+ 8];
144 s
->cursor
= cursor_alloc(64, 64);
146 cursor_set_mono(s
->cursor
, s
->regs
.cur_color1
, s
->regs
.cur_color0
,
147 &data
[512], 1, &data
[0]);
148 dpy_cursor_define(s
->vga
.con
, s
->cursor
);
151 /* Alternatively support guest rendered hardware cursor */
152 static void ati_cursor_invalidate(VGACommonState
*vga
)
154 ATIVGAState
*s
= container_of(vga
, ATIVGAState
, vga
);
155 int size
= (s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
) ? 64 : 0;
157 if (s
->regs
.cur_offset
& BIT(31)) {
158 return; /* Do not update cursor if locked */
160 if (s
->cursor_size
!= size
||
161 vga
->hw_cursor_x
!= s
->regs
.cur_hv_pos
>> 16 ||
162 vga
->hw_cursor_y
!= (s
->regs
.cur_hv_pos
& 0xffff) ||
163 s
->cursor_offset
!= s
->regs
.cur_offset
- (s
->regs
.cur_hv_offs
>> 16) -
164 (s
->regs
.cur_hv_offs
& 0xffff) * 16) {
165 /* Remove old cursor then update and show new one if needed */
166 vga_invalidate_scanlines(vga
, vga
->hw_cursor_y
, vga
->hw_cursor_y
+ 63);
167 vga
->hw_cursor_x
= s
->regs
.cur_hv_pos
>> 16;
168 vga
->hw_cursor_y
= s
->regs
.cur_hv_pos
& 0xffff;
169 s
->cursor_offset
= s
->regs
.cur_offset
- (s
->regs
.cur_hv_offs
>> 16) -
170 (s
->regs
.cur_hv_offs
& 0xffff) * 16;
171 s
->cursor_size
= size
;
173 vga_invalidate_scanlines(vga
,
174 vga
->hw_cursor_y
, vga
->hw_cursor_y
+ 63);
179 static void ati_cursor_draw_line(VGACommonState
*vga
, uint8_t *d
, int scr_y
)
181 ATIVGAState
*s
= container_of(vga
, ATIVGAState
, vga
);
183 uint32_t *dp
= (uint32_t *)d
;
186 if (!(s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
) ||
187 scr_y
< vga
->hw_cursor_y
|| scr_y
>= vga
->hw_cursor_y
+ 64 ||
188 scr_y
> s
->regs
.crtc_v_total_disp
>> 16) {
191 /* FIXME handle cur_hv_offs correctly */
192 src
= s
->vga
.vram_ptr
+ (s
->regs
.crtc_offset
& 0x07ffffff) +
193 s
->cursor_offset
+ (scr_y
- vga
->hw_cursor_y
) * 16;
194 dp
= &dp
[vga
->hw_cursor_x
];
195 h
= ((s
->regs
.crtc_h_total_disp
>> 16) + 1) * 8;
196 for (i
= 0; i
< 8; i
++) {
198 uint8_t abits
= src
[i
];
199 uint8_t xbits
= src
[i
+ 8];
200 for (j
= 0; j
< 8; j
++, abits
<<= 1, xbits
<<= 1) {
201 if (abits
& BIT(7)) {
202 if (xbits
& BIT(7)) {
203 color
= dp
[i
* 8 + j
] ^ 0xffffffff; /* complement */
205 continue; /* transparent, no change */
208 color
= (xbits
& BIT(7) ? s
->regs
.cur_color1
:
209 s
->regs
.cur_color0
) << 8 | 0xff;
211 if (vga
->hw_cursor_x
+ i
* 8 + j
>= h
) {
212 return; /* end of screen, don't span to next line */
214 dp
[i
* 8 + j
] = color
;
219 static uint64_t ati_i2c(bitbang_i2c_interface
*i2c
, uint64_t data
, int base
)
221 bool c
= (data
& BIT(base
+ 17) ? !!(data
& BIT(base
+ 1)) : 1);
222 bool d
= (data
& BIT(base
+ 16) ? !!(data
& BIT(base
)) : 1);
224 bitbang_i2c_set(i2c
, BITBANG_I2C_SCL
, c
);
225 d
= bitbang_i2c_set(i2c
, BITBANG_I2C_SDA
, d
);
229 data
|= BIT(base
+ 9);
232 data
|= BIT(base
+ 8);
237 static inline uint64_t ati_reg_read_offs(uint32_t reg
, int offs
,
240 if (offs
== 0 && size
== 4) {
243 return extract32(reg
, offs
* BITS_PER_BYTE
, size
* BITS_PER_BYTE
);
247 static uint64_t ati_mm_read(void *opaque
, hwaddr addr
, unsigned int size
)
249 ATIVGAState
*s
= opaque
;
254 val
= s
->regs
.mm_index
;
256 case MM_DATA
... MM_DATA
+ 3:
257 /* indexed access to regs or memory */
258 if (s
->regs
.mm_index
& BIT(31)) {
259 uint32_t idx
= s
->regs
.mm_index
& ~BIT(31);
260 if (idx
<= s
->vga
.vram_size
- size
) {
261 val
= ldn_le_p(s
->vga
.vram_ptr
+ idx
, size
);
264 val
= ati_mm_read(s
, s
->regs
.mm_index
+ addr
- MM_DATA
, size
);
267 case BIOS_0_SCRATCH
... BUS_CNTL
- 1:
269 int i
= (addr
- BIOS_0_SCRATCH
) / 4;
270 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
&& i
> 3) {
273 val
= ati_reg_read_offs(s
->regs
.bios_scratch
[i
],
274 addr
- (BIOS_0_SCRATCH
+ i
* 4), size
);
277 case CRTC_GEN_CNTL
... CRTC_GEN_CNTL
+ 3:
278 val
= ati_reg_read_offs(s
->regs
.crtc_gen_cntl
,
279 addr
- CRTC_GEN_CNTL
, size
);
281 case CRTC_EXT_CNTL
... CRTC_EXT_CNTL
+ 3:
282 val
= ati_reg_read_offs(s
->regs
.crtc_ext_cntl
,
283 addr
- CRTC_EXT_CNTL
, size
);
286 val
= s
->regs
.dac_cntl
;
289 val
= s
->regs
.gpio_vga_ddc
;
292 val
= s
->regs
.gpio_dvi_ddc
;
294 case GPIO_MONID
... GPIO_MONID
+ 3:
295 val
= ati_reg_read_offs(s
->regs
.gpio_monid
,
296 addr
- GPIO_MONID
, size
);
299 /* FIXME unaligned access */
300 val
= vga_ioport_read(&s
->vga
, VGA_PEL_IR
) << 16;
301 val
|= vga_ioport_read(&s
->vga
, VGA_PEL_IW
) & 0xff;
304 val
= vga_ioport_read(&s
->vga
, VGA_PEL_D
);
307 val
= s
->vga
.vram_size
;
314 val
= 64; /* free CMDFIFO entries */
316 case CRTC_H_TOTAL_DISP
:
317 val
= s
->regs
.crtc_h_total_disp
;
319 case CRTC_H_SYNC_STRT_WID
:
320 val
= s
->regs
.crtc_h_sync_strt_wid
;
322 case CRTC_V_TOTAL_DISP
:
323 val
= s
->regs
.crtc_v_total_disp
;
325 case CRTC_V_SYNC_STRT_WID
:
326 val
= s
->regs
.crtc_v_sync_strt_wid
;
329 val
= s
->regs
.crtc_offset
;
331 case CRTC_OFFSET_CNTL
:
332 val
= s
->regs
.crtc_offset_cntl
;
335 val
= s
->regs
.crtc_pitch
;
337 case 0xf00 ... 0xfff:
338 val
= pci_default_read_config(&s
->dev
, addr
- 0xf00, size
);
341 val
= s
->regs
.cur_offset
;
343 case CUR_HORZ_VERT_POSN
:
344 val
= s
->regs
.cur_hv_pos
;
345 val
|= s
->regs
.cur_offset
& BIT(31);
347 case CUR_HORZ_VERT_OFF
:
348 val
= s
->regs
.cur_hv_offs
;
349 val
|= s
->regs
.cur_offset
& BIT(31);
352 val
= s
->regs
.cur_color0
;
355 val
= s
->regs
.cur_color1
;
358 val
= s
->regs
.dst_offset
;
361 val
= s
->regs
.dst_pitch
;
362 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
363 val
&= s
->regs
.dst_tile
<< 16;
367 val
= s
->regs
.dst_width
;
370 val
= s
->regs
.dst_height
;
384 case DP_GUI_MASTER_CNTL
:
385 val
= s
->regs
.dp_gui_master_cntl
;
388 val
= s
->regs
.src_offset
;
391 val
= s
->regs
.src_pitch
;
392 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
393 val
&= s
->regs
.src_tile
<< 16;
396 case DP_BRUSH_BKGD_CLR
:
397 val
= s
->regs
.dp_brush_bkgd_clr
;
399 case DP_BRUSH_FRGD_CLR
:
400 val
= s
->regs
.dp_brush_frgd_clr
;
402 case DP_SRC_FRGD_CLR
:
403 val
= s
->regs
.dp_src_frgd_clr
;
405 case DP_SRC_BKGD_CLR
:
406 val
= s
->regs
.dp_src_bkgd_clr
;
409 val
= s
->regs
.dp_cntl
;
412 val
= s
->regs
.dp_datatype
;
415 val
= s
->regs
.dp_mix
;
418 val
= s
->regs
.dp_write_mask
;
421 val
= s
->regs
.default_offset
;
422 if (s
->dev_id
!= PCI_DEVICE_ID_ATI_RAGE128_PF
) {
424 val
|= s
->regs
.default_pitch
<< 16;
425 val
|= s
->regs
.default_tile
<< 30;
429 val
= s
->regs
.default_pitch
;
430 val
|= s
->regs
.default_tile
<< 16;
432 case DEFAULT_SC_BOTTOM_RIGHT
:
433 val
= s
->regs
.default_sc_bottom_right
;
438 if (addr
< CUR_OFFSET
|| addr
> CUR_CLR1
|| ATI_DEBUG_HW_CURSOR
) {
439 trace_ati_mm_read(size
, addr
, ati_reg_name(addr
& ~3ULL), val
);
444 static inline void ati_reg_write_offs(uint32_t *reg
, int offs
,
445 uint64_t data
, unsigned int size
)
447 if (offs
== 0 && size
== 4) {
450 *reg
= deposit32(*reg
, offs
* BITS_PER_BYTE
, size
* BITS_PER_BYTE
,
455 static void ati_mm_write(void *opaque
, hwaddr addr
,
456 uint64_t data
, unsigned int size
)
458 ATIVGAState
*s
= opaque
;
460 if (addr
< CUR_OFFSET
|| addr
> CUR_CLR1
|| ATI_DEBUG_HW_CURSOR
) {
461 trace_ati_mm_write(size
, addr
, ati_reg_name(addr
& ~3ULL), data
);
465 s
->regs
.mm_index
= data
;
467 case MM_DATA
... MM_DATA
+ 3:
468 /* indexed access to regs or memory */
469 if (s
->regs
.mm_index
& BIT(31)) {
470 uint32_t idx
= s
->regs
.mm_index
& ~BIT(31);
471 if (idx
<= s
->vga
.vram_size
- size
) {
472 stn_le_p(s
->vga
.vram_ptr
+ idx
, size
, data
);
475 ati_mm_write(s
, s
->regs
.mm_index
+ addr
- MM_DATA
, data
, size
);
478 case BIOS_0_SCRATCH
... BUS_CNTL
- 1:
480 int i
= (addr
- BIOS_0_SCRATCH
) / 4;
481 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
&& i
> 3) {
484 ati_reg_write_offs(&s
->regs
.bios_scratch
[i
],
485 addr
- (BIOS_0_SCRATCH
+ i
* 4), data
, size
);
488 case CRTC_GEN_CNTL
... CRTC_GEN_CNTL
+ 3:
490 uint32_t val
= s
->regs
.crtc_gen_cntl
;
491 ati_reg_write_offs(&s
->regs
.crtc_gen_cntl
,
492 addr
- CRTC_GEN_CNTL
, data
, size
);
493 if ((val
& CRTC2_CUR_EN
) != (s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
)) {
494 if (s
->cursor_guest_mode
) {
495 s
->vga
.force_shadow
= !!(s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
);
497 if (s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
) {
498 ati_cursor_define(s
);
500 dpy_mouse_set(s
->vga
.con
, s
->regs
.cur_hv_pos
>> 16,
501 s
->regs
.cur_hv_pos
& 0xffff,
502 (s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
) != 0);
505 if ((val
& (CRTC2_EXT_DISP_EN
| CRTC2_EN
)) !=
506 (s
->regs
.crtc_gen_cntl
& (CRTC2_EXT_DISP_EN
| CRTC2_EN
))) {
507 ati_vga_switch_mode(s
);
511 case CRTC_EXT_CNTL
... CRTC_EXT_CNTL
+ 3:
513 uint32_t val
= s
->regs
.crtc_ext_cntl
;
514 ati_reg_write_offs(&s
->regs
.crtc_ext_cntl
,
515 addr
- CRTC_EXT_CNTL
, data
, size
);
516 if (s
->regs
.crtc_ext_cntl
& CRT_CRTC_DISPLAY_DIS
) {
517 DPRINTF("Display disabled\n");
518 s
->vga
.ar_index
&= ~BIT(5);
520 DPRINTF("Display enabled\n");
521 s
->vga
.ar_index
|= BIT(5);
522 ati_vga_switch_mode(s
);
524 if ((val
& CRT_CRTC_DISPLAY_DIS
) !=
525 (s
->regs
.crtc_ext_cntl
& CRT_CRTC_DISPLAY_DIS
)) {
526 ati_vga_switch_mode(s
);
531 s
->regs
.dac_cntl
= data
& 0xffffe3ff;
532 s
->vga
.dac_8bit
= !!(data
& DAC_8BIT_EN
);
535 if (s
->dev_id
!= PCI_DEVICE_ID_ATI_RAGE128_PF
) {
536 /* FIXME: Maybe add a property to select VGA or DVI port? */
540 if (s
->dev_id
!= PCI_DEVICE_ID_ATI_RAGE128_PF
) {
541 s
->regs
.gpio_dvi_ddc
= ati_i2c(&s
->bbi2c
, data
, 0);
544 case GPIO_MONID
... GPIO_MONID
+ 3:
545 /* FIXME What does Radeon have here? */
546 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
547 ati_reg_write_offs(&s
->regs
.gpio_monid
,
548 addr
- GPIO_MONID
, data
, size
);
550 * Rage128p accesses DDC used to get EDID via these bits.
551 * Only touch i2c when write overlaps 3rd byte because some
552 * drivers access this reg via multiple partial writes and
553 * without this spurious bits would be sent.
555 if ((s
->regs
.gpio_monid
& BIT(25)) &&
556 addr
<= GPIO_MONID
+ 2 && addr
+ size
> GPIO_MONID
+ 2) {
557 s
->regs
.gpio_monid
= ati_i2c(&s
->bbi2c
, s
->regs
.gpio_monid
, 1);
561 case PALETTE_INDEX
... PALETTE_INDEX
+ 3:
563 vga_ioport_write(&s
->vga
, VGA_PEL_IR
, (data
>> 16) & 0xff);
564 vga_ioport_write(&s
->vga
, VGA_PEL_IW
, data
& 0xff);
566 if (addr
== PALETTE_INDEX
) {
567 vga_ioport_write(&s
->vga
, VGA_PEL_IW
, data
& 0xff);
569 vga_ioport_write(&s
->vga
, VGA_PEL_IR
, data
& 0xff);
573 case PALETTE_DATA
... PALETTE_DATA
+ 3:
574 data
<<= addr
- PALETTE_DATA
;
575 data
= bswap32(data
) >> 8;
576 vga_ioport_write(&s
->vga
, VGA_PEL_D
, data
& 0xff);
578 vga_ioport_write(&s
->vga
, VGA_PEL_D
, data
& 0xff);
580 vga_ioport_write(&s
->vga
, VGA_PEL_D
, data
& 0xff);
582 case CRTC_H_TOTAL_DISP
:
583 s
->regs
.crtc_h_total_disp
= data
& 0x07ff07ff;
585 case CRTC_H_SYNC_STRT_WID
:
586 s
->regs
.crtc_h_sync_strt_wid
= data
& 0x17bf1fff;
588 case CRTC_V_TOTAL_DISP
:
589 s
->regs
.crtc_v_total_disp
= data
& 0x0fff0fff;
591 case CRTC_V_SYNC_STRT_WID
:
592 s
->regs
.crtc_v_sync_strt_wid
= data
& 0x9f0fff;
595 s
->regs
.crtc_offset
= data
& 0xc7ffffff;
597 case CRTC_OFFSET_CNTL
:
598 s
->regs
.crtc_offset_cntl
= data
; /* FIXME */
601 s
->regs
.crtc_pitch
= data
& 0x07ff07ff;
603 case 0xf00 ... 0xfff:
604 /* read-only copy of PCI config space so ignore writes */
607 if (s
->regs
.cur_offset
!= (data
& 0x87fffff0)) {
608 s
->regs
.cur_offset
= data
& 0x87fffff0;
609 ati_cursor_define(s
);
612 case CUR_HORZ_VERT_POSN
:
613 s
->regs
.cur_hv_pos
= data
& 0x3fff0fff;
614 if (data
& BIT(31)) {
615 s
->regs
.cur_offset
|= data
& BIT(31);
616 } else if (s
->regs
.cur_offset
& BIT(31)) {
617 s
->regs
.cur_offset
&= ~BIT(31);
618 ati_cursor_define(s
);
620 if (!s
->cursor_guest_mode
&&
621 (s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
) && !(data
& BIT(31))) {
622 dpy_mouse_set(s
->vga
.con
, s
->regs
.cur_hv_pos
>> 16,
623 s
->regs
.cur_hv_pos
& 0xffff, 1);
626 case CUR_HORZ_VERT_OFF
:
627 s
->regs
.cur_hv_offs
= data
& 0x3f003f;
628 if (data
& BIT(31)) {
629 s
->regs
.cur_offset
|= data
& BIT(31);
630 } else if (s
->regs
.cur_offset
& BIT(31)) {
631 s
->regs
.cur_offset
&= ~BIT(31);
632 ati_cursor_define(s
);
636 if (s
->regs
.cur_color0
!= (data
& 0xffffff)) {
637 s
->regs
.cur_color0
= data
& 0xffffff;
638 ati_cursor_define(s
);
643 * Update cursor unconditionally here because some clients set up
644 * other registers before actually writing cursor data to memory at
645 * offset so we would miss cursor change unless always updating here
647 s
->regs
.cur_color1
= data
& 0xffffff;
648 ati_cursor_define(s
);
651 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
652 s
->regs
.dst_offset
= data
& 0xfffffff0;
654 s
->regs
.dst_offset
= data
& 0xfffffc00;
658 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
659 s
->regs
.dst_pitch
= data
& 0x3fff;
660 s
->regs
.dst_tile
= (data
>> 16) & 1;
662 s
->regs
.dst_pitch
= data
& 0x3ff0;
666 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RADEON_QY
) {
667 s
->regs
.dst_tile
= data
& 3;
671 s
->regs
.dst_width
= data
& 0x3fff;
675 s
->regs
.dst_height
= data
& 0x3fff;
678 s
->regs
.src_x
= data
& 0x3fff;
681 s
->regs
.src_y
= data
& 0x3fff;
684 s
->regs
.dst_x
= data
& 0x3fff;
687 s
->regs
.dst_y
= data
& 0x3fff;
689 case SRC_PITCH_OFFSET
:
690 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
691 s
->regs
.src_offset
= (data
& 0x1fffff) << 5;
692 s
->regs
.src_pitch
= (data
& 0x7fe00000) >> 21;
693 s
->regs
.src_tile
= data
>> 31;
695 s
->regs
.src_offset
= (data
& 0x3fffff) << 10;
696 s
->regs
.src_pitch
= (data
& 0x3fc00000) >> 16;
697 s
->regs
.src_tile
= (data
>> 30) & 1;
700 case DST_PITCH_OFFSET
:
701 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
702 s
->regs
.dst_offset
= (data
& 0x1fffff) << 5;
703 s
->regs
.dst_pitch
= (data
& 0x7fe00000) >> 21;
704 s
->regs
.dst_tile
= data
>> 31;
706 s
->regs
.dst_offset
= (data
& 0x3fffff) << 10;
707 s
->regs
.dst_pitch
= (data
& 0x3fc00000) >> 16;
708 s
->regs
.dst_tile
= data
>> 30;
712 s
->regs
.src_x
= data
& 0x3fff;
713 s
->regs
.src_y
= (data
>> 16) & 0x3fff;
716 s
->regs
.dst_x
= data
& 0x3fff;
717 s
->regs
.dst_y
= (data
>> 16) & 0x3fff;
719 case DST_HEIGHT_WIDTH
:
720 s
->regs
.dst_width
= data
& 0x3fff;
721 s
->regs
.dst_height
= (data
>> 16) & 0x3fff;
724 case DP_GUI_MASTER_CNTL
:
725 s
->regs
.dp_gui_master_cntl
= data
& 0xf800000f;
726 s
->regs
.dp_datatype
= (data
& 0x0f00) >> 8 | (data
& 0x30f0) << 4 |
727 (data
& 0x4000) << 16;
728 s
->regs
.dp_mix
= (data
& GMC_ROP3_MASK
) | (data
& 0x7000000) >> 16;
731 s
->regs
.dst_x
= data
& 0x3fff;
732 s
->regs
.dst_width
= (data
>> 16) & 0x3fff;
736 s
->regs
.src_y
= data
& 0x3fff;
737 s
->regs
.src_x
= (data
>> 16) & 0x3fff;
740 s
->regs
.dst_y
= data
& 0x3fff;
741 s
->regs
.dst_x
= (data
>> 16) & 0x3fff;
743 case DST_WIDTH_HEIGHT
:
744 s
->regs
.dst_height
= data
& 0x3fff;
745 s
->regs
.dst_width
= (data
>> 16) & 0x3fff;
749 s
->regs
.dst_y
= data
& 0x3fff;
750 s
->regs
.dst_height
= (data
>> 16) & 0x3fff;
753 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
754 s
->regs
.src_offset
= data
& 0xfffffff0;
756 s
->regs
.src_offset
= data
& 0xfffffc00;
760 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
761 s
->regs
.src_pitch
= data
& 0x3fff;
762 s
->regs
.src_tile
= (data
>> 16) & 1;
764 s
->regs
.src_pitch
= data
& 0x3ff0;
767 case DP_BRUSH_BKGD_CLR
:
768 s
->regs
.dp_brush_bkgd_clr
= data
;
770 case DP_BRUSH_FRGD_CLR
:
771 s
->regs
.dp_brush_frgd_clr
= data
;
774 s
->regs
.dp_cntl
= data
;
777 s
->regs
.dp_datatype
= data
& 0xe0070f0f;
780 s
->regs
.dp_mix
= data
& 0x00ff0700;
783 s
->regs
.dp_write_mask
= data
;
786 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
787 s
->regs
.default_offset
= data
& 0xfffffff0;
789 /* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET */
790 s
->regs
.default_offset
= (data
& 0x3fffff) << 10;
791 s
->regs
.default_pitch
= (data
& 0x3fc00000) >> 16;
792 s
->regs
.default_tile
= data
>> 30;
796 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
797 s
->regs
.default_pitch
= data
& 0x3fff;
798 s
->regs
.default_tile
= (data
>> 16) & 1;
801 case DEFAULT_SC_BOTTOM_RIGHT
:
802 s
->regs
.default_sc_bottom_right
= data
& 0x3fff3fff;
809 static const MemoryRegionOps ati_mm_ops
= {
811 .write
= ati_mm_write
,
812 .endianness
= DEVICE_LITTLE_ENDIAN
,
815 static void ati_vga_realize(PCIDevice
*dev
, Error
**errp
)
817 ATIVGAState
*s
= ATI_VGA(dev
);
818 VGACommonState
*vga
= &s
->vga
;
822 for (i
= 0; i
< ARRAY_SIZE(ati_model_aliases
); i
++) {
823 if (!strcmp(s
->model
, ati_model_aliases
[i
].name
)) {
824 s
->dev_id
= ati_model_aliases
[i
].dev_id
;
828 if (i
>= ARRAY_SIZE(ati_model_aliases
)) {
829 warn_report("Unknown ATI VGA model name, "
830 "using default rage128p");
833 if (s
->dev_id
!= PCI_DEVICE_ID_ATI_RAGE128_PF
&&
834 s
->dev_id
!= PCI_DEVICE_ID_ATI_RADEON_QY
) {
835 error_setg(errp
, "Unknown ATI VGA device id, "
836 "only 0x5046 and 0x5159 are supported");
839 pci_set_word(dev
->config
+ PCI_DEVICE_ID
, s
->dev_id
);
841 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RADEON_QY
&&
842 s
->vga
.vram_size_mb
< 16) {
843 warn_report("Too small video memory for device id");
844 s
->vga
.vram_size_mb
= 16;
848 vga_common_init(vga
, OBJECT(s
));
849 vga_init(vga
, OBJECT(s
), pci_address_space(dev
),
850 pci_address_space_io(dev
), true);
851 vga
->con
= graphic_console_init(DEVICE(s
), 0, s
->vga
.hw_ops
, &s
->vga
);
852 if (s
->cursor_guest_mode
) {
853 vga
->cursor_invalidate
= ati_cursor_invalidate
;
854 vga
->cursor_draw_line
= ati_cursor_draw_line
;
858 I2CBus
*i2cbus
= i2c_init_bus(DEVICE(s
), "ati-vga.ddc");
859 bitbang_i2c_init(&s
->bbi2c
, i2cbus
);
860 I2CSlave
*i2cddc
= I2C_SLAVE(qdev_create(BUS(i2cbus
), TYPE_I2CDDC
));
861 i2c_set_slave_address(i2cddc
, 0x50);
863 /* mmio register space */
864 memory_region_init_io(&s
->mm
, OBJECT(s
), &ati_mm_ops
, s
,
865 "ati.mmregs", 0x4000);
866 /* io space is alias to beginning of mmregs */
867 memory_region_init_alias(&s
->io
, OBJECT(s
), "ati.io", &s
->mm
, 0, 0x100);
869 pci_register_bar(dev
, 0, PCI_BASE_ADDRESS_MEM_PREFETCH
, &vga
->vram
);
870 pci_register_bar(dev
, 1, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io
);
871 pci_register_bar(dev
, 2, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->mm
);
874 static void ati_vga_reset(DeviceState
*dev
)
876 ATIVGAState
*s
= ATI_VGA(dev
);
879 vga_common_reset(&s
->vga
);
883 static void ati_vga_exit(PCIDevice
*dev
)
885 ATIVGAState
*s
= ATI_VGA(dev
);
887 graphic_console_close(s
->vga
.con
);
890 static Property ati_vga_properties
[] = {
891 DEFINE_PROP_UINT32("vgamem_mb", ATIVGAState
, vga
.vram_size_mb
, 16),
892 DEFINE_PROP_STRING("model", ATIVGAState
, model
),
893 DEFINE_PROP_UINT16("x-device-id", ATIVGAState
, dev_id
,
894 PCI_DEVICE_ID_ATI_RAGE128_PF
),
895 DEFINE_PROP_BOOL("guest_hwcursor", ATIVGAState
, cursor_guest_mode
, false),
896 DEFINE_PROP_END_OF_LIST()
899 static void ati_vga_class_init(ObjectClass
*klass
, void *data
)
901 DeviceClass
*dc
= DEVICE_CLASS(klass
);
902 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
904 dc
->reset
= ati_vga_reset
;
905 dc
->props
= ati_vga_properties
;
906 dc
->hotpluggable
= false;
907 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
909 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
910 k
->vendor_id
= PCI_VENDOR_ID_ATI
;
911 k
->device_id
= PCI_DEVICE_ID_ATI_RAGE128_PF
;
912 k
->romfile
= "vgabios-ati.bin";
913 k
->realize
= ati_vga_realize
;
914 k
->exit
= ati_vga_exit
;
917 static const TypeInfo ati_vga_info
= {
918 .name
= TYPE_ATI_VGA
,
919 .parent
= TYPE_PCI_DEVICE
,
920 .instance_size
= sizeof(ATIVGAState
),
921 .class_init
= ati_vga_class_init
,
922 .interfaces
= (InterfaceInfo
[]) {
923 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
928 static void ati_vga_register_types(void)
930 type_register_static(&ati_vga_info
);
933 type_init(ati_vga_register_types
)